From patchwork Tue Mar 29 18:43:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12795190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A131BC4332F for ; Tue, 29 Mar 2022 18:43:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240646AbiC2Spe (ORCPT ); Tue, 29 Mar 2022 14:45:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234950AbiC2Spd (ORCPT ); Tue, 29 Mar 2022 14:45:33 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39496338A4; Tue, 29 Mar 2022 11:43:49 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a8so36806748ejc.8; Tue, 29 Mar 2022 11:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VMqff0AA4ues5gejWo82ERpXccxpeB9zCdHCRWcLylw=; b=Ro5n3KjVjRw3+k4L60gptenas6QL3UcFcMzVDbvIwdJAEDTRjaS4ve085vhJrtapzy XiZLKb8tjOI+LdDzMfUspzyAHb8rCGjb6CIecLT0UWJBGDzIt7mrso/cjDO95T1B0bgr UusxGBlf6jUUsScu8RuobfVNr2QiRR2hGtNHwdIg7vqIiCJvJId4/nIVhJfeC2729mZW T2GnOsdxqE+k3TVG8EJtzdpzQdVMEn7dhqXdzLXsmeueGeXFlxmNZmFY2S0Ub+peczDB d/QmHEeOGDJLvrL2Bq6Cw6vj60w01yKqwZnrtM3XdAwHVETOlaMicOo3xNTaaqqp8DXt jgsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VMqff0AA4ues5gejWo82ERpXccxpeB9zCdHCRWcLylw=; b=ka0o6ti4HHEK7K0XjFckUWybblWzw93aVMyaIiMPkgW/ADPqarXBd7QO5p3fHB45qX F4QlC1qSw2p+g+x3+I1nayRnY3sIXCxRjltiFH3ZDFdr7OeYcswEGIP2xJwsIkWrytUR K5BK5rb4Bx4k9c2zQVTUqN+sefc7vy1qDV7i0R9fMI7LgBrFwG7k5nxyZbHUMattG/JV e9vJU7rPN4+aJ9XpCE1fhT0o0HdZyn8LHIy/6OOVhnjfy0tgP1CNgQp9rT/drTUMmjJV 0ITXlGFDWE8+hSkpqlXTipBgoQeXCmvm7Fcm35sqyAWh0UcOPkz8QKHwFHAbAOfx+sQi EnqQ== X-Gm-Message-State: AOAM530iXobIYsQRO/QY7xzdi5pogEUhMxSFcSqGXy4YH1feYjN/QbSX zOt/eucXduUa9XXuR0a8hIA= X-Google-Smtp-Source: ABdhPJwEs5t8gHV99e7n5X+AeeylUWh58oZWTzleCryNYu9GZNqAFcGZtF6/9Onh5jQb/4YUIguDYg== X-Received: by 2002:a17:906:c1d6:b0:6d6:e0a3:bbc7 with SMTP id bw22-20020a170906c1d600b006d6e0a3bbc7mr36833053ejb.484.1648579427760; Tue, 29 Mar 2022 11:43:47 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id z12-20020a17090674cc00b006df9afdda91sm7138714ejl.185.2022.03.29.11.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 11:43:47 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML Date: Tue, 29 Mar 2022 20:43:38 +0200 Message-Id: <20220329184339.1134-1-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3308-cru.txt to YAML. Changes against original bindings: - Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/rockchip,rk3308-cru.txt | 60 --------------- .../bindings/clock/rockchip,rk3308-cru.yaml | 76 +++++++++++++++++++ 2 files changed, 76 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt deleted file mode 100644 index 9b151c5b0..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Rockchip RK3308 Clock and Reset Unit - -The RK3308 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: CRU should be "rockchip,rk3308-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in", - "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in", - "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional, - - "mac_clkin" - external MAC clock - optional - -Example: Clock controller node: - - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml new file mode 100644 index 000000000..523ee578a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3308 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3308 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", + "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in", + "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or + SPDIF clock - optional + - "mac_clkin" - external MAC clock - optional + +properties: + compatible: + enum: + - rockchip,rk3308-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff500000 { + compatible = "rockchip,rk3308-cru"; + reg = <0xff500000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Tue Mar 29 18:43:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12795189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E3ACC433EF for ; Tue, 29 Mar 2022 18:43:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240639AbiC2Spe (ORCPT ); Tue, 29 Mar 2022 14:45:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240643AbiC2Spd (ORCPT ); Tue, 29 Mar 2022 14:45:33 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 480A97E595; Tue, 29 Mar 2022 11:43:50 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id x34so21707700ede.8; Tue, 29 Mar 2022 11:43:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xBJkwvNeki5PfTqOsvfJ8a7WGcSaDHdZIXo5PFl9ZH4=; b=Fh+hp3c9C56wxdRXyU/NFIsIQjB5m67Zkizv52Y6yu4n8bg7nWzMMIg2fGM0Y4alnn KxbxZqTc9BYKE1IDQrQjujvTv/4adFFCrpFPT8oq6Ou9IqqiNs2u8aPQY6PhflBxrGnz 0na83mlgrmzHeNCw6AaehTXklkDtbO9uAljp1XyRDJkRUa7e6rjC5wJi8PzE6DGVt72D zNpf9nq94iB7Ulmqbz1rn639u/YnVWavAj7wBxVd2SEt2UZkG5cj0xpB6apRnC5fhe22 75SdMFI0NER9HpiZO0GXG9f6pKkdTHeIDapwWHEQ1OU+eD3fPxorrQ761X5M40La5j7P hsUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xBJkwvNeki5PfTqOsvfJ8a7WGcSaDHdZIXo5PFl9ZH4=; b=QsJHgUPmOw3EqDK88xD9S1RKAwANJI6HmjX2VB9NOxlGapLUeqw2X7V8uHodPzh/WJ Wmp/bf9yuYH5ZoBbgzdz29sr3mH87hrB7j9CgZXFXSe1hZ6tHmS1CRsIwct/PeeNMwNi qe+cT3SClMZa89vDBkM4vmSmmwP2qJ6hRIlf72e84TOjflH5kLg5krG184El7HKEkYC/ hymd+Q+kiJLXUmC5Ls1q7QvVtHuVrHR2YH2lGywfbpVXlpnxI5WjaaugBDawo68eQ400 OEgsydaSqduk5YUDnEKSCQlZO9xNUI//aWb9Qid5Yj3uiOmNja454xAlsF4p7N49ftHx ISAA== X-Gm-Message-State: AOAM530tza6mssgYYkG0rFszAa5iiWlyKgGn5HkVLmD+E4aKPTRx280J mgTQq8SV30ZzCyr11673A0w= X-Google-Smtp-Source: ABdhPJyrlb3mvXOJgIqbuaQuQYalBaoCxOz4mvbsmiTDPBplEVYFMP3StxTyydNuVperBtbUNHBuhQ== X-Received: by 2002:aa7:c748:0:b0:418:f0fb:83a1 with SMTP id c8-20020aa7c748000000b00418f0fb83a1mr6395176eds.350.1648579428630; Tue, 29 Mar 2022 11:43:48 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id z12-20020a17090674cc00b006df9afdda91sm7138714ejl.185.2022.03.29.11.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Mar 2022 11:43:48 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] arm64: rockchip: add clocks property to cru node rk3308 Date: Tue, 29 Mar 2022 20:43:39 +0200 Message-Id: <20220329184339.1134-2-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220329184339.1134-1-jbx6244@gmail.com> References: <20220329184339.1134-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add clocks and clock-names to the rk3308 cru node, because the device has to have at least one input clock. Also in case someone wants to add properties that start with assign-xxx to fix warnings like: 'clocks' is a dependency of 'assigned-clocks' With the addition of new properties also sort the node properties a little bit. Signed-off-by: Johan Jonker --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 1cbe21261..2dfa67f1c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -745,10 +745,11 @@ cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - rockchip,grf = <&grf>; - assigned-clocks = <&cru SCLK_RTC32K>; assigned-clock-rates = <32768>; };