From patchwork Wed Mar 30 10:39:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12795670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54049C433F5 for ; Wed, 30 Mar 2022 10:39:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245455AbiC3KlR (ORCPT ); Wed, 30 Mar 2022 06:41:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245446AbiC3KlQ (ORCPT ); Wed, 30 Mar 2022 06:41:16 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 777F9269364; Wed, 30 Mar 2022 03:39:31 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id dr20so40581186ejc.6; Wed, 30 Mar 2022 03:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HvmiSu9xAVWzXe/vos+wSBdt9erRcs0gCDQxB9pqVmU=; b=Nb7h5fOcV9fCrQeAWHkS8H3GUTSFI6dj+3abP914pwFbJCEf7ezBG2jq6doiUOEcbe pa3wmC0vMjABFZbMAHIXaVv6IeVopOomX9b+dpxVxHo71cZDh310hTYx1/1ko7o0s3Wp iFMNo+MkBLx8SSrG2f9hOPk8A1Hy997E8Cy/TJmD3N0k/CNcf/JmQSZi3IjF04wF1mE7 SI0+u3vUxZUy1lPqtDl4H65+BHwMxjkE8tNRl4BV3yg2njbHnw3WElF/i9dY9HTGgaeW yZrPM6dhgVTVIKd72i/ziGqdU6II96G2oYrGw+SKtaD4JYGnsesoAS64AL1iOYtpXaj2 ni8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HvmiSu9xAVWzXe/vos+wSBdt9erRcs0gCDQxB9pqVmU=; b=CSbyI91XicOdTR7ENp1zmG4nEmCY8Wb8318UkuJYLLJ3yJYxvVvA5UcaZ11Hf5Dzao 5Pqd1XFlDoi+7jQTgUb+Dg1PRPDs7AEqb7QW1GXnIjEGfkOXEK1vb2KIH7jPJyJq9sjt e6rz2qLPR5EKDLz+cE9QmmRlRI1J3soB1BkBKCS4IdaXQZcDjJI1RI1qZbb8QrIobVv/ NVdVZDlyjf739R5dz/RZ8dLDcI743Qaw6qcKeHzszAvi6jIqlqePQXPtswxN+t2Q4WnK fLl8z4g6mSCwZ0Amt04zXeFAf3W5Zm1PPgYo6R2XWGtVVFzstl9VuWOsqEYscl4GJf/2 63PQ== X-Gm-Message-State: AOAM532Z6i+DcRrj3uaH1rTG0UAx7hH3ZKVrxCEkH2CvjLbML+Ny1RkR 25yQRBAb2txc9cxWMgyIq+SNCmFBBsE= X-Google-Smtp-Source: ABdhPJzj6PjRZfoG8CmLerET50pv3HRkg/iiOQK9o1YzQSFScT1rWeTxqTuKciAnHVoxRcNz3BT9Eg== X-Received: by 2002:a17:906:dc90:b0:6e0:1ef7:638f with SMTP id cs16-20020a170906dc9000b006e01ef7638fmr39578624ejc.234.1648636769900; Wed, 30 Mar 2022 03:39:29 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id hq15-20020a1709073f0f00b006dfc0fe42b1sm8264920ejc.177.2022.03.30.03.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Mar 2022 03:39:29 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] dt-bindings: clock: convert rockchip,px30-cru.txt to YAML Date: Wed, 30 Mar 2022 12:39:23 +0200 Message-Id: <20220330103923.11063-1-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,px30-cru.txt to YAML. Changes against original bindings: Use compatible string: "rockchip,px30-pmucru" Signed-off-by: Johan Jonker Reviewed-by: Krzysztof Kozlowski --- Changed V2: add allOf:if:then: constraining --- .../bindings/clock/rockchip,px30-cru.txt | 70 ----------- .../bindings/clock/rockchip,px30-cru.yaml | 119 ++++++++++++++++++ 2 files changed, 119 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt deleted file mode 100644 index 55e78cdde..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Rockchip PX30 Clock and Reset Unit - -The PX30 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: PMU for CRU should be "rockchip,px30-pmu-cru" -- compatible: CRU should be "rockchip,px30-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names -- clock-names: Should contain the following: - - "xin24m" for both PMUCRU and CRU - - "gpll" for CRU (sourced from PMUCRU) -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "i2sx_clkin" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - pmucru: clock-controller@ff2bc000 { - compatible = "rockchip,px30-pmucru"; - reg = <0x0 0xff2bc000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff030000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff030000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml new file mode 100644 index 000000000..3eec381c7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PX30 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The PX30 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "i2sx_clkin" - external I2S clock - optional + - "gmac_clkin" - external GMAC clock - optional + +properties: + compatible: + enum: + - rockchip,px30-cru + - rockchip,px30-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 1 + items: + - description: Clock for both PMUCRU and CRU + - description: Clock for CRU (sourced from PMUCRU) + + clock-names: + minItems: 1 + items: + - const: xin24m + - const: gpll + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,px30-cru + + then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + + pmucru: clock-controller@ff2bc000 { + compatible = "rockchip,px30-pmucru"; + reg = <0xff2bc000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff2b0000 { + compatible = "rockchip,px30-cru"; + reg = <0xff2b0000 0x1000>; + clocks = <&xin24m>, <&pmucru PLL_GPLL>; + clock-names = "xin24m", "gpll"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + };