From patchwork Mon Jan 7 03:28:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10749853 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64F4713AD for ; Mon, 7 Jan 2019 03:28:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47D15285B9 for ; Mon, 7 Jan 2019 03:28:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39DA528691; Mon, 7 Jan 2019 03:28:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D2133285B9 for ; Mon, 7 Jan 2019 03:28:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bHkuUQaZMPLuBQJWII3D6WluBIBrfuSZsv4x1poETYc=; b=s+/ukjF9c4ogp6 pdzn1FDeFYMN+J4PNXeZmjC1gVfIPV/tEXOCnRiVdDBENfEmLwyGsGTKKl++Vf/OuwSK3GxLtPkvL slPXwWq2/0sKpfVgqqnwe3GZeq5RqLMgbOQ+6kgvZargk7xBeTYeFQDeAofCVmNWvG4jzSYDPYxlk KePkUceOkeDdcWkULaT2PG5iGVXJcWDO5dktKNM00LHYFPuqd+njnMWQHiC5FNahV4Rml4qHNtywy IRYYD8FO/ileZ2BKX6vqBGbCaz4KhHrphi6My4WxcrjJ9jFwLBgIrA4f3RfUJDXfymn/ad2zKFw4o GMNDhR5BQephgmeeLuOQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1ggLaq-0008Ln-QO; Mon, 07 Jan 2019 03:28:48 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1ggLaQ-0007u6-B7 for linux-arm-kernel@lists.infradead.org; Mon, 07 Jan 2019 03:28:25 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 06 Jan 2019 19:27:55 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 06 Jan 2019 19:28:18 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 06 Jan 2019 19:28:18 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 7 Jan 2019 03:28:17 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 7 Jan 2019 03:28:17 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 7 Jan 2019 03:28:17 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 06 Jan 2019 19:28:17 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH 1/6] dt-bindings: timer: add Tegra210 timer Date: Mon, 7 Jan 2019 11:28:05 +0800 Message-ID: <20190107032810.13522-2-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190107032810.13522-1-josephl@nvidia.com> References: <20190107032810.13522-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546831675; bh=LHEqbecChah87qfLXM/Qea7EG6dEAOWjm6zr4VtFkWc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=pXngyVzULhyLucbO37W6ia+BZ96QEIYjvDD8gHopmPOZqEWX+if90dVyph5cRr/u8 jla58YcJNu5D2iyslAtRaliqYZxd4QthLZA+2E1KbzdF+kfIRGJO9sf7O6Ym/I02HF DwzED5wQqTqz1La9tc2p4odELbajOPIIQ2Zx6p6pNwa+QJhGChnz6wHgOrqbjsLd5S jhwcBRpLLHDfb9Oy8QBU8dGd3PAwtSBSECjEBUScCFb5dR11ZoHnqhjGPSgSIPOJcp gDMxrQKikvAAKM71TBB1C7P1HHVK6qR8g1todV60VDoD2kctIeUPl6foKojbqgl+vi NrijBrFyDEt/A== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190106_192822_392825_FBBE55D1 X-CRM114-Status: UNSURE ( 7.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Daniel Lezcano , linux-kernel@vger.kernel.org, Joseph Lo , linux-tegra@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Reviewed-by: Rob Herring --- .../bindings/timer/nvidia,tegra210-timer.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 000000000000..ba511220a669 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,25 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 4 interrupts; one per each of TMR10 through TMR13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +}; From patchwork Mon Jan 7 03:28:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10749855 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C314A13AD for ; Mon, 7 Jan 2019 03:29:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ADE91286A9 for ; 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Sun, 06 Jan 2019 19:28:20 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 06 Jan 2019 19:28:20 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 7 Jan 2019 03:28:19 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 7 Jan 2019 03:28:19 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 06 Jan 2019 19:28:19 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH 2/6] clocksource: tegra: add Tegra210 timer driver Date: Mon, 7 Jan 2019 11:28:06 +0800 Message-ID: <20190107032810.13522-3-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190107032810.13522-1-josephl@nvidia.com> References: <20190107032810.13522-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546831684; bh=s8IY+h9IkiprqLgYA1ZLKIoVj6hPmRxlGX95RnCfMwo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=oBSETjQwAtSvWPL4jZQiQnPOSBAqbh3Uz+qTYENJjEhtyR5tGe91EFt1Ll65nBQJt KztDyryjXKbz7PADmMzV00JQ2G7SVmRRw5ZwfxyzQbsFNyS05eGLa5CrmZX2a1jF+0 DWi3CW7D1dNQSEOt2ct2spjiG1/QhNvNjyz5Ud6n479AOe4HLjh4Cg2SNOM3XkFCsq xmA4u06uGcZkQORL6PIpp4TjYZEyBMSM6M/X1dZmp3xtT2H8vhetTSzr5oc6+DaE1F irxXfzHiYA7rAI+9oEqBWATpnMTausip4cq0n2S1bVxJU42s65TVLq3Ts4fOsecD+K kxTlxKMBxkveA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190106_192822_719819_127FA2D5 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Lezcano , linux-kernel@vger.kernel.org, Joseph Lo , linux-tegra@vger.kernel.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the Tegra210 timer that runs at oscillator clock (TMR10-TMR13). We need these timers to work as clock event device and to replace the ARMv8 architected timer due to it can't survive across the power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up source when CPU suspends in power down state. Based on the work of Antti P Miettinen Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Joseph Lo --- drivers/clocksource/Kconfig | 3 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-tegra210.c | 240 +++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 245 insertions(+) create mode 100644 drivers/clocksource/timer-tegra210.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a9e26f6a81a1..e6e3e64b6320 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -135,6 +135,9 @@ config TEGRA_TIMER help Enables support for the Tegra driver. +config TEGRA210_TIMER + def_bool ARCH_TEGRA_210_SOC + config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cdd210ff89ea..95de59c8a47b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o +obj-$(CONFIG_TEGRA210_TIMER) += timer-tegra210.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/timer-tegra210.c b/drivers/clocksource/timer-tegra210.c new file mode 100644 index 000000000000..d88c127d3b3b --- /dev/null +++ b/drivers/clocksource/timer-tegra210.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static u32 tegra210_timer_freq; +static void __iomem *tegra210_timer_reg_base; +static u32 usec_config; + +#define TIMER_PTV 0x0 +#define TIMER_PTV_EN BIT(31) +#define TIMER_PTV_PER BIT(30) +#define TIMER_PCR 0x4 +#define TIMER_PCR_INTR_CLR BIT(30) +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 + +#define TIMER10_OFFSET 0x90 + +#define TIMER_FOR_CPU(cpu) (TIMER10_OFFSET + (cpu) * 8) + +struct tegra210_clockevent { + struct clock_event_device evt; + char name[20]; + void __iomem *reg_base; +}; +#define to_tegra_cevt(p) (container_of(p, struct tegra210_clockevent, evt)) + +static struct tegra210_clockevent __percpu *tegra210_evt; + +static int tegra210_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct tegra210_clockevent *tevt; + + tevt = to_tegra_cevt(evt); + writel(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + tevt->reg_base + TIMER_PTV); + + return 0; +} + +static inline void timer_shutdown(struct tegra210_clockevent *tevt) +{ + writel(0, tevt->reg_base + TIMER_PTV); +} + +static int tegra210_timer_shutdown(struct clock_event_device *evt) +{ + struct tegra210_clockevent *tevt; + + tevt = to_tegra_cevt(evt); + timer_shutdown(tevt); + + return 0; +} + +static int tegra210_timer_set_periodic(struct clock_event_device *evt) +{ + struct tegra210_clockevent *tevt; + + tevt = to_tegra_cevt(evt); + writel(TIMER_PTV_EN | TIMER_PTV_PER | ((tegra210_timer_freq / HZ) - 1), + tevt->reg_base + TIMER_PTV); + + return 0; +} + +static irqreturn_t tegra210_timer_isr(int irq, void *dev_id) +{ + struct tegra210_clockevent *tevt; + + tevt = dev_id; + writel(TIMER_PCR_INTR_CLR, tevt->reg_base + TIMER_PCR); + tevt->evt.event_handler(&tevt->evt); + + return IRQ_HANDLED; +} + +static int tegra210_timer_setup(unsigned int cpu) +{ + struct tegra210_clockevent *tevt = per_cpu_ptr(tegra210_evt, cpu); + + irq_force_affinity(tevt->evt.irq, cpumask_of(cpu)); + enable_irq(tevt->evt.irq); + + clockevents_config_and_register(&tevt->evt, tegra210_timer_freq, + 1, /* min */ + 0x1fffffff); /* 29 bits */ + + return 0; +} + +static int tegra210_timer_stop(unsigned int cpu) +{ + struct tegra210_clockevent *tevt = per_cpu_ptr(tegra210_evt, cpu); + + tevt->evt.set_state_shutdown(&tevt->evt); + disable_irq_nosync(tevt->evt.irq); + + return 0; +} + +static int tegra_timer_suspend(void) +{ + int cpu; + + for_each_possible_cpu(cpu) { + void __iomem *reg_base = tegra210_timer_reg_base + + TIMER_FOR_CPU(cpu); + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + } + + return 0; +} + +static void tegra_timer_resume(void) +{ + writel(usec_config, tegra210_timer_reg_base + TIMERUS_USEC_CFG); +} + +static struct syscore_ops tegra_timer_syscore_ops = { + .suspend = tegra_timer_suspend, + .resume = tegra_timer_resume, +}; + +static int __init tegra210_timer_init(struct device_node *np) +{ + int cpu, ret; + struct tegra210_clockevent *tevt; + struct clk *clk; + + tegra210_evt = alloc_percpu(struct tegra210_clockevent); + if (!tegra210_evt) + return -ENOMEM; + + tegra210_timer_reg_base = of_iomap(np, 0); + if (!tegra210_timer_reg_base) + return -ENXIO; + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) + return -EINVAL; + + clk_prepare_enable(clk); + tegra210_timer_freq = clk_get_rate(clk); + + for_each_possible_cpu(cpu) { + tevt = per_cpu_ptr(tegra210_evt, cpu); + tevt->reg_base = tegra210_timer_reg_base + TIMER_FOR_CPU(cpu); + tevt->evt.irq = irq_of_parse_and_map(np, cpu); + if (!tevt->evt.irq) { + pr_err("%s: can't map IRQ for CPU%d\n", + __func__, cpu); + return -EINVAL; + } + + snprintf(tevt->name, ARRAY_SIZE(tevt->name), + "tegra210_timer%d", cpu); + tevt->evt.name = tevt->name; + tevt->evt.cpumask = cpumask_of(cpu); + tevt->evt.set_next_event = tegra210_timer_set_next_event; + tevt->evt.set_state_shutdown = tegra210_timer_shutdown; + tevt->evt.set_state_periodic = tegra210_timer_set_periodic; + tevt->evt.set_state_oneshot = tegra210_timer_shutdown; + tevt->evt.tick_resume = tegra210_timer_shutdown; + tevt->evt.features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT; + tevt->evt.rating = 460; + + irq_set_status_flags(tevt->evt.irq, IRQ_NOAUTOEN); + ret = request_irq(tevt->evt.irq, tegra210_timer_isr, + IRQF_TIMER | IRQF_NOBALANCING, + tevt->name, tevt); + if (ret) { + pr_err("%s: cannot setup irq %d for CPU%d\n", + __func__, tevt->evt.irq, cpu); + return -EINVAL; + } + } + + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (tegra210_timer_freq) { + case 12000000: + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case 12800000: + usec_config = 0x043f; /* (63+1)/(4+1) */ + break; + case 13000000: + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case 16800000: + usec_config = 0x0453; /* (83+1)/(4+1) */ + break; + case 19200000: + usec_config = 0x045f; /* (95+1)/(4+1) */ + break; + case 26000000: + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case 38400000: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case 48000000: + usec_config = 0x002f; /* (47+1)/(0+1) */ + break; + default: + return -EINVAL; + } + + writel(usec_config, tegra210_timer_reg_base + TIMERUS_USEC_CFG); + + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra210_timer_setup, + tegra210_timer_stop); + + register_syscore_ops(&tegra_timer_syscore_ops); + + return 0; +} + +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_timer_init); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index fd586d0301e7..e78281d07b70 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -121,6 +121,7 @@ enum cpuhp_state { CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, + CPUHP_AP_TEGRA_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MARCO_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, From patchwork Mon Jan 7 03:28:07 2019 Content-Type: text/plain; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Fix timer node to make it work with Tegra210 timer driver. And backward compatible with the Tegra watchdog driver. Signed-off-by: Joseph Lo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index b5858b5ea052..143bd103c923 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -384,14 +384,12 @@ }; timer@60005000 { - compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra210-timer", "nvidia,tegra30-timer"; reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + ; clocks = <&tegra_car TEGRA210_CLK_TIMER>; clock-names = "timer"; }; From patchwork Mon Jan 7 03:28:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10749857 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D1F51399 for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add idle states properties for generic ARM CPU idle driver. This includes a C7 state which is the power down state of CPU cores. Signed-off-by: Joseph Lo --- Note: This dt patch depends on the DT changes in below series. http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380 --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 143bd103c923..b583d3065946 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1308,24 +1308,41 @@ <&dfll>; clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; + cpu-idle-states = <&C7>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <1>; + cpu-idle-states = <&C7>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <2>; + cpu-idle-states = <&C7>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <3>; + cpu-idle-states = <&C7>; + }; + + idle-states { + entry-method = "psci"; + + C7: c7 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000007>; + wakeup-latency-us = <130>; + min-residency-us = <1000>; + idle-state-name = "c7-cpu-powergated"; + status = "disabled"; + }; }; }; From patchwork Mon Jan 7 03:28:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10749859 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76F4313AD for ; Mon, 7 Jan 2019 03:29:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 636902873B for ; Mon, 7 Jan 2019 03:29:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 569712881A; Mon, 7 Jan 2019 03:29:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 02B522873B for ; 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Sun, 06 Jan 2019 19:28:24 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH 5/6] arm64: dts: tegra210-p2180: Enable CPU idle support Date: Mon, 7 Jan 2019 11:28:09 +0800 Message-ID: <20190107032810.13522-6-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190107032810.13522-1-josephl@nvidia.com> References: <20190107032810.13522-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546831693; bh=Qd+NpVy4Qte8b22/j1d3hdAYFVB8vJOHdGdLHXu2Rkg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=peGfCCUzxobrK+gfGQ6DYFrEz6KExDfQas3+MZwkN1hYBao6bvkG5ljvXm8WFMNY5 6b8X6oGCdrbV7tIAV1/TxMRV/MoU/UhL/ghOKR0kKZH0GoonIeyW9FdY61eIbrp8tZ mhR9VEhMNsZr8twbPFmkK2RoUG9nupRfwe69+hiZai07exA11i1kyMwgVQINnDy50X kpiZGvQ6AvYbhnxxVaGhMN5ZadJAGSl92yCUAtU3HQ2luW5d2oxPAUgXL+jpwoJlfd c8KjIaP8ONtANRNtg7jUMzyK92O6v2BD96fbI58U9bw4Zclj1JBc1KQyJiRSW/3aDC zeMinBvCRqljA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190106_192825_956124_B81AD903 X-CRM114-Status: UNSURE ( 6.57 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable CPU idle support for Jetson TX1 platform. Signed-off-by: Joseph Lo --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 053458a5db55..d1a492c63e96 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -305,6 +305,12 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + c7 { + status = "okay"; + }; + }; }; psci { From patchwork Mon Jan 7 03:28:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10749861 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6640113AD for ; Mon, 7 Jan 2019 03:29:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 555B02873B for ; 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Sun, 06 Jan 2019 19:28:27 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 06 Jan 2019 19:28:27 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 7 Jan 2019 03:28:27 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 7 Jan 2019 03:28:26 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 7 Jan 2019 03:28:26 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 06 Jan 2019 19:28:26 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter Subject: [PATCH 6/6] arm64: dts: tegra210-smaug: Enable CPU idle support Date: Mon, 7 Jan 2019 11:28:10 +0800 Message-ID: <20190107032810.13522-7-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190107032810.13522-1-josephl@nvidia.com> References: <20190107032810.13522-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable CPU idle support for Smaug platform. Signed-off-by: Joseph Lo --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 5a67890cfb7a..da0eb4530acf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1751,6 +1751,13 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + c7 { + arm,psci-suspend-param = <0x00010007>; + status = "okay"; + }; + }; }; gpio-keys {