From patchwork Thu Mar 31 12:58:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12797084 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5190A813 for ; Thu, 31 Mar 2022 12:58:24 +0000 (UTC) Received: by mail-wm1-f46.google.com with SMTP id p189so14228380wmp.3 for ; Thu, 31 Mar 2022 05:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9w3ZU2FP1Rv3cljPhXS0CpszxfyekTzsqMLGoLCCSm8=; b=llpzdZ2QoUIy9Tl0HxXnxvtUoVjm9IgVG5PX86hpKe72UlB1I5Lq+qPkd3R+eHJoA2 EhH3UJig8Z4xLiD+fmzidq5eoc0HkacxizCfKsEm2oLn90plB55zQ7pVM2DNmlvkKDI8 RcyFXcCbhcSlE+Rq0X68yBVT3e6e2TbkzwYts= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9w3ZU2FP1Rv3cljPhXS0CpszxfyekTzsqMLGoLCCSm8=; b=FIvytpkpjGwPro4NNqb0hyeCuWXvwnhEUe1CEg6a7ZVHMDdtcf9IMDwNy4jUzLHe2e hHavM3G0y9pYZhl+itpRCFyqV925PBBqkoaT8n9aGFwbOHNyUh/tOtZJUYuX8OPRLHH+ yfZ6UhdPSUP224XkbQ1BCq6s+aoKAg/uSZH85Br01f69cw/9v2RuwdB0lTlvdP4YNYuy GoSP67hwI7HENn1CTGzvx7nf9gsiqdQ7PqRmuSMIShMwBtoq85OpxE6DJh0hEi0SAqIS VjAA69pWQMVZUwcpb4vGp4gKTh9HYv/zzi5HplXyN2JVdve3qBd5iW47mL9FUSWYtEHS PhGQ== X-Gm-Message-State: AOAM532Yv/gjboZEzbSsqW0mo8OtretvOE0/xpWQd7ltyFlM+k9ls5+m +j1Oz/DYNOR2312CcAS+R9z7Kg== X-Google-Smtp-Source: ABdhPJw/bvvxGSAdxaxfDR7i8xQQgyJ4xG4agDhOyHyIbNnyenaBkh8+NJdEuQEXlJHU37EUBxUwZQ== X-Received: by 2002:a05:600c:378d:b0:38b:e12f:edde with SMTP id o13-20020a05600c378d00b0038be12feddemr4636148wmr.69.1648731502654; Thu, 31 Mar 2022 05:58:22 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id j16-20020a05600c191000b0038c9249ffdesm8230695wmq.9.2022.03.31.05.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 05:58:22 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v2 1/4] dt-bindings: add mfd/cros_ec definitions Date: Thu, 31 Mar 2022 12:58:15 +0000 Message-Id: <20220331125818.3776912-2-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog In-Reply-To: <20220331125818.3776912-1-fabiobaltieri@chromium.org> References: <20220331125818.3776912-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a dt-bindings include file for cros_ec devicetree definition, define a pair of special purpose PWM channels in it. Signed-off-by: Fabio Baltieri --- include/dt-bindings/mfd/cros_ec.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/mfd/cros_ec.h diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cros_ec.h new file mode 100644 index 000000000000..3b29cd049578 --- /dev/null +++ b/include/dt-bindings/mfd/cros_ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * DTS binding definitions used for the Chromium OS Embedded Controller. + * + * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MFD_CROS_EC_H +#define _DT_BINDINGS_MFD_CROS_EC_H + +/* Typed channel for keyboard backlight. */ +#define CROS_EC_PWM_DT_KB_LIGHT 0 +/* Typed channel for display backlight. */ +#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 +/* Number of typed channels. */ +#define CROS_EC_PWM_DT_COUNT 2 + +#endif From patchwork Thu Mar 31 12:58:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12797085 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21B7D814 for ; Thu, 31 Mar 2022 12:58:25 +0000 (UTC) Received: by mail-wm1-f49.google.com with SMTP id v64-20020a1cac43000000b0038cfd1b3a6dso1660109wme.5 for ; Thu, 31 Mar 2022 05:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fnERuxTpwmIqEKkUGAva/36LeD27jpDMYFwmiCf/45o=; b=FDWRdxI76mF4dLFtAAI648zdVhUOPFc4EVL9mY55Hm8emhvXspwcut4lQ9hEQy7dYM nRPYfpRFT2MhWNStKi8Sx07jD6TkYplFoo4hWr2bIKq17j2bRTJlcmQ7unT1iku9BJdg hzkgzU/NuG7/dYPo4boPHAaDmyUB7fPBGe+1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fnERuxTpwmIqEKkUGAva/36LeD27jpDMYFwmiCf/45o=; b=0rnafxVTgzRTw+4ZfITjPtSRQxCT/BIxiUhSUBELisdbgXdar1E5VnSX10uGH5VVX/ Dn7AOVNR7nqmwAPsHln9Bdyu5TQUPRZUzYzJWTKRMxLaYRcAOagGNfWLoB1RTmegpPGz oUuiPkCl8elwfhUB3Pg9bHYwHIwmbD1n54CRDl66hJ13Amcnpqt0Q0e/JsOu/kRC5+7c CTDuDGKy5I/8YcZ6PKxYRTXHlab4T2Bfhp8N2awn7rHCk0phobJm04mcLqAawCQZg2HD /wY0EkrLmxIYD3YmEGd77g44Yz+9ZOsn14ezFuJVBxEt/XLDepl8Dtj9a1lEi2EjjwsR xvZA== X-Gm-Message-State: AOAM533jczksx93fgZ8m9/ZpSrbEdjDb7xwqK96phHwmeG/KNdnmaibj 8Q9OZiDSe4/2gKaRnMPjpKTVVA== X-Google-Smtp-Source: ABdhPJzVVIAmiHVnmlyTZI1yKGbj6Wos/oqQ1UVDOn2sfEpc7PpD6rwUeidkI6nuuNVCsPWGYpWsHA== X-Received: by 2002:a05:600c:5120:b0:38c:d121:4738 with SMTP id o32-20020a05600c512000b0038cd1214738mr4870920wms.32.1648731503476; Thu, 31 Mar 2022 05:58:23 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id j16-20020a05600c191000b0038c9249ffdesm8230695wmq.9.2022.03.31.05.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 05:58:23 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v2 2/4] drivers: pwm: pwm-cros-ec: add channel type support Date: Thu, 31 Mar 2022 12:58:16 +0000 Message-Id: <20220331125818.3776912-3-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog In-Reply-To: <20220331125818.3776912-1-fabiobaltieri@chromium.org> References: <20220331125818.3776912-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for EC_PWM_TYPE_DISPLAY_LIGHT and EC_PWM_TYPE_KB_LIGHT pwm types to the PWM cros_ec_pwm driver. This allows specifying one of these PWM channel by functionality, and let the EC firmware pick the correct channel, thus abstracting the hardware implementation from the kernel driver. Signed-off-by: Fabio Baltieri Reviewed-by: Tzung-Bi Shih --- drivers/pwm/pwm-cros-ec.c | 80 +++++++++++++++++++++++++++++++-------- 1 file changed, 65 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 5e29d9c682c3..051791f5d024 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -12,17 +12,21 @@ #include #include +#include + /** * struct cros_ec_pwm_device - Driver data for EC PWM * * @dev: Device node * @ec: Pointer to EC device * @chip: PWM controller chip + * @use_pwm_type: Use PWM types instead of generic channels */ struct cros_ec_pwm_device { struct device *dev; struct cros_ec_device *ec; struct pwm_chip chip; + bool use_pwm_type; }; /** @@ -58,14 +62,31 @@ static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) kfree(channel); } -static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) +static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type) { + switch (dt_index) { + case CROS_EC_PWM_DT_KB_LIGHT: + *pwm_type = EC_PWM_TYPE_KB_LIGHT; + return 0; + case CROS_EC_PWM_DT_DISPLAY_LIGHT: + *pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT; + return 0; + default: + return -EINVAL; + } +} + +static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index, + u16 duty) +{ + struct cros_ec_device *ec = ec_pwm->ec; struct { struct cros_ec_command msg; struct ec_params_pwm_set_duty params; } __packed buf; struct ec_params_pwm_set_duty *params = &buf.params; struct cros_ec_command *msg = &buf.msg; + int ret; memset(&buf, 0, sizeof(buf)); @@ -75,14 +96,25 @@ static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) msg->outsize = sizeof(*params); params->duty = duty; - params->pwm_type = EC_PWM_TYPE_GENERIC; - params->index = index; + + if (ec_pwm->use_pwm_type) { + ret = cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index = 0; + } else { + params->pwm_type = EC_PWM_TYPE_GENERIC; + params->index = index; + } return cros_ec_cmd_xfer_status(ec, msg); } -static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) +static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 index) { + struct cros_ec_device *ec = ec_pwm->ec; struct { struct cros_ec_command msg; union { @@ -102,8 +134,17 @@ static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) msg->insize = sizeof(*resp); msg->outsize = sizeof(*params); - params->pwm_type = EC_PWM_TYPE_GENERIC; - params->index = index; + if (ec_pwm->use_pwm_type) { + ret = cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index = 0; + } else { + params->pwm_type = EC_PWM_TYPE_GENERIC; + params->index = index; + } ret = cros_ec_cmd_xfer_status(ec, msg); if (ret < 0) @@ -133,7 +174,7 @@ static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, */ duty_cycle = state->enabled ? state->duty_cycle : 0; - ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle); + ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle); if (ret < 0) return ret; @@ -149,7 +190,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct cros_ec_pwm *channel = pwm_get_chip_data(pwm); int ret; - ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm); + ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm); if (ret < 0) { dev_err(chip->dev, "error getting initial duty: %d\n", ret); return; @@ -204,13 +245,13 @@ static const struct pwm_ops cros_ec_pwm_ops = { * of PWMs it supports directly, so we have to read the pwm duty cycle for * subsequent channels until we get an error. */ -static int cros_ec_num_pwms(struct cros_ec_device *ec) +static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm) { int i, ret; /* The index field is only 8 bits */ for (i = 0; i <= U8_MAX; i++) { - ret = cros_ec_pwm_get_duty(ec, i); + ret = cros_ec_pwm_get_duty(ec_pwm, i); /* * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM * responses; everything else is treated as an error. @@ -251,17 +292,26 @@ static int cros_ec_pwm_probe(struct platform_device *pdev) chip = &ec_pwm->chip; ec_pwm->ec = ec; + ec_pwm->use_pwm_type = of_property_read_bool( + dev->of_node, "google,use-pwm-type"); + /* PWM chip */ chip->dev = dev; chip->ops = &cros_ec_pwm_ops; chip->of_xlate = cros_ec_pwm_xlate; chip->of_pwm_n_cells = 1; - ret = cros_ec_num_pwms(ec); - if (ret < 0) { - dev_err(dev, "Couldn't find PWMs: %d\n", ret); - return ret; + + if (ec_pwm->use_pwm_type) { + chip->npwm = CROS_EC_PWM_DT_COUNT; + } else { + ret = cros_ec_num_pwms(ec_pwm); + if (ret < 0) { + dev_err(dev, "Couldn't find PWMs: %d\n", ret); + return ret; + } + chip->npwm = ret; } - chip->npwm = ret; + dev_dbg(dev, "Probed %u PWMs\n", chip->npwm); ret = pwmchip_add(chip); From patchwork Thu Mar 31 12:58:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12797086 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 078D0813 for ; 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Thu, 31 Mar 2022 05:58:24 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id j16-20020a05600c191000b0038c9249ffdesm8230695wmq.9.2022.03.31.05.58.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 05:58:24 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v2 3/4] dt-bindings: update google,cros-ec-pwm documentation Date: Thu, 31 Mar 2022 12:58:17 +0000 Message-Id: <20220331125818.3776912-4-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog In-Reply-To: <20220331125818.3776912-1-fabiobaltieri@chromium.org> References: <20220331125818.3776912-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update google,cros-ec-pwm node documentation to mention the google,use_pwm_type property. Signed-off-by: Fabio Baltieri --- .../devicetree/bindings/pwm/google,cros-ec-pwm.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 4cfbffd8414a..9c895c990ed8 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -19,6 +19,12 @@ description: | properties: compatible: const: google,cros-ec-pwm + + google,use-pwm-type: + description: + Use PWM types (CROS_EC_PWM_DT_<...>) instead of generic channels. + type: boolean + "#pwm-cells": description: The cell specifies the PWM index. const: 1 From patchwork Thu Mar 31 12:58:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12797087 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE7ED814 for ; Thu, 31 Mar 2022 12:58:26 +0000 (UTC) Received: by mail-wm1-f44.google.com with SMTP id r7so14214925wmq.2 for ; Thu, 31 Mar 2022 05:58:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Aw43ShyWTbUOanwO78IeqdFbuMs79zsCXNAFn6cnNUM=; b=VOYyqlHVDP1xMHK2KF+JHMxE/Lb8UZ9nEDnDfj+kS6qvnqSx/1c2n0j0oboBWyb54T GqIZTEJ2UF2cyu9V+Ae4WQt3npQFXI/x9CwodL5bn0WRn4FRS4Gsz7fruMCeokUqo0wZ gzjCoarEqmOTIVVIdEwAzcTL/Io7b5lMXqDrc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Aw43ShyWTbUOanwO78IeqdFbuMs79zsCXNAFn6cnNUM=; b=Zri9wn6mOrYbAEgxfNZCNhDwdycbcgwwOSXZXMZ6oVW4os49cnadPAgBX3zjaYTKYy 4rL8OtpNhRZkejlfiJFtEKB0qy+e478/Ndem/vQTT9Ft88jl52g1A76JxTSaS1M9zB3W AL1Y3wcRtm7n5PzvdxfJU9SyykeV8y+Lk3a8colpGBsz0jJMWrpSfSe0xs377kuR3Ow7 fgjOxvRKCZAbC1gvu9j9qQa6lv3cJ8+Xz2H5kkiPKWF+7Ecj1AiSnqxdwsu+tPMb2Hy3 ErOmVT+EI9hKBe95CWzPj68PfL9aNAPg7LTwr6CjGPWWHog/fgHsEo0ZWNLBISZEMLNB +dEw== X-Gm-Message-State: AOAM530QGQ+zpXiPsgynlk6Ue0sVa2PMgMOgGgDQtFRlpR4c6PGIC66o 4grpXdOgPhEADX+I/f7ZBuyhqw== X-Google-Smtp-Source: ABdhPJwBNx9zCzQDcWS+m0Z1PQADM7edu7bYTDURpz+AdSt3EYCH77a34WW0LFsLI414BhpW3lWz4w== X-Received: by 2002:a05:600c:4f94:b0:38d:ed0:8468 with SMTP id n20-20020a05600c4f9400b0038d0ed08468mr4703460wmq.164.1648731505251; Thu, 31 Mar 2022 05:58:25 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id j16-20020a05600c191000b0038c9249ffdesm8230695wmq.9.2022.03.31.05.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 05:58:24 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v2 4/4] arm64: dts: address cros-ec-pwm channels by type Date: Thu, 31 Mar 2022 12:58:18 +0000 Message-Id: <20220331125818.3776912-5-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog In-Reply-To: <20220331125818.3776912-1-fabiobaltieri@chromium.org> References: <20220331125818.3776912-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update various cros-ec-pwm board definitions to address the keyboard and screen backlight PWM channels by type rather than channel number. This makes the instance independent by the actual hardware configuration, relying on the EC firmware to pick the right channel, and allows dropping few dtsi overrides as a consequence. Changed the node label used to cros_ec_pwm_type to avoid ambiguity about the pwm cell meaning. Signed-off-by: Fabio Baltieri --- .../dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 3 ++- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 8 +++++--- .../arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 6 ++++-- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 6 ++++-- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 4 +++- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 13 files changed, 28 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index dec11a4eb59e..e2554a313deb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -15,13 +15,13 @@ pwmleds { compatible = "pwm-leds"; keyboard_backlight: keyboard-backlight { label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; }; -&cros_ec_pwm { +&cros_ec_pwm_type { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..f70c549bae93 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,10 +92,11 @@ volume_up { }; &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm_type: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; status = "disabled"; + google,use-pwm-type; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..ff54687ab8bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include "mt8183.dtsi" #include "mt6358.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index c81805ef2250..aea7c66d95e0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -77,10 +77,6 @@ &ap_spi_fp { status = "okay"; }; -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - &camcc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 732e1181af48..56f398b05b7b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -316,7 +317,7 @@ backlight: backlight { num-interpolated-steps = <64>; default-brightness-level = <951>; - pwms = <&cros_ec_pwm 1>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; pinctrl-names = "default"; @@ -354,7 +355,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -637,9 +638,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { + cros_ec_pwm_type: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use-pwm-type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 1779d96c30f6..cc11de91cc2c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -336,7 +337,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -705,9 +706,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { + cros_ec_pwm_type: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use-pwm-type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index dc17f2079695..e5a041226db6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "sc7280-qcard.dtsi" #include "sc7280-chrome-common.dtsi" @@ -288,7 +289,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -421,9 +422,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { + cros_ec_pwm_type: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use-pwm-type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index a7c346aa3b02..a8c189328ae3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,9 +20,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { + cros_ec_pwm_type: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use-pwm-type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index e7e4cc5936aa..600b8ea69a5d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include "sdm845.dtsi" @@ -27,7 +28,7 @@ chosen { backlight: backlight { compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; pinctrl-names = "default"; @@ -708,9 +709,10 @@ cros_ec: ec@0 { pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { + cros_ec_pwm_type: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use-pwm-type; }; i2c_tunnel: i2c-tunnel { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts index 31ebb4e5fd33..5a076c2564f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -55,10 +55,6 @@ trackpad: trackpad@15 { }; }; -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - &cpu_alert0 { temperature = <65000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3355fb90fa54..fece0176a3d2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -198,6 +198,7 @@ backlight: backlight { power-supply = <&pp3300_disp>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; pwm-delay-us = <10000>; }; @@ -462,9 +463,10 @@ ap_i2c_tp: &i2c5 { }; &cros_ec { - cros_ec_pwm: pwm { + cros_ec_pwm_type: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; + google,use-pwm-type; }; usbc_extcon1: extcon1 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 6863689df06f..e959a33af34b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -84,10 +84,6 @@ thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { }; }; -&backlight { - pwms = <&cros_ec_pwm 1>; -}; - &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..181159e9982d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include "rk3399.dtsi" #include "rk3399-op1-opp.dtsi"