From patchwork Sat Apr 2 14:36:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2D40C433F5 for ; Sat, 2 Apr 2022 14:36:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356572AbiDBOik (ORCPT ); Sat, 2 Apr 2022 10:38:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356564AbiDBOii (ORCPT ); Sat, 2 Apr 2022 10:38:38 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B564181B19; Sat, 2 Apr 2022 07:36:46 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id yy13so11446214ejb.2; Sat, 02 Apr 2022 07:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ay5bIkDMN0uWXFaucFOQ03lqhqXOzPmmv54m4o8auLE=; b=RvgbPEG3WIiL//B+ubI3vbRFJWsOVYJku3J9ODjBbgB1bLKL0HE6yHEpz7c0zAEFoN w7WiczXcCXezSPwFP5LqpDHoGG9De5viqdBAgEgAwa4apaYbR/mU093W6ZqzW6QZXbbM t8ch6M0V6mJsKJJo0+crOv8cGXYX7AOfq4sQYQsYhGmEn9qj05qYEK0OA1yz/01L1Dun U1Dw0nWZPGiSSWZ9wJNcGBci24sNtT1Ssyj4TQ42/d32seY0xLUMdSBUaAf9LY2Al6pv RS9XH11lyqWAD70gS/S22z5YUM9Vp6Jm7Do8nTPDYtnJfHD6SZN231AI1+Vm8KfFLg7h BZmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ay5bIkDMN0uWXFaucFOQ03lqhqXOzPmmv54m4o8auLE=; b=5skUcvBqT7ozUNxiZTRFv7lsipqhUOa8VE6LGBBNgtK1XXHUskh4mECB/ZsPjFJHdv kjd/n69ckXrqEb+IZHdHn2QKA5Uy3zzj6yBBjRXRfXvB5k2p0DevB9Fk/RpeSq+2cGcr OpcGkRy0iNnUjVNK9P2ao1lLLgktGvefzVfmuvUbfkVkT/JWxPQI2FfpFLhLAapxjjI+ CKYM+SZcZ1Jx4XxqGtW9sekh39UQHmhZrf5ms1pYQWmGPTjfCI6eOZbNYcFXdnYRzAAr M162HNauya52tdu3IpcTNXe5K9wgtuUj8vWs4fyDGMp6fIJm63RU4x6U0jbVqeQxmDIN DLYg== X-Gm-Message-State: AOAM530TkGqI0cjLVyiXqPNonpqNox9+qauySVb1DqSP6McovSqc4nfF QV0wAfY0lGIXPyyyj+avzZ0frPcch7I= X-Google-Smtp-Source: ABdhPJxm4mqwNr+KeTDo/7qreofruqZueesSFWpUFtS4m+sFct+MNlyiLH22R+eW/XGiaHx72ivOSQ== X-Received: by 2002:a17:907:2cc3:b0:6e6:45fb:39fa with SMTP id hg3-20020a1709072cc300b006e645fb39famr2593392ejc.545.1648910204514; Sat, 02 Apr 2022 07:36:44 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:44 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/16] dt-bindings: clock: convert rockchip,px30-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:21 +0200 Message-Id: <20220402143636.15222-2-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,px30-cru.txt to YAML. Changes against original bindings: Use compatible string: "rockchip,px30-pmucru" Signed-off-by: Johan Jonker --- Changed V4: add more clocks Changed V2: add allOf:if:then: constraining --- .../bindings/clock/rockchip,px30-cru.txt | 70 ---------- .../bindings/clock/rockchip,px30-cru.yaml | 120 ++++++++++++++++++ 2 files changed, 120 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt deleted file mode 100644 index 55e78cdde..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Rockchip PX30 Clock and Reset Unit - -The PX30 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: PMU for CRU should be "rockchip,px30-pmu-cru" -- compatible: CRU should be "rockchip,px30-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names -- clock-names: Should contain the following: - - "xin24m" for both PMUCRU and CRU - - "gpll" for CRU (sourced from PMUCRU) -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "i2sx_clkin" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - pmucru: clock-controller@ff2bc000 { - compatible = "rockchip,px30-pmucru"; - reg = <0x0 0xff2bc000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff030000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff030000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml new file mode 100644 index 000000000..c88e7e3db --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PX30 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The PX30 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,px30-cru + - rockchip,px30-pmucru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,px30-cru + + then: + properties: + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + items: + enum: + - xin24m + - xin32k + - gpll + - gmac_clkin + - i2sx_clkin + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + const: xin24m + +additionalProperties: false + +examples: + - | + #include + + pmucru: clock-controller@ff2bc000 { + compatible = "rockchip,px30-pmucru"; + reg = <0xff2bc000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff2b0000 { + compatible = "rockchip,px30-cru"; + reg = <0xff2b0000 0x1000>; + clocks = <&xin24m>, <&pmucru PLL_GPLL>; + clock-names = "xin24m", "gpll"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 224D9C43217 for ; Sat, 2 Apr 2022 14:36:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243878AbiDBOik (ORCPT ); Sat, 2 Apr 2022 10:38:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356566AbiDBOii (ORCPT ); Sat, 2 Apr 2022 10:38:38 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3D74182AE9; Sat, 2 Apr 2022 07:36:46 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id r13so11403622ejd.5; Sat, 02 Apr 2022 07:36:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ufsyFzWX+CGvBkTM6+OlUoN/PVXoz5psm+dkWM18YxY=; b=CsaViOiw1wtT2ca0hqNq2k4rPL0P4BrLEaUK1vr8ezWHE1usaWJ2+tB3i8Kv79/nvT TFILa3c3gvlnXjwMS0EIt1ggkKsWjo+veW6SYhiStX7rLApFks72dsviBFHLURZZJkpt sD2HtG+lUOW9vnqPX9LpNxuip2v6tw+wzE1xZCFpD8ymIF2EscZD79/UY7m7TzBmqnQI zudasWsdDTIKctuaezV3psE930pYYQ5KNo3YfR9P6bOpBp3pVGs7y7NNvxl+Z3Oi9NjM jRRbuBfLT8NX6gKucTpIG5drpaM8qJPkAdMsfsgUcALbYxzIMM05qCtwX2tESkJVa/yW 9wqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ufsyFzWX+CGvBkTM6+OlUoN/PVXoz5psm+dkWM18YxY=; b=bOdIdTfeA6/FkFVAccNB+nA7B+Rkf72WlGq+uupL5Sed0utals0o+fpXZvzwnOraXd sksw5/FYjOAiOODpQTOoKuXLuKhsBS3/FZ369tv3OQmxkbl7z61dUNIqM3bwsXm2U+3C /aFc9wmm2e1bKdxsV0OdAir1IQ3yn00YgGsJyz3yF8PZsOvJM3wn4lEu80rqPv3bkJSB qTkHDn9AJH9v/h54N0A4wUcekL09QNGvedKT7MvHiKJxymbznQJU5oJNctTWxoebR0Zl 3JgjHUhUYBPkVi4qBWUC3TFRYgjJNwEdMgloKuO/GRcD6IxpkTpV6ZPU5QlVqWYX3ivv OYPg== X-Gm-Message-State: AOAM533fMXHVEgwxfeSDrNcz7zRevete3I3AagrwdM1eLaoQYH4DBGFe Ze1FxWnhvYLVXNW2x5wTIIY= X-Google-Smtp-Source: ABdhPJyKu2ptLDRlztPlfYTVwwF23IydRosnHQX9fwIkOdiZ72WUzQaJsA7kY6ipIsV6HPAerSZIFA== X-Received: by 2002:a17:906:7943:b0:6df:e5b3:6553 with SMTP id l3-20020a170906794300b006dfe5b36553mr3994573ejo.398.1648910205452; Sat, 02 Apr 2022 07:36:45 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:45 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/16] dt-bindings: clock: convert rockchip,rk3036-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:22 +0200 Message-Id: <20220402143636.15222-3-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3036-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement --- .../bindings/clock/rockchip,rk3036-cru.txt | 56 ------------- .../bindings/clock/rockchip,rk3036-cru.yaml | 80 +++++++++++++++++++ 2 files changed, 80 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt deleted file mode 100644 index 20df350b9..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Rockchip RK3036 Clock and Reset Unit - -The RK3036 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3036-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "rmii_clkin" - external EMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@20060000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml new file mode 100644 index 000000000..121b298a6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3036 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3036 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rk3036-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + items: + enum: + - xin24m + - ext_i2s + - rmii_clkin + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AB69C43219 for ; Sat, 2 Apr 2022 14:36:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356586AbiDBOim (ORCPT ); Sat, 2 Apr 2022 10:38:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356576AbiDBOik (ORCPT ); Sat, 2 Apr 2022 10:38:40 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0EF0182D86; Sat, 2 Apr 2022 07:36:47 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id p15so11375478ejc.7; Sat, 02 Apr 2022 07:36:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QIVGUjs41+UBtdFf/mZgPvyrkZrSiMzhST++uwe+iNs=; b=IGuZEVR1bFfkZLH0sXRh90pKHTRRNW+084MuD3+cu+xCPq7RTGrtNw3tLoT2zl7sZM EFO02jQytaY4f1Ib7Qb46XSoN+k9aXQUHsSy3VSO00Dlr3MkT7v0X3MaFyei6TvNNx17 PghUn/aKObHAUxVd+ijKsB95beQTPQUinP0oKxwvvKNFSSt1kXJONRRZsCiwo1lEwCEi 1GSASPfAxpBTSbowHLyGrmMnXbXI66rVTQUwqGpS6kmvPkKHqmIh0PG9AAJukYt1cBGk K5Ogcve+0/GAHD+AwBhAK8Bq15Z55hNE+aXv2uJW/fle+avizL1bqapFmElhkeftp13W urWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QIVGUjs41+UBtdFf/mZgPvyrkZrSiMzhST++uwe+iNs=; b=v2dF2l5kGQncg+YSqxWTBhKkXwDEfb+FO5bTxjZCzATRf6KpEz7cTnmuVuDEfT4sPJ DUz5J5bSRL4VHnFv+3cVWLGSxTe7Rn0lwdC+AMPaMorK4T8i0xxBsnAFE1bZqNMeYRO4 sVy2PMqMzb9cuW//m4grsEsPlRiKrCzFrtDBCLOf1Y1xr7rkp1W4I+pzKUDvo32vqOMr WAeSdO9S8OwvjiOiRS/2a4XFJRUTQLZr46eg5ENFrAOPJ8q6qO+jJrAz4+Fnpb/oXsUV ps0qvWiBzNhggINgIMIqsP+LGG0d1U4z+j7wuzGi04OtWPBz4LSdEcz6VeqtdqTLmKSV PrNQ== X-Gm-Message-State: AOAM530EiHcSkb6n/cHOuju4cbB1DepmfcUjzbueA1UIYzq/2QMeoJuC QmVEMnlkHk26wO7TQkIFvy4= X-Google-Smtp-Source: ABdhPJwwbv2hW46fHq4psw3tyc9kpcHon8oxSjm3y1lmDhVixzxYpzsjl7IzWYUwvvIthjYoIrN/ag== X-Received: by 2002:a17:907:8a17:b0:6e7:28d2:ba51 with SMTP id sc23-20020a1709078a1700b006e728d2ba51mr883255ejc.614.1648910206412; Sat, 02 Apr 2022 07:36:46 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:46 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/16] dt-bindings: clock: convert rockchip,rk3188-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:23 +0200 Message-Id: <20220402143636.15222-4-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3188-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement Changed V3: add Rockchip maintainer on her request fix yamllint line too long Changed V2: change clocks maxItems add clock-names use clock-controller node name remove assigned-xxx --- .../bindings/clock/rockchip,rk3188-cru.txt | 61 ------------- .../bindings/clock/rockchip,rk3188-cru.yaml | 86 +++++++++++++++++++ 2 files changed, 86 insertions(+), 61 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt deleted file mode 100644 index 7f368530a..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3188/RK3066 Clock and Reset Unit - -The RK3188/RK3066 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or - "rockchip,rk3066a-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3188-cru.h and -dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. -Similar macros exist for the reset sources in these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "xin27m" - 27mhz crystal input on rk3066 - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_cif0" - external camera clock - optional, - - "ext_rmii" - external RMII clock - optional, - - "ext_jtag" - externalJTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml new file mode 100644 index 000000000..ff849c729 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3188/RK3066 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3188-cru.h and + dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. + Similar macros exist for the reset sources in these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rk3066a-cru + - rockchip,rk3188-cru + - rockchip,rk3188a-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 7 + + clock-names: + minItems: 1 + maxItems: 7 + items: + enum: + - xin24m + - xin27m + - xin32k + - ext_cif0 + - ext_hsadc + - ext_jtag + - ext_rmii + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90139C433FE for ; Sat, 2 Apr 2022 14:36:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356590AbiDBOin (ORCPT ); Sat, 2 Apr 2022 10:38:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356585AbiDBOil (ORCPT ); Sat, 2 Apr 2022 10:38:41 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB495182D89; Sat, 2 Apr 2022 07:36:48 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id bh17so11385172ejb.8; Sat, 02 Apr 2022 07:36:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5wuju+GcmYHRq1+g1VvLGc9DiGyJBre0gIrOt9rqobw=; b=avp5su2L7EX/jwg6lriJohP1j8I/Nq4bQNRYW5UFYMAwJX0cDeilOfV2oIgUGU5wd1 XafhySaun27VOslvjeenI95S+mBKD5O49ta0aUMMyf/G8j2P1zBtEE58K6Gz+YorWDeX QWeZ3FZnadj0RlUXzfkWNmycQWXpCkJtpKcSi42mc9yUwz8CgekkVJTGGf946pH3/xBF lI74l/c6KZUTxRq/FZGJZ4i22GCwb3geJBFfOetGH9o1vEWYJW4gBoyzyFt9Je5DkXuW gGpBhhvkI0Og4VqgPI3FQsYR9N9CM61TyE8MgmEr1mbSm1aK3f6GjiJty92QFXUreUf9 JkKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5wuju+GcmYHRq1+g1VvLGc9DiGyJBre0gIrOt9rqobw=; b=j9qxZX6IWAN09+LIWZqIPjYlFraY12IPCRsu92y/mkPIF8GgDuzVbo6GW3jPZi0aJZ m8xw8pTf4DBKkDoZQVmbuLozfYCtlRYCm76+rYi1b2qIpySTxTbbu9C0GTEE5HfkghRB Dd2KwWDjlGloqpwSe0k/RiiYYSrW8lx141z6w1eBIRaiR9aj445issHh0lkOZVLY7WvU LeeMiJJRLyf44SJ0e7zt0fHWTLn2RughW+5qHwgYGYRmgx19RuoWHF5btgPLZFk+3yxg WPk36W1EKCDRi3cXzjTyUzbBBCL+hzuOhbLjuwLZWoQuiPa5Q1lOwoVl8dFche6z7ZMm wRTQ== X-Gm-Message-State: AOAM531LfA+dwbPMpnXp7jT/W7ZgfsiA4qeswHhELaZq20i88xSrXq5U +ryOh7MJwbD9O/A3MkuLmMY= X-Google-Smtp-Source: ABdhPJy+WWzYHb7E1VcYub3CXzv5wWc1U+pq1/5Ev2buxP2+8x9LYC16fYRchAXleRmqyNxCKqTvJw== X-Received: by 2002:a17:907:7704:b0:6cf:48ac:b4a8 with SMTP id kw4-20020a170907770400b006cf48acb4a8mr3914724ejc.305.1648910207334; Sat, 02 Apr 2022 07:36:47 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:47 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/16] dt-bindings: clock: convert rockchip,rk3228-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:24 +0200 Message-Id: <20220402143636.15222-5-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3228-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement --- .../bindings/clock/rockchip,rk3228-cru.txt | 58 ------------- .../bindings/clock/rockchip,rk3228-cru.yaml | 82 +++++++++++++++++++ 2 files changed, 82 insertions(+), 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt deleted file mode 100644 index f32304812..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3228 Clock and Reset Unit - -The RK3228 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3228-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional - - "phy_50m_out" - output clock of the pll in the mac phy - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10110000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10110000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml new file mode 100644 index 000000000..0a91c5dc9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3228 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3228 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rk3228-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + items: + enum: + - xin24m + - ext_i2s + - ext_gmac + - ext_hsadc + - phy_50m_out + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 734C3C4167E for ; Sat, 2 Apr 2022 14:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356594AbiDBOin (ORCPT ); Sat, 2 Apr 2022 10:38:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356578AbiDBOil (ORCPT ); Sat, 2 Apr 2022 10:38:41 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB169182D96; Sat, 2 Apr 2022 07:36:49 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id i27so4263855ejd.9; Sat, 02 Apr 2022 07:36:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4sJAGR00sQPyOa2NU6Kbyt+hZau/MXPRKhM5pgnXKBk=; b=nSX9fb1plzvZ8Fzbh6lDWAeF2413rghTIuHHV7jUMZEmWpfKljublWpjDg9xSVwPmU 5maN3DQhb1xh1LGSQRKfXUOvwnun1NLQTqIf86MH5vUqvKSV0XCzfFjdTJD3Gculn+qt kfR7+8cWZ7HpXAMeEjPfjJnuGjKXrNRDqnGRUEsiHgXqoRqOlEFKWSeh5Co+Ehw/sW9d akAsexFf5b2vD4OwgfrTTWgj9n3ScWe4MMvASNWVO3SpocPl8uky5WZMFqlEmjYo/Xlv 49igTm1MeW0W7oRKPrUX0t62lYwLPbuFDsPETsWqcAk446julRqLLIqxQmWpnATKlzqs 3BXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4sJAGR00sQPyOa2NU6Kbyt+hZau/MXPRKhM5pgnXKBk=; b=uXHhJt+Fr0lmTCPO6ytswSgDV7hxa0P2fV/vaDdbELT843Ch3i3q3EQAsjDb5ICyPe WLXPIiXR8dOoIE1S5r0y4PQrjXeao9444ZNdoFwnmpvH4jhEk2NicV647MFqiwjta6NU hB7/HTtXNpri05ZQ5HGrrXJIBsjUIbOGRyHoS2kCTf0jB9Zx2/DCHUjrMsW3E8vOar0r OylJi4cDqt8XvFCW/CGTH8jZN4UVemLJe2TlCgA9k+g3cqZZPYigiNZvn/GdumCaFeIm ph/Ds6cfhZGrJQab2WMnG4yD/ZeDNRw3j7RHPiYYz/z/t2pEHvZOy6CjVAJvsz+orRfz vjOQ== X-Gm-Message-State: AOAM531ulE4Pl9U+8x3unz1x8+XM3glVKrH0f1i4vvGjDZMXXRUeq+AD vQs/kV0uXeYyr4AFBOEaV87J5OrW4Gk= X-Google-Smtp-Source: ABdhPJwUDASQKnl3UVkOThXossDxGeZHDcmYNFHcd6uJ8J+iXty3WoVJI3QJE2Ya1Uh+nRCJNTJKEg== X-Received: by 2002:a17:907:7295:b0:6e6:d8c7:5b4b with SMTP id dt21-20020a170907729500b006e6d8c75b4bmr1651189ejc.606.1648910208241; Sat, 02 Apr 2022 07:36:48 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:47 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/16] dt-bindings: clock: convert rockchip,rk3288-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:25 +0200 Message-Id: <20220402143636.15222-6-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3288-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement Changed V2: add Rockchip maintainer on her request fix yamllint line too long restyle --- .../bindings/clock/rockchip,rk3288-cru.txt | 67 ------------- .../bindings/clock/rockchip,rk3288-cru.yaml | 93 +++++++++++++++++++ 2 files changed, 93 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index bf3a9ec19..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -A revision of this SoC is available: rk3288w. The clock tree is a bit -different so another dt-compatible is available. Noticed that it is only -setting the difference but there is no automatic revision detection. This -should be performed by bootloaders. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in - case of this revision of Rockchip rk3288. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml new file mode 100644 index 000000000..558e5a094 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3288 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3288 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + + A revision of this SoC is available: rk3288w. The clock tree is a bit + different so another dt-compatible is available. Noticed that it is only + setting the difference but there is no automatic revision detection. This + should be performed by boot loaders. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rk3288-cru + - rockchip,rk3288w-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 8 + + clock-names: + minItems: 1 + maxItems: 8 + items: + enum: + - xin24m + - xin32k + - ext_i2s + - ext_hsadc + - ext_edp_24m + - ext_vip + - ext_isp + - ext_jtag + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0xff760000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B480BC433EF for ; Sat, 2 Apr 2022 14:37:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356622AbiDBOi5 (ORCPT ); Sat, 2 Apr 2022 10:38:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356564AbiDBOim (ORCPT ); Sat, 2 Apr 2022 10:38:42 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B66DA181B19; Sat, 2 Apr 2022 07:36:50 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id qh7so1398596ejb.11; Sat, 02 Apr 2022 07:36:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=McFpQ5/hW4Zbu4Ht8+BLpCgdUXBbUIZ2u7Nful4GDGM=; b=CnkrWwg6ioIxsLmOZcg3Ae61uiEygQtLuvT17CHCUiEYmLqsKPLFhHKsNC5XJcLkC9 z9DBA+3MQg/zDKo9j3fAn6s7rPu06EZk0o9P8VH9UeBrABB5cGvmEb2JOtcBGUZixHGI y2URA+odVgsW/AB9CoqA3Z1dz5yo31ykqaP0Bav13LX+1IMC5z9Q03L2MU1I5e1qDxXL sD0e6ZLKUcWPlUwu0u7yXj+GQGDwfi4ukto2UZd6KOo/atEJAQO1GL/M1a9lIB8dAv7L hBqs7DnY/22R6Tdkmrmr5zbRpoTaYGaEGJNO4y8vCpMsfx5wkTBp9FBcOLJkom1Vi22j oQeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=McFpQ5/hW4Zbu4Ht8+BLpCgdUXBbUIZ2u7Nful4GDGM=; b=Z77Jm3iEszC0H4QFL4HFcseaSCwBcVPAbNCkLho/w5mUfvBCyukMhYIAo5V1gIQx6W 4rRGNETH1sAq5FoJTL4B66NcBybiExwxOFMc1t9XTdnGq7/eJuj482jg4wIVi6YmOUo/ nPb1jtqldleQ8j4HB48P8oJQfF3DT9b/hK2nx62f9p93brBbWvn+ZQagEkwGXdm5Djmq O1P5OH1y8un6ACPa5rwHAT/Io0XCqYIxZTbmyJHS1fzWVHae+ffsvKZHI5t0YfXswlCQ 0PH8mMU1X+9n5/ZYCxc2OhfOqKeSWmUEJJDlLqJFWdZndwuCYr5+heOqOzf7jZ9Z6HQg Xkgw== X-Gm-Message-State: AOAM531FNOTfTYMq9i1bvmIh5XhfdO0R64Me5aqXo1M/UvbhQC8M09+7 0XjSejI4fNEDjtNWOMKFEe4= X-Google-Smtp-Source: ABdhPJzpTeP7eaTWHqyR4NNPQDqgajKijKBnn1fgmM99LPS0+oVSq68qsxMPcdcn+EUwY81sEQ1ufw== X-Received: by 2002:a17:907:2d8d:b0:6df:a06c:7c55 with SMTP id gt13-20020a1709072d8d00b006dfa06c7c55mr4054714ejc.325.1648910209152; Sat, 02 Apr 2022 07:36:49 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:48 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/16] dt-bindings: clock: convert rockchip,rk3308-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:26 +0200 Message-Id: <20220402143636.15222-7-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3308-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement --- .../bindings/clock/rockchip,rk3308-cru.txt | 60 ------------- .../bindings/clock/rockchip,rk3308-cru.yaml | 86 +++++++++++++++++++ 2 files changed, 86 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt deleted file mode 100644 index 9b151c5b0..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Rockchip RK3308 Clock and Reset Unit - -The RK3308 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: CRU should be "rockchip,rk3308-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in", - "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in", - "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional, - - "mac_clkin" - external MAC clock - optional - -Example: Clock controller node: - - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml new file mode 100644 index 000000000..01f2d1690 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3308 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3308 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rk3308-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 9 + + clock-names: + minItems: 1 + maxItems: 9 + items: + enum: + - xin24m + - xin32k + - mac_clkin + - mclk_i2s0_2ch_in + - mclk_i2s1_2ch_in + - mclk_i2s0_8ch_in + - mclk_i2s1_8ch_in + - mclk_i2s2_8ch_in + - mclk_i2s3_8ch_in + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff500000 { + compatible = "rockchip,rk3308-cru"; + reg = <0xff500000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 166FFC433F5 for ; Sat, 2 Apr 2022 14:37:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356645AbiDBOi6 (ORCPT ); Sat, 2 Apr 2022 10:38:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356595AbiDBOin (ORCPT ); Sat, 2 Apr 2022 10:38:43 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 907DD181B13; Sat, 2 Apr 2022 07:36:51 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id yy13so11446475ejb.2; Sat, 02 Apr 2022 07:36:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gDX6XR3jVDm9yWJ+XzR+YFdJXpUjQXrovXJ8YXoJ/eQ=; b=Gkcp8k95sTeZEk8ouc+Cz0NB5BQTPfw9R9dJ5Q1aGu6JQ4E+2wJuYyFT3PY9hcZcy1 HVvbItxziBvdTE95+7S+Z4pZ7EVz44W+pLxU4OTDCxqpNIEBZ+OpaGTQD1HNSpLI6P9K 1Zo7OY9F1u4i8U4TjwPZwsMrJ8cM9E2yKyba1siqaiw7T7WP5l0kt3v4+ZeQsLYiBqtX xF0ahmQsB6PMLPpxh6VYMBHIEC5UeKJ10JD3WcYU3Gbwbxc68L4HPcDvtKoxc3CmtoM9 lGhlD48L3rczzHKysiYUxi6yEZ5Q8doxOP9MNE773DBjePlQlq5iDvpCzpMvwe/l8OPk eR2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gDX6XR3jVDm9yWJ+XzR+YFdJXpUjQXrovXJ8YXoJ/eQ=; b=vsWoaeNj0187tTosILrf68O7jLJbPehiIwh1H+8knUk8VJ8VE+gmQp1F4RuOYRHnex f6h3hpC8V/95KNRRY63tSFAtnyboRrC/6rruhANn10gESrkj0BYs/aIi83K0U+Y6OBhc g6vZlK5OT10TNjD/Hj09sH7GRX8aWPX4PX6wdYP6WSRUE9/IyTPUkmIl3oLtfbDwjqR4 KPLRTGsKxdTZ8vnp+lMj7Ank4W/A4tG4p/86SQz1lXLUlu6bAMESxmZiIScE2Kgtw91/ ECiWqUjgB+YMI6IorJGmbuoRXfiqRg0/rXdRcVv1jEzu3w/1wW1X5Ivjh9ovkEkPCeal OO0Q== X-Gm-Message-State: AOAM533UkSqvzeD99uOi7p6SRYk6G/1T2+8GYb6HHGiF6L7W32UTfNb2 x0qbJRVBx73dQw6uhuhvrcg= X-Google-Smtp-Source: ABdhPJxDsZ0j8m7pCLEC+sxvbQOm35l111ofY5I/W40A9SpsH55KuoLgxiZNEbcTmIxdLc1g3Li69g== X-Received: by 2002:a17:907:6e03:b0:6e0:15ce:77ba with SMTP id sd3-20020a1709076e0300b006e015ce77bamr3988665ejc.67.1648910210153; Sat, 02 Apr 2022 07:36:50 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:49 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/16] dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:27 +0200 Message-Id: <20220402143636.15222-8-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3328-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement --- .../bindings/clock/rockchip,rk3328-cru.txt | 58 ------------- .../bindings/clock/rockchip,rk3328-cru.yaml | 82 +++++++++++++++++++ 2 files changed, 82 insertions(+), 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt deleted file mode 100644 index 904ae682e..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3328 Clock and Reset Unit - -The RK3328 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3328-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "clkin_i2s" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - - "phy_50m_out" - output clock of the pll in the mac phy - - "hdmi_phy" - output clock of the hdmi phy pll - optional - -Example: Clock controller node: - - cru: clock-controller@ff440000 { - compatible = "rockchip,rk3328-cru"; - reg = <0x0 0xff440000 0x0 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff120000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff120000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml new file mode 100644 index 000000000..965f67be3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3328 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3328 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rk3328-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + items: + enum: + - xin24m + - clkin_i2s + - gmac_clkin + - hdmi_phy + - phy_50m_out + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff440000 { + compatible = "rockchip,rk3328-cru"; + reg = <0xff440000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E1A0C4332F for ; Sat, 2 Apr 2022 14:37:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356675AbiDBOjA (ORCPT ); Sat, 2 Apr 2022 10:39:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356597AbiDBOio (ORCPT ); Sat, 2 Apr 2022 10:38:44 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80B9E182D8A; Sat, 2 Apr 2022 07:36:52 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id bh17so11385337ejb.8; Sat, 02 Apr 2022 07:36:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2aGoR+jxGDzn8cgNTtv9/Wz52MpH/aK9EVPCLp/ehIM=; b=ikSmNvyPeCmAtCK60FrPC5QI4QD8u3dzi7SFtTmYR496NfMiTk8b5Dl39Y0zvp/jC8 IM8bYf2NPzpzlihE4OBUu2VqwXhXtgbYJr2i+nhcHEy58gdLz1yI7NiDrc6Py+4IWi/J qCb4hvKBYmsPqijBuW9cuTQ0VkVoRI2l4tf2VIGskizoiNP6VY+C/7I3sJJwf6Mt6LHh C2EbJ2ea5OgCwEdIe73JzUmuHA0/c15H6hLK53wccqG+MUcuctoa4z0YBb+nyw32M04B Tf8r8pkvmUh75AcQGMB9P3Jn5Gql6rEJxwuzwzplrPjPK53waSKt+VbnEH3R/S2JK8PF lvpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2aGoR+jxGDzn8cgNTtv9/Wz52MpH/aK9EVPCLp/ehIM=; b=NzEvV9h3NIn7n5JHau+RlcL+q/Ha0JxSabhdQGh/pCFnCMSMni3BBLY+qWMgC2/JQZ e0JLPgUetJg4BzTFtCLgXtxt60TVKEp682laK3dvboXAzBJwchaVTpR2mgawi6N7An3b P6vB6Cn6fc0PoYLjp5kCC/47bkkfwcV5FxcooFeMDNfz0W0Frd6TN+so5jtUZP+C2BBH tIXWohjTaGwkG79EGaLmSGl5MKUQJuMffgJr270iw1+5oU26D+Fd87cAQ4djUQXMSgvT 5WzbKdnbGZlEmX/WN0ShQhkxesAKh4MZTLWXJGta6N+iOTJ1EwVyjMAc9KgUwTYODabB SH5g== X-Gm-Message-State: AOAM533d8wCX/X8XazT7NGP5YKFQlHipJ5fZvjBQOmSaquzVfmqBmDOw /L0/AxLRgMympUyxYXeCEzA= X-Google-Smtp-Source: ABdhPJxi9Qq9lRX++GDHOv/U4QNe8vF8sPKa2MqR4wILfaeO88cZNIUGrkotlOQi22yA9u5y56mrBQ== X-Received: by 2002:a17:906:a398:b0:6ce:71b:deff with SMTP id k24-20020a170906a39800b006ce071bdeffmr3974682ejz.204.1648910211054; Sat, 02 Apr 2022 07:36:51 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:50 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/16] dt-bindings: clock: convert rockchip,rk3368-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:28 +0200 Message-Id: <20220402143636.15222-9-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rk3368-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement --- .../bindings/clock/rockchip,rk3368-cru.txt | 61 ------------- .../bindings/clock/rockchip,rk3368-cru.yaml | 86 +++++++++++++++++++ 2 files changed, 86 insertions(+), 61 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt deleted file mode 100644 index 7c8bbcfed..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3368 Clock and Reset Unit - -The RK3368 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3368-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - - "ext_vip" - external VIP clock - optional, - - "usbotg_out" - output clock of the pll in the otg phy - -Example: Clock controller node: - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3368-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml new file mode 100644 index 000000000..b09d169c7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3368 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3368 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rk3368-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 9 + + clock-names: + minItems: 1 + maxItems: 9 + items: + enum: + - xin24m + - xin32k + - ext_i2s + - ext_gmac + - ext_hsadc + - ext_isp + - ext_jtag + - ext_vip + - usbotg_out + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3368-cru"; + reg = <0xff760000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 845FDC433F5 for ; Sat, 2 Apr 2022 14:37:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356662AbiDBOi6 (ORCPT ); Sat, 2 Apr 2022 10:38:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356610AbiDBOi5 (ORCPT ); Sat, 2 Apr 2022 10:38:57 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60385182D96; Sat, 2 Apr 2022 07:36:53 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id ot30so1483788ejb.12; Sat, 02 Apr 2022 07:36:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RI0GoRc5b1X0/vt9l1Smbq3N/ifsIvAYcPQbiupDesQ=; b=Fu/AyvztsYDGFE4E4SbHfWP3jdau9pB/RhNZtRTr4NEiw1+HpAsmxypnrgc3eRo3PN yxf7tfLd/8WleFomFsQAFVAY2P2s11ZRRnRrZDtw6JfaQX+dJG0N3l7Mg4jCkNX5Nh9f 7LNzDlVxDYDHMvD2pAAMU2aPPNEx2HFh9DuVW/ZkJsmpEnVmai2WkRHnGLOzt0AX2lSG sTc76KvIh0+DE/bEG3jQSnXA1hKyGlHzCu+17XZqm0ITfxmpJkyjHzjvswUCf1Qe9Rzh jnZChEKN2Gxe/yjqtbMXag8rAHfE7Tfq4IYhvSiWw4fDr75CM0UfpLlZ9vqJfcbLNBV3 nbTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RI0GoRc5b1X0/vt9l1Smbq3N/ifsIvAYcPQbiupDesQ=; b=Kpkd+wreo5UytwZjmGJ8zHmYF5wuhtWiINCPwi+Smf7EM82luuFbcgKlPC5sBjYlFZ JLfWvhtXSUqsZdOfPXq1KLz9C45AB8j3rBSXaOjXYJEB8jbNLu+Q/imbDcLikwOR1ALi ka4X4bBwrefRZvNYgF6CSTcGkX3fTC9acPblnZRAx8P6k9iz2CVYCFj99rCFDieGvQ6O rGHf/4fzMdr9WRE1N2RXvwIW7w9fCiShfH3h8zB/H7q5z2ZHi4dy7EwP4lcPDkBe++1S KHPihAenJBfRJz3zO301JJa5oFiYLj9RM+tIa0gim7GU0+g1PNiT0L+RgdJyJvv37CWI 6+kQ== X-Gm-Message-State: AOAM5321b4P2fQAIS2+DpUbVcJtTMdEgskncsqnsCfSIZbdnh0Tlde97 O05l+jf8oqbRmf/rTxwoBuq3o85UIOk= X-Google-Smtp-Source: ABdhPJxjvkr5bVULkIKPFJH4QLeCWNip5rPSmhjzRxv3NkzjaHPu80dIevC+y3oKx/F/XxZBhky4fA== X-Received: by 2002:a17:907:60cf:b0:6db:f0a6:74af with SMTP id hv15-20020a17090760cf00b006dbf0a674afmr3927634ejc.317.1648910211938; Sat, 02 Apr 2022 07:36:51 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:51 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/16] dt-bindings: clock: convert rockchip,rv1108-cru.txt to YAML Date: Sat, 2 Apr 2022 16:36:29 +0200 Message-Id: <20220402143636.15222-10-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert rockchip,rv1108-cru.txt to YAML. Changes against original bindings: Add clocks and clock-names because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: add more clocks add clocks to example add clocks requirement --- .../bindings/clock/rockchip,rv1108-cru.txt | 59 ------------- .../bindings/clock/rockchip,rv1108-cru.yaml | 83 +++++++++++++++++++ 2 files changed, 83 insertions(+), 59 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt deleted file mode 100644 index 161326a4f..000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Rockchip RV1108 Clock and Reset Unit - -The RV1108 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rv1108-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_vip" - external VIP clock - optional - - "ext_i2s" - external I2S clock - optional - - "ext_gmac" - external GMAC clock - optional - - "hdmiphy" - external clock input derived from HDMI PHY - optional - - "usbphy" - external clock input derived from USB PHY - optional - -Example: Clock controller node: - - cru: cru@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml new file mode 100644 index 000000000..abbfdfae8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1108 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RV1108 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. + +properties: + compatible: + enum: + - rockchip,rv1108-cru + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + items: + enum: + - xin24m + - ext_gmac + - ext_i2s + - ext_vip + - hdmiphy + - usbphy + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Sat Apr 2 14:36:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFC03C433FE for ; Sat, 2 Apr 2022 14:37:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356678AbiDBOjA (ORCPT ); Sat, 2 Apr 2022 10:39:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356612AbiDBOi5 (ORCPT ); Sat, 2 Apr 2022 10:38:57 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C8A6182D9D; Sat, 2 Apr 2022 07:36:54 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id ot30so1483853ejb.12; Sat, 02 Apr 2022 07:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+72+q1Txcd0x+KfNjt3ACd6ZcebuPkaO0L/4gKOj9+0=; b=oTJu+xsN8ywcQNmH772d3KN5prhrg21w4+tEM+sA02t5NmTbGwRiJnlFt1GjR41pu7 DnepmW2CR8HUomcZmq1yHep8leDOECqj7dP3V5ATAhJLi0hypc7MiW8pFECHxM508nyI OSQnRw6h+g7LoFln3CjrgkW7S5+RNEf+MnF92OcXYMtrVyyiLlBaYDlRX4ngvBq+DvXz Tp1qWLpdQewlKa8wV8qqrQ5Ux4q5XjcFqiQGhIYfvrSTX8jVoMsU4h+TWrBi0yCdM+cs Bbg5zzyGgvmYUhFBVaLAjpYklcycSO83CHte7Vit2P+y4qCYaUs46rRwhX627KIqwXZ6 QnVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+72+q1Txcd0x+KfNjt3ACd6ZcebuPkaO0L/4gKOj9+0=; b=c8YzQ8QNTZ+gZAetXNfS8zLHrzDPVGrSRIKk/eoojvOQr1QtGhKk4vnNPZn1ViE7y5 ythl7lUqdG916VnDPS7lpv6s8CsVDKpKb0UM5qlhmNZbrVtLQtZV6TJSliFK4p3cqdUq mzVaS95CNOXTzLWNplgiztkvysyNmQqtvl9KQmAYZk4+wCa8f1Ru7MBSDAbJlwyK08Oh MKKv1Gdy0m4bcICOZMxBq5txuGhL+7xC0RtsnO3mDck2462ttTvyyhGVySnfUPhyC/n3 viViWD7tNEMMb9+Py1UA0L4I0gPTYJZ+7rlaYky4i26R14Z/x41ViGRQGl0WFQitoQ/d ckLw== X-Gm-Message-State: AOAM531IWjvLc20honbGTZM2mnNrmrHy/EyVjWB5vaiDNWtxHjF3r3V0 zGor2AULiWFMY3QO0nZsY48= X-Google-Smtp-Source: ABdhPJx/A0xgRJhlO6BICgIqz9WDJ5poFGm4p0UJMsgf1vYVei9jL21VvAup7jxV53a7ohORvW2JLw== X-Received: by 2002:a17:906:dc90:b0:6e0:1ef7:638f with SMTP id cs16-20020a170906dc9000b006e01ef7638fmr4147584ejc.234.1648910212849; Sat, 02 Apr 2022 07:36:52 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:52 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/16] ARM: dts: rockchip: add clocks property to Rockchip cru nodes Date: Sat, 2 Apr 2022 16:36:30 +0200 Message-Id: <20220402143636.15222-11-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add clocks and clock-names to the Rockchip cru nodes, because the device has to have at least one input clock. Signed-off-by: Johan Jonker --- Changed V4: combine patches --- arch/arm/boot/dts/rk3036.dtsi | 2 ++ arch/arm/boot/dts/rk3066a.dtsi | 3 ++- arch/arm/boot/dts/rk3188.dtsi | 3 ++- arch/arm/boot/dts/rk322x.dtsi | 2 ++ arch/arm/boot/dts/rk3288.dtsi | 2 ++ arch/arm/boot/dts/rv1108.dtsi | 2 ++ 6 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index ba2b8891b..3894b8d2e 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -330,6 +330,8 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3036-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index c25b9695d..de9915d94 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -202,8 +202,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index a94321e90..cdd4a0bd5 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -195,8 +195,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 5868eb512..2547f46fe 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -484,6 +484,8 @@ cru: clock-controller@110e0000 { compatible = "rockchip,rk3228-cru"; reg = <0x110e0000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 26b9bbe31..487b0e03d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -862,6 +862,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3288-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 448254906..eceaa940b 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -456,6 +456,8 @@ cru: clock-controller@20200000 { compatible = "rockchip,rv1108-cru"; reg = <0x20200000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Sat Apr 2 14:36:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBABBC433F5 for ; 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:53 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 11/16] arm64: dts: rockchip: add clocks property to Rockchip cru nodes Date: Sat, 2 Apr 2022 16:36:31 +0200 Message-Id: <20220402143636.15222-12-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add clocks and clock-names to the Rockchip cru node, because the device has to have at least one input clock. With the addition of new properties also sort the node properties a little bit where needed. Signed-off-by: Johan Jonker --- Changed V4: combine patches --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 5 +++-- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++ arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++++ 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 1cbe21261..2dfa67f1c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -745,10 +745,11 @@ cru: clock-controller@ff500000 { compatible = "rockchip,rk3308-cru"; reg = <0x0 0xff500000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - rockchip,grf = <&grf>; - assigned-clocks = <&cru SCLK_RTC32K>; assigned-clock-rates = <32768>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b822533dc..9c76c288b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -758,6 +758,8 @@ cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index c99da9032..4f0b5feaa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -747,6 +747,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 88f26d89e..ce1cc42ff 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1416,6 +1416,8 @@ pmucru: pmu-clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; @@ -1426,6 +1428,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Sat Apr 2 14:36:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A698C4167B for ; Sat, 2 Apr 2022 14:37:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356657AbiDBOjM (ORCPT ); Sat, 2 Apr 2022 10:39:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356618AbiDBOi5 (ORCPT ); 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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:54 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 12/16] arm64: dts: rockchip: rk3399: use generic node name for pmucru Date: Sat, 2 Apr 2022 16:36:32 +0200 Message-Id: <20220402143636.15222-13-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The node names should be generic, so fix this for the rk3399 pmucru node and rename it to "clock-controller". Signed-off-by: Johan Jonker --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ce1cc42ff..56af1a1d6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1413,7 +1413,7 @@ clock-names = "apb_pclk"; }; - pmucru: pmu-clock-controller@ff750000 { + pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; clocks = <&xin24m>; From patchwork Sat Apr 2 14:36:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C59BC4167B for ; Sat, 2 Apr 2022 14:37:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356655AbiDBOjB (ORCPT ); Sat, 2 Apr 2022 10:39:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356621AbiDBOi5 (ORCPT ); Sat, 2 Apr 2022 10:38:57 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD985182DA9; Sat, 2 Apr 2022 07:36:56 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id f18so1017722edc.5; Sat, 02 Apr 2022 07:36:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uTBoLKmFu3SudRrqJ18gR0Ex2iOqgaqOCTSIcXbzjD4=; b=d2XA5+lbzbqgUClSScxRzK8VZ4PkpUMVTN0uvEH/krKdNx4C1+rVGMAkjyjl5wk6F0 un/rwtokiCwsoqEMKy0SOwqTlDVOQz2srNSeZEd+IvowfEUexyuPGpU7CkIi/vcsK5P0 bk+WbRlafAay2+EHW94cNWP9r7Ym6QahwLQIlWO5ebpwEY5Nd3XKnBpdRXh56Kvk7Bhp 5JnXO/dTunO6BrD2H16p80mMYpj/FKFeE7qT8z6Tc2Xza4hNWlYUVG56ASU/cspgFqmD bE+fwB3TSUeFBbqgZzbFdt9JJRe4ONJFBg9jw21LAIrTQ15iHnU3WcIpSxb4IanrJEZo 0DtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uTBoLKmFu3SudRrqJ18gR0Ex2iOqgaqOCTSIcXbzjD4=; b=Og0EZGTQKslCaAEUL6FktsPh3VNl0u5RGzp6pSJ9TiZC9t6eHO+AmsGS4W3fx7h1ux DbY7qbUQtmcNdrD5pwd8kJfQT5ULX3Y++VchuRWyLo00Q6kDRyGZhq9Aawa2jxqcEVNy c8T9UwBJF2eHA7W/SzKTeuBgvRu558V7JiFpCPBWmUd5QiPdd7kK3pNFJ0nBM8VbujQt 99xzbmEW649HqCyGejoXUtUXve6aPZXrFwYgiL+x8tAdej6PC/lwxQflD0eJBDq7+nUO UFnvCR9gqjPyQgVBYGEwDJaylU9o1vdybRphvfC1dNEY3oj1xDYs3p8IsBVhNLvvybL8 mXNA== X-Gm-Message-State: AOAM530xaL1gO9rdsVeaILsSO2M5eb2AwK2BxOCMgL0mRVgbKkYNC9rV q/t1hHRRNQjG8xOI6UUs9Wg= X-Google-Smtp-Source: ABdhPJzZeLptWSIWN1DIeaKwHOX9srEUgHYaOuX/82OJK1wtowsFIw+5wYQxhBkNlts96i0VQfbncQ== X-Received: by 2002:aa7:db94:0:b0:410:f0e8:c39e with SMTP id u20-20020aa7db94000000b00410f0e8c39emr25102336edt.14.1648910215459; Sat, 02 Apr 2022 07:36:55 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:55 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 13/16] arm64: dts: rockchip: fix compatible string rk3328 cru node Date: Sat, 2 Apr 2022 16:36:33 +0200 Message-Id: <20220402143636.15222-14-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The rockchip,rk3328-cru.txt file was converted to YAML. A DT test of the rk3328 cru node gives notifications regarding the compatible string. Bring it in line with the binding by removing some unused fall back strings. Signed-off-by: Johan Jonker --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 9c76c288b..8ceac0388 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -756,7 +756,7 @@ }; cru: clock-controller@ff440000 { - compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; + compatible = "rockchip,rk3328-cru"; reg = <0x0 0xff440000 0x0 0x1000>; clocks = <&xin24m>; clock-names = "xin24m"; From patchwork Sat Apr 2 14:36:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8BF7C4321E for ; Sat, 2 Apr 2022 14:37:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356651AbiDBOjB (ORCPT ); Sat, 2 Apr 2022 10:39:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356625AbiDBOi5 (ORCPT ); Sat, 2 Apr 2022 10:38:57 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D00D4182DB6; Sat, 2 Apr 2022 07:36:57 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id c10so11311378ejs.13; Sat, 02 Apr 2022 07:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UMzMILXZOYBjEHWGG0NtpE3Gk3RKI6Zuc2PgcEOU4hk=; b=hKH+EKXwHDcVdeec4xKFrNDsZIRyknKca1Lf0IqDKfvplrYbVWQI6lg8AHp/WMaqRr 1kgMP/fsOjJzdh1R9iMh0f1MQiXtPIlKnwURS8zfHuVGs53qVd6QkmBmFKedyB0ww4Bv oQmK7d1B/fsghyO74h6dJXDYP8VlgjIP1ZpESFOCH0Vw1rZQz73TRX7U4kFGXv0YFoKv BYmrjQqzHEDS0Ij8SK1ZUJBNqEmZ7BiOqoo+USngfl6NFbFr+NhlHJ4r11zDNKebbIOR iPGrY8wAE4WBBO+z+iCJ5SLfPLygzHXWTdojFiw5VGi+WD9q0GKDRIXGs2xnO4fCial0 Rz9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UMzMILXZOYBjEHWGG0NtpE3Gk3RKI6Zuc2PgcEOU4hk=; b=7l2ulbvLNoO+4K/0j2n02/5vYmiKK2+lKGtos0nHBUzbTLRcmla5ABf3YPrEYMiq7i rF/hwNEXNqo7PcQbl7yiOJFYbq/Nw2UyVGZ09jD1h2jef/Ad300lSArphiD+vQtm1WmM ZPZ+eL0FrQ/teXIm87ghkoc3hlPAowA3JHP+nJCbmOY/6fWtlkTTLQzoHvQhnuXZdSTA q94RXZcBPJbJXmDOmA0WYxtsukEI1DE4H8fiJUkqRS8mgd7kAvH43rdnN0XJQJGiOiEk m+hF0kpa2H2H/K45x91nYMSJTiUrzMiKASNOhGmTEDMylK1C01YZ9/0U6PxBWhLW9L01 +DLw== X-Gm-Message-State: AOAM532PyZpBUDCTGAxf8mLPeR5+bb10Zyu7vXg5J138Fek95B4aeZZd nAQuj+aTjhbm1C1sgr9cdsA= X-Google-Smtp-Source: ABdhPJzkt4WAyQJZ3jF1iMKFKicysCmRDS+tUpRwZXcfJmmMfXyM7C6JEmced06QohgpOIs1rpC2cQ== X-Received: by 2002:a17:907:1c0a:b0:6da:7ac4:5349 with SMTP id nc10-20020a1709071c0a00b006da7ac45349mr3992797ejc.596.1648910216420; Sat, 02 Apr 2022 07:36:56 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:56 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 14/16] dt-bindings: clock: replace a maintainer for rockchip,rk3399-cru.yaml Date: Sat, 2 Apr 2022 16:36:34 +0200 Message-Id: <20220402143636.15222-15-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org With the rk3399 cru YAML conversion the original text author was somehow added as a maintainer, but who's currently no longer involved on the subject. Replace this position with the Rockchip clock maintainer on her request. Signed-off-by: Johan Jonker --- .../devicetree/bindings/clock/rockchip,rk3399-cru.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml index 72b286a1b..5ee686938 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip RK3399 Clock and Reset Unit maintainers: - - Xing Zheng + - Elaine Zhang - Heiko Stuebner description: | From patchwork Sat Apr 2 14:36:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8344DC4332F for ; Sat, 2 Apr 2022 14:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356660AbiDBOjK (ORCPT ); Sat, 2 Apr 2022 10:39:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356627AbiDBOi5 (ORCPT ); Sat, 2 Apr 2022 10:38:57 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 984A11834C3; Sat, 2 Apr 2022 07:36:58 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id i27so4264419ejd.9; Sat, 02 Apr 2022 07:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mzmU0Dp6HwdkT8Z3OuirJmjfQNObHAqgJgTjMG47n0A=; b=aAJvmM6ItjEgWTXZGaCViiqDWjBz6+wHVzQdkA8YZcefaus3pcCVmi4hu/yGogWBMw NsOpU0o/vLInsxt50G/p7LyhyeTXAyCL7VE5KLYddZ+YFOjMgt6uENIlXUmDioFAATtU /oA6PV3nNuyQpf2qD8dO0hTlLwIoi6Gve0sFXpZf1B50xqKSFG3h/INH4EU9+EuSRTYw MNRtw5w0g7/FhQL5TS133sS7PxJsG7+NDwKAbTMuv8l9fSdLyeoLUd0hiyZvJTdooMre CuaQjr41QjhVOcQuxc7cVKqRgt+zisakKkkqHQtyVjK/lQV8iFZnnhGVgxLBuDNqAJEc zLzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mzmU0Dp6HwdkT8Z3OuirJmjfQNObHAqgJgTjMG47n0A=; b=mj7hCngPSdL070cgFGJZWtfcNtDLlKG/8XZdVeCrr5cb02485D4IIoIx0NAiH5Z5qB uC5VTwrHd/cECaxu2SHrQYmPhkOZAwGPgh9p1Aj43jUSCneAy9oiUYM6q5+ndBwgsmSS +rtTgRp9r2t5Szz90eh6UvH+S0k5JkLNNDJLaNUDeI3w4CP8fAiGYn9WDjFu3+UjVOll q9D3Gb+nlxiehGVprKiIOulS7m8Qn32oXR635Y2UcUnjpD5JAquYxZqByapu5br7Nl6J Kt3a226+xZOxtwVGoz1TK60mBXT2t2Zqcmq08uZTW2jo/0EYA3f/EeAQVAWul5GNqq9K NBnQ== X-Gm-Message-State: AOAM531+12eIcy6Pd6fwk1+2tvzYt/h3l6WWKfu08JUvdcA+PtsW0vgV HuAypTJ3hwpDw8B3iTPwrDE= X-Google-Smtp-Source: ABdhPJy5vDCSDA33e1YaTBNZjVAxvQmIg2J1e3ERyi0Y8CcCnlsMLUqoBKYkj1aRKQ+EF8csYeOy3A== X-Received: by 2002:a17:906:3918:b0:6e0:5bbd:bf33 with SMTP id f24-20020a170906391800b006e05bbdbf33mr3920592eje.764.1648910217228; Sat, 02 Apr 2022 07:36:57 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:56 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 15/16] dt-bindings: clock: use generic node name for pmucru example in rockchip,rk3399-cru.yaml Date: Sat, 2 Apr 2022 16:36:35 +0200 Message-Id: <20220402143636.15222-16-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The node names should be generic, so fix this for the pmucru node example in the rockchip,rk3399-cru.yaml file and rename it to "clock-controller". Signed-off-by: Johan Jonker --- .../devicetree/bindings/clock/rockchip,rk3399-cru.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml index 5ee686938..e91147c84 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -77,7 +77,7 @@ additionalProperties: false examples: - | - pmucru: pmu-clock-controller@ff750000 { + pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0xff750000 0x1000>; #clock-cells = <1>; From patchwork Sat Apr 2 14:36:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Jonker X-Patchwork-Id: 12799326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A898FC433EF for ; Sat, 2 Apr 2022 14:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356640AbiDBOjK (ORCPT ); Sat, 2 Apr 2022 10:39:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356632AbiDBOi6 (ORCPT ); Sat, 2 Apr 2022 10:38:58 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76A961834C6; Sat, 2 Apr 2022 07:36:59 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id c10so11311491ejs.13; Sat, 02 Apr 2022 07:36:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A5SAjUnYFQM9w8TOLgtiKBk9tPwBKnHPcAhw0POhc3g=; b=b+K26tGd8dmMu+pIRWuwIMbEAih1Gm5KNPQz4TaxkahLVAIXTDQOYilQfs8RntMuHl z1o/m88jL57/PMesvniiC8uNJH9XM91PY50+Fe6sr9+CKQM6os9BZO+0TpyKt16jRTTD ViQt0MTtubQNJJf2rVHYmbgOIQxVgCbd4upIBjEWLKJNuxtrXiVkFucspBDYOq46Nmkg puOsAJgpI3321euHAjQ3Twa2TebnTGPh8WPtifqk9tP5a3En2kcYWMnA8BE7Z/mtCPer xADC7oCqHspz098E2cckQ6A2UFWwMhNgZvfFbeVvQba6yXlE4y6EZFiGjPf10ntrc4Cv p4HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A5SAjUnYFQM9w8TOLgtiKBk9tPwBKnHPcAhw0POhc3g=; b=OqmZyrbq3DWMhXj39HV7Ar5X7wknfE9Hewk4q6cwZDPwNmvIr8p4IovV1uUvop3xlS 6uDwCqvPT4SQuD8ymgc+fjJhaqFYid/aVulJiLTR4l4gn/RwiTEffk5dtAa8T7BtTSdJ 0jhlb7S4YYvcZHM0QZkugbvi/C7TlLT9YmbJHd1HsLhQwACtBzfwsEfkPpTQf2AUzml6 ufNzEAbSm7Mhu8COoIwBSibQ2G6qQqWcdkj0lGt7WRF7TBQgMdxObQKumZk2ClrcM+je iJaPCS8FEpK2IWhDP2gPG1svJY1cqxIIfp+sOrWp5I7icxWquMpiwpZkGUNP2rMwoOaN Y7tQ== X-Gm-Message-State: AOAM531bduAgPsjGcnOs0+QdrZTgIOFQJYB7WqCeIGWNcsPLv69IkSZV lctR4J9xH49sKQl1GFh8T7c= X-Google-Smtp-Source: ABdhPJxKiB5huzHM1gmRf9jZL2520dkuPbe0wyAiByFM551Ipm7AyngjKLm0atJYVdkKEmHblocIHg== X-Received: by 2002:a17:906:4fc4:b0:6da:b4c6:fadb with SMTP id i4-20020a1709064fc400b006dab4c6fadbmr4195430ejw.282.1648910218049; Sat, 02 Apr 2022 07:36:58 -0700 (PDT) Received: from debian.home (81-204-249-205.fixed.kpn.net. [81.204.249.205]) by smtp.gmail.com with ESMTPSA id bp8-20020a170907918800b006e0daaa63ddsm2169557ejb.60.2022.04.02.07.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Apr 2022 07:36:57 -0700 (PDT) From: Johan Jonker To: heiko@sntech.de, zhangqing@rock-chips.com Cc: robh+dt@kernel.org, krzk+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 16/16] dt-bindings: clock: fix some conversion clock issues for rockchip,rk3399-cru.yaml Date: Sat, 2 Apr 2022 16:36:36 +0200 Message-Id: <20220402143636.15222-17-jbx6244@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220402143636.15222-1-jbx6244@gmail.com> References: <20220402143636.15222-1-jbx6244@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org With the YAML conversion somehow "assigned-xxx" properties where added. If a proper clock is added to the cru node these properties are no longer needed, so removed them. With the conversion of rockchip,rk3399-cru.txt a table with external clocks was copied. Include these clocks into the schema. Add clocks and clocks-names to example and make them a requirement. Reorder/restyle so that this file is line with the other Rockchip CRU bindings. Signed-off-by: Johan Jonker --- .../bindings/clock/rockchip,rk3399-cru.yaml | 55 ++++++++++--------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml index e91147c84..4574727da 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -20,15 +20,8 @@ description: | used in device tree sources. Similar macros exist for the reset sources in these files. There are several clocks that are generated outside the SoC. It is expected - that they are defined using standard clock bindings with following - clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "clkin_gmac" - external GMAC clock - optional, - - "clkin_i2s" - external I2S clock - optional, - - "pclkin_cif" - external ISP clock - optional, - - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 - - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 + that they are defined using standard clock bindings with the + clock-output-names defined in this schema. properties: compatible: @@ -39,37 +32,41 @@ properties: reg: maxItems: 1 - "#clock-cells": - const: 1 - - "#reset-cells": - const: 1 - clocks: minItems: 1 + maxItems: 7 - assigned-clocks: - minItems: 1 - maxItems: 64 - - assigned-clock-parents: + clock-names: minItems: 1 - maxItems: 64 - - assigned-clock-rates: - minItems: 1 - maxItems: 64 + maxItems: 7 + items: + enum: + - xin24m + - xin32k + - clkin_gmac + - clkin_i2s + - clk_usbphy0_480m + - clk_usbphy1_480m + - pclkin_cif rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle - description: > - phandle to the syscon managing the "general register files". It is used + description: + Phandle to the syscon managing the "general register files". It is used for GRF muxes, if missing any muxes present in the GRF will not be available. + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + required: - compatible - reg + - clocks + - clock-names - "#clock-cells" - "#reset-cells" @@ -80,6 +77,8 @@ examples: pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0xff750000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -87,6 +86,8 @@ examples: cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0xff760000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; #clock-cells = <1>; #reset-cells = <1>; };