From patchwork Mon Apr 4 13:38:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 12800255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99E2BC433F5 for ; Mon, 4 Apr 2022 13:38:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D1AAA10E00B; Mon, 4 Apr 2022 13:38:54 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id DBE0E10E00B; Mon, 4 Apr 2022 13:38:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649079533; x=1680615533; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UMpeyKNRrKSm3EcvkXoFnlv4prmjWPgpum12xxlp/D0=; b=RtHIGwEfO4pwT/cbx8PnlnTxzN126LWudKFScj8oTZHPsIWk237Z/cEQ 3vOVKArCP8qSpXRRdSErzVI3U+wS0CCQHm1b+XC967RvfLMCsujj7ELRt T24ESIDASGPWVa65LjpvzHkjURn7nJwTkhLmIilBXZH9llhXDrqygWR9a akL4lQcNZmi+2scui9bUAa4NYv2DhUOdGlZSlByt4osVFdZP4RqxmGse0 ELjJWxdEZq6XeLMCbTynjjbRMhGZ044nWKlSoo5a29H7rJUyCjLgqwnRs J/oVmwhu4rwgLA7pTvKRxY3iPJYpdAO+NEVDZNI9Mz37qDolTU9Kuntde A==; X-IronPort-AV: E=McAfee;i="6200,9189,10306"; a="321210209" X-IronPort-AV: E=Sophos;i="5.90,234,1643702400"; d="scan'208";a="321210209" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 06:38:53 -0700 X-IronPort-AV: E=Sophos;i="5.90,234,1643702400"; d="scan'208";a="548655969" Received: from ideak-desk.fi.intel.com ([10.237.72.175]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 06:38:51 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression Date: Mon, 4 Apr 2022 16:38:43 +0300 Message-Id: <20220404133846.131401-2-imre.deak@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220404133846.131401-1-imre.deak@intel.com> References: <20220404133846.131401-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nanley Chery , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Matt Roper The render/media engines on DG2 unify render compression and media compression into a single format for the first time, using the Tile 4 layout for main surfaces. The compression algorithm is different from any previous platform and the display engine must still be configured to decompress either a render or media compressed surface; as such, we need new RC and MC framebuffer modifiers to represent buffers in this format. v2: Clarify modifier layout description. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Matt Roper Signed-off-by: Imre Deak Acked-by: Nanley Chery Reviewed-by: Juha-Pekka Heikkila Reviewed-by: Juha-Pekka Heikkila --- include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index b73fe6797fc37..4a5117715db3c 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -583,6 +583,28 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) +/* + * Intel color control surfaces (CCS) for DG2 render compression. + * + * The main surface is Tile 4 and at plane index 0. The CCS data is stored + * outside of the GEM object in a reserved memory area dedicated for the + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The + * main surface pitch is required to be a multiple of four Tile 4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) + +/* + * Intel color control surfaces (CCS) for DG2 media compression. + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface + * pitch is required to be a multiple of four Tile 4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * From patchwork Mon Apr 4 13:38:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 12800256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F35C7C433EF for ; Mon, 4 Apr 2022 13:39:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FDD810E0AE; Mon, 4 Apr 2022 13:39:00 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7112E10F5CF; Mon, 4 Apr 2022 13:38:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649079538; x=1680615538; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A+aL2KuJ6UEihn352iGjxL3BF6UK7i1fl8dUqaYgqzc=; b=fyQi0caPUoIgNg7KsGnVKCqfZg7EEMCvUloMj/GgDMI3SzvyDJwSBH8T XCxHLj/c+BHvTUeTzfCzkfAeyISzQ/a3SiYBr3A0fFw5EhHt58t08MJ2G ng0WGZsdUrGzsudUUIc9Wu9i2MMJCn/3CaNMfX23BK/roEx+4FD7bVKz1 WM/OClqqOUqTuLVLhM1abWwdPtcGl+T92Fhn5XUtC9zkSzHor5cwQ/4gw S/s89Nk1ExlvthsA5D4uDVkQ+5dQWK4sCTnzLPnDwBh0u+ZKuOIxg+YFL h+YBPatkNMPQiWKkVHgAzvItqmjHcglw262q5Chmhb+2c8IAaRr5Ub82H w==; X-IronPort-AV: E=McAfee;i="6200,9189,10306"; a="321210253" X-IronPort-AV: E=Sophos;i="5.90,234,1643702400"; d="scan'208";a="321210253" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 06:38:58 -0700 X-IronPort-AV: E=Sophos;i="5.90,234,1643702400"; d="scan'208";a="548656003" Received: from ideak-desk.fi.intel.com ([10.237.72.175]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 06:38:56 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/4] drm/fourcc: Introduce format modifier for DG2 clear color Date: Mon, 4 Apr 2022 16:38:45 +0300 Message-Id: <20220404133846.131401-4-imre.deak@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220404133846.131401-1-imre.deak@intel.com> References: <20220404133846.131401-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nanley Chery , dri-devel@lists.freedesktop.org, =?utf-8?q?Juha-Pekka_Heikkil=C3=A4?= , Mika Kahola , Anshuman Gupta Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Mika Kahola DG2 clear color render compression uses Tile4 layout. Therefore, we need to define a new format modifier for uAPI to support clear color rendering. v2: Display version is fixed. [Imre] KDoc is enhanced for cc modifier. [Nanley & Lionel] v3: Split out the modifier addition to a separate patch. Clarify the modifier layout description. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Mika Kahola cc: Anshuman Gupta Signed-off-by: Juha-Pekka Heikkilä Signed-off-by: Ramalingam C Signed-off-by: Imre Deak Acked-by: Nanley Chery --- include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 4a5117715db3c..e5074162bcdd4 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -605,6 +605,20 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) +/* + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. + * + * The main surface is Tile 4 and at plane index 0. The CCS data is stored + * outside of the GEM object in a reserved memory area dedicated for the + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The + * main surface pitch is required to be a multiple of four Tile 4 widths. The + * clear color is stored at plane index 1 and the pitch should be ignored. The + * format of the 256 bits of clear color data matches the one used for the + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description + * for details. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks *