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Tue, 5 Apr 2022 10:47:45 +0000 From: Joey Gouly To: CC: , , , , Subject: [PATCH v1] arm64: alternatives: mark patch_alternative() as `noinstr` Date: Tue, 5 Apr 2022 11:47:33 +0100 Message-ID: <20220405104733.11476-1-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 1ac07d57-ba7f-44d2-91c4-08da16f1bcfd X-MS-TrafficTypeDiagnostic: DB8PR08MB5516:EE_|AM5EUR03FT007:EE_|AM9PR08MB6243:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: R9hmGOtX371MUjWcGk2OfcJ1QrH5N3piERez+kjNtt05BSzXU2zqUiYMYZGfcdWQ4Hq8gHAfTDmfWfDp3OoPicbZDYKj02IV5BHJZLjC2j9rw5Hum692zrV+9rvjM23XD32SLfjQ2TX88OUE/3P0Y3ydk8cSFHctGA8RvrD9iHadPCZjP78HDbPLfOWNIMbJx/vllWPRNFgRhivGpozOVeCg1uoMYRjd5c1AG3hYR/5Q3+micD7q2rWF38/U7qnq8Yqnn/vTMySEx4herz1IMQqQ1MJZKatJOdLcDTHxrGI1UFG/nhbaGw+KjI4+gdVQuftuQcbxwcC+K+gEuSI45or5YaQ5S8xiFfBHb25A9KRk9XRmmSVZcy8KZFuvBK57qE2P7epcjN3szIa7mjd+LK4gEIVungwGJWGIp/6NW2mmt+X4HJX34L42mP2l4ag9uOh21vz9yB2QZoa7st97DjgJ8Qxu8YRBBIcdnluhe796FdIVRaSgm1Rtpb4v/UyYLBDXAPVtVcwRIzuC5Hv4eStyWKJHCUO7h8d4gN135LeCjJZN1WxsJ7QjMPNuRhYawe+ZVGboCs6iT+haCixD4S4TVbz6KYxFWK/gvN04o34cOgPpMKTa7fi0AD2orkOneEga8gQuA2VjIgC/2Pct36Bg416UrMDMoiKLY6teiMIPpIM0r5tXhGzw7PqEYevYe8unUnmld60EzgXqD7aSXX8oQXZDaY2/K2Eax94Fmm0= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(2906002)(7696005)(5660300002)(8936002)(86362001)(81166007)(44832011)(6666004)(36756003)(336012)(8676002)(508600001)(2616005)(1076003)(26005)(70206006)(82310400005)(40460700003)(316002)(186003)(4326008)(47076005)(83380400001)(107886003)(6916009)(36860700001)(426003)(54906003)(70586007)(81973001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2022 10:47:53.9541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ac07d57-ba7f-44d2-91c4-08da16f1bcfd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT007.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6243 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220405_034802_720308_01193D22 X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The alternatives code must be `noinstr` such that it does not patch itself, as the cache invalidation is only performed after all the alternatives have been applied. Mark patch_alternative() as `noinstr`. Mark branch_insn_requires_update() and get_alt_insn() with `__always_inline` since they are both only called through patch_alternative(). Booting a kernel in QEMU TCG with KCSAN=y and ARM64_USE_LSE_ATOMICS=y caused a boot hang: [ 0.241121] CPU: All CPU(s) started at EL2 The alternatives code was patching the atomics in __tsan_read4() from LL/SC atomics to LSE atomics. The following fragment is using LL/SC atomics in the .text section: | <__tsan_unaligned_read4+304>: ldxr x6, [x2] | <__tsan_unaligned_read4+308>: add x6, x6, x5 | <__tsan_unaligned_read4+312>: stxr w7, x6, [x2] | <__tsan_unaligned_read4+316>: cbnz w7, <__tsan_unaligned_read4+304> This LL/SC atomic sequence was to be replaced with LSE atomics. However since the alternatives code was instrumentable, __tsan_read4() was being called after only the first instruction was replaced, which led to the following code in memory: | <__tsan_unaligned_read4+304>: ldadd x5, x6, [x2] | <__tsan_unaligned_read4+308>: add x6, x6, x5 | <__tsan_unaligned_read4+312>: stxr w7, x6, [x2] | <__tsan_unaligned_read4+316>: cbnz w7, <__tsan_unaligned_read4+304> This caused an infinite loop as the `stxr` instruction never completed successfully, so `w7` was always 0. Signed-off-by: Joey Gouly Cc: Mark Rutland Cc: Catalin Marinas Cc: Will Deacon --- arch/arm64/kernel/alternative.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c index 3fb79b76e9d9..7bbf5104b7b7 100644 --- a/arch/arm64/kernel/alternative.c +++ b/arch/arm64/kernel/alternative.c @@ -42,7 +42,7 @@ bool alternative_is_applied(u16 cpufeature) /* * Check if the target PC is within an alternative block. */ -static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc) +static __always_inline bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc) { unsigned long replptr = (unsigned long)ALT_REPL_PTR(alt); return !(pc >= replptr && pc <= (replptr + alt->alt_len)); @@ -50,7 +50,7 @@ static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc) #define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1)) -static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr) +static __always_inline u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr) { u32 insn; @@ -95,7 +95,7 @@ static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnp return insn; } -static void patch_alternative(struct alt_instr *alt, +static noinstr void patch_alternative(struct alt_instr *alt, __le32 *origptr, __le32 *updptr, int nr_inst) { __le32 *replptr;