From patchwork Tue Apr 5 14:53:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12801695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 205F2C433F5 for ; Tue, 5 Apr 2022 14:54:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B6F810E764; Tue, 5 Apr 2022 14:54:20 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 82A9B10E91C; Tue, 5 Apr 2022 14:54:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649170457; x=1680706457; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BH6rhIiByOXzo9zRMRtLAntr271Y6ajSjCNhzEAAA0E=; b=DXZgyNB61179BRKy4WbHRGbMoSZNImjnLb5d9yRGVx19gXP+NxrYbBlc 8zHFDr3ZJe8/s9g1oJPVAOzCZocRFCbZ9r8u30imWha/IiDUde6v0+wXT 0Zew5oYb3+pXW660jdAubmoVyb0dYPQacm/cPA4YVUc8TCP9QeH1OO22O PeHG6odsexXGODTi7om6KwHAujCVWxamMi/++Z4BlO0cvilSrycYxIJMs de7xewsBM8v7R7j6eZDBB5xm6caSkICA+bOwwlhOFIMGWOxTb2ukRY7Qw hAjx6sD7k1cGWSB0QJOf/hH5/S/kb0gUNYT1k17Sma2Qg8LFq04taWKL/ w==; X-IronPort-AV: E=McAfee;i="6200,9189,10307"; a="241353395" X-IronPort-AV: E=Sophos;i="5.90,236,1643702400"; d="scan'208";a="241353395" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2022 07:54:17 -0700 X-IronPort-AV: E=Sophos;i="5.90,236,1643702400"; d="scan'208";a="608470336" Received: from pmulcahy-mobl.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.235.32]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2022 07:54:15 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 1/3] drm/i915: Make some recently added vfuncs use full scheduling attribute Date: Tue, 5 Apr 2022 15:53:43 +0100 Message-Id: <20220405145345.3284084-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220405145345.3284084-1-tvrtko.ursulin@linux.intel.com> References: <20220405145345.3284084-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Brost , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Code added in 71ed60112d5d ("drm/i915: Add kick_backend function to i915_sched_engine") and ee242ca704d3 ("drm/i915/guc: Implement GuC priority management") introduced some scheduling related vfuncs which take integer request priority as argument. Make them instead take struct i915_sched_attr which is the type encapsulating this information. This better aligns with the codebase and enables transparently extending the internal data passed along the scheduling call chains. Signed-off-by: Tvrtko Ursulin Cc: Matthew Brost Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 +++- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 ++- drivers/gpu/drm/i915/i915_scheduler.c | 4 ++-- drivers/gpu/drm/i915/i915_scheduler_types.h | 4 ++-- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index f8749c433b7c..8b04c6e4c006 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -3273,11 +3273,13 @@ static bool can_preempt(struct intel_engine_cs *engine) return engine->class != RENDER_CLASS; } -static void kick_execlists(const struct i915_request *rq, int prio) +static void kick_execlists(const struct i915_request *rq, + const struct i915_sched_attr *attr) { struct intel_engine_cs *engine = rq->engine; struct i915_sched_engine *sched_engine = engine->sched_engine; const struct i915_request *inflight; + const int prio = attr->priority; /* * We only need to kick the tasklet once for the high priority diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index e1612c393781..2d5193a9a1d3 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3520,9 +3520,10 @@ static void guc_init_breadcrumbs(struct intel_engine_cs *engine) } static void guc_bump_inflight_request_prio(struct i915_request *rq, - int prio) + const struct i915_sched_attr *attr) { struct intel_context *ce = request_to_scheduling_context(rq); + const int prio = attr->priority; u8 new_guc_prio = map_i915_prio_to_guc_prio(prio); /* Short circuit function */ diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 762127dd56c5..534bab99fcdc 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -255,7 +255,7 @@ static void __i915_schedule(struct i915_sched_node *node, /* Must be called before changing the nodes priority */ if (sched_engine->bump_inflight_request_prio) - sched_engine->bump_inflight_request_prio(from, prio); + sched_engine->bump_inflight_request_prio(from, attr); WRITE_ONCE(node->attr.priority, prio); @@ -280,7 +280,7 @@ static void __i915_schedule(struct i915_sched_node *node, /* Defer (tasklet) submission until after all of our updates. */ if (sched_engine->kick_backend) - sched_engine->kick_backend(node_to_request(node), prio); + sched_engine->kick_backend(node_to_request(node), attr); } spin_unlock(&sched_engine->lock); diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h index b0a1b58c7893..24b9ac1c2ce2 100644 --- a/drivers/gpu/drm/i915/i915_scheduler_types.h +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h @@ -177,13 +177,13 @@ struct i915_sched_engine { * @kick_backend: kick backend after a request's priority has changed */ void (*kick_backend)(const struct i915_request *rq, - int prio); + const struct i915_sched_attr *attr); /** * @bump_inflight_request_prio: update priority of an inflight request */ void (*bump_inflight_request_prio)(struct i915_request *rq, - int prio); + const struct i915_sched_attr *attr); /** * @retire_inflight_request_prio: indicate request is retired to From patchwork Tue Apr 5 14:53:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12801694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACA24C433F5 for ; Tue, 5 Apr 2022 14:54:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF0C310E72F; Tue, 5 Apr 2022 14:54:19 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA01D10E8F2; Tue, 5 Apr 2022 14:54:18 +0000 (UTC) DKIM-Signature: v=1; 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05 Apr 2022 07:54:17 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 2/3] drm/i915: Inherit process nice for context scheduling priority Date: Tue, 5 Apr 2022 15:53:44 +0100 Message-Id: <20220405145345.3284084-3-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220405145345.3284084-1-tvrtko.ursulin@linux.intel.com> References: <20220405145345.3284084-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Introduce the concept of context nice value which matches the process nice. We do this by extending the struct i915_sched_attr and add a helper (i915_sched_attr_priority) to be used to convert to effective priority when used by backend code and for priority sorting. Context nice is then inherited from the process which creates the GEM context and utilised secondary to context priority, but only when the latter has been left at the default setting in order to avoid disturbing any application made choices of low and high (batch processing and maybe latency sensitive compositing). In this case nice value adjusts the effective priority in the narrow band of -19 to +20 around I915_CONTEXT_DEFAULT_PRIORITY. This means that userspace using the context priority uapi directly has a wider range of possible adjustments (in practice that only applies to execlists platforms - with GuC there are only three priority buckets), but in all cases nice adjustment has the expected effect: positive nice lowering the scheduling priority and negative nice raising it. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +++++- .../gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- drivers/gpu/drm/i915/i915_request.c | 2 +- drivers/gpu/drm/i915/i915_request.h | 5 +++++ drivers/gpu/drm/i915/i915_scheduler.c | 12 ++++++++---- drivers/gpu/drm/i915/i915_scheduler.h | 14 ++++++++++++++ drivers/gpu/drm/i915/i915_scheduler_types.h | 8 ++++++++ 8 files changed, 44 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index ab4c5ab28e4d..1d772cc87ae6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -294,6 +294,7 @@ proto_context_create(struct drm_i915_private *i915, unsigned int flags) if (i915->params.enable_hangcheck) pc->user_flags |= BIT(UCONTEXT_PERSISTENCE); pc->sched.priority = I915_PRIORITY_NORMAL; + pc->sched.nice = task_nice(current); if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) { if (!HAS_EXECLISTS(i915)) { @@ -914,8 +915,11 @@ static int set_proto_ctx_param(struct drm_i915_file_private *fpriv, case I915_CONTEXT_PARAM_PRIORITY: ret = validate_priority(fpriv->dev_priv, args); - if (!ret) + if (!ret) { pc->sched.priority = args->value; + if (args->value == I915_CONTEXT_DEFAULT_PRIORITY) + pc->sched.nice = task_nice(current); + } break; case I915_CONTEXT_PARAM_SSEU: diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 8b04c6e4c006..eb035cd73bc5 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -254,7 +254,7 @@ static struct i915_priolist *to_priolist(struct rb_node *rb) static int rq_prio(const struct i915_request *rq) { - return READ_ONCE(rq->sched.attr.priority); + return i915_request_priority(rq); } static int effective_prio(const struct i915_request *rq) @@ -3278,8 +3278,8 @@ static void kick_execlists(const struct i915_request *rq, { struct intel_engine_cs *engine = rq->engine; struct i915_sched_engine *sched_engine = engine->sched_engine; + const int prio = i915_sched_attr_priority(attr); const struct i915_request *inflight; - const int prio = attr->priority; /* * We only need to kick the tasklet once for the high priority diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 2d5193a9a1d3..a60118461750 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3523,7 +3523,7 @@ static void guc_bump_inflight_request_prio(struct i915_request *rq, const struct i915_sched_attr *attr) { struct intel_context *ce = request_to_scheduling_context(rq); - const int prio = attr->priority; + const int prio = i915_sched_attr_priority(attr); u8 new_guc_prio = map_i915_prio_to_guc_prio(prio); /* Short circuit function */ diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 582770360ad1..960bfd517ff7 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -2093,7 +2093,7 @@ static int print_sched_attr(const struct i915_sched_attr *attr, return x; x += snprintf(buf + x, len - x, - " prio=%d", attr->priority); + " prio=%d nice=%d", attr->priority, attr->nice); return x; } diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index 28b1f9db5487..57648206bdc6 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -439,6 +439,11 @@ long i915_request_wait(struct i915_request *rq, #define I915_WAIT_PRIORITY BIT(1) /* small priority bump for the request */ #define I915_WAIT_ALL BIT(2) /* used by i915_gem_object_wait() */ +static inline int i915_request_priority(const struct i915_request *rq) +{ + return i915_sched_attr_priority(&rq->sched.attr); +} + void i915_request_show(struct drm_printer *m, const struct i915_request *rq, const char *prefix, diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 534bab99fcdc..e75793e36454 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -155,7 +155,9 @@ lock_sched_engine(struct i915_sched_node *node, static void __i915_schedule(struct i915_sched_node *node, const struct i915_sched_attr *attr) { - const int prio = max(attr->priority, node->attr.priority); + const int prio = + max(i915_sched_attr_priority(attr), + i915_sched_attr_priority(&node->attr)); struct i915_sched_engine *sched_engine; struct i915_dependency *dep, *p; struct i915_dependency stack; @@ -209,7 +211,7 @@ static void __i915_schedule(struct i915_sched_node *node, if (node_signaled(p->signaler)) continue; - if (prio > READ_ONCE(p->signaler->attr.priority)) + if (prio > i915_sched_attr_priority(&p->signaler->attr)) list_move_tail(&p->dfs_link, &dfs); } } @@ -247,7 +249,8 @@ static void __i915_schedule(struct i915_sched_node *node, lockdep_assert_held(&sched_engine->lock); /* Recheck after acquiring the engine->timeline.lock */ - if (prio <= node->attr.priority || node_signaled(node)) + if (prio <= i915_sched_attr_priority(&node->attr) || + node_signaled(node)) continue; GEM_BUG_ON(node_to_request(node)->engine->sched_engine != @@ -257,7 +260,7 @@ static void __i915_schedule(struct i915_sched_node *node, if (sched_engine->bump_inflight_request_prio) sched_engine->bump_inflight_request_prio(from, attr); - WRITE_ONCE(node->attr.priority, prio); + WRITE_ONCE(node->attr, *attr); /* * Once the request is ready, it will be placed into the @@ -305,6 +308,7 @@ void i915_sched_node_init(struct i915_sched_node *node) void i915_sched_node_reinit(struct i915_sched_node *node) { node->attr.priority = I915_PRIORITY_INVALID; + node->attr.nice = 0; node->semaphores = 0; node->flags = 0; diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 0b9b86af6c7f..75ccc9f55d14 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -38,6 +38,20 @@ void i915_sched_node_fini(struct i915_sched_node *node); void i915_schedule(struct i915_request *request, const struct i915_sched_attr *attr); +static inline int i915_sched_attr_priority(const struct i915_sched_attr *attr) +{ + int prio = attr->priority; + + /* + * Only allow I915_CONTEXT_DEFAULT_PRIORITY to be affected by the + * nice setting. + */ + if (!prio) + prio = -attr->nice; + + return prio; +} + struct list_head * i915_sched_lookup_priolist(struct i915_sched_engine *sched_engine, int prio); diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h index 24b9ac1c2ce2..159237aa7609 100644 --- a/drivers/gpu/drm/i915/i915_scheduler_types.h +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h @@ -29,6 +29,14 @@ struct i915_sched_attr { * The &drm_i915_private.kernel_context is assigned the lowest priority. */ int priority; + + /** + * @nice: context nice level + * + * Nice level follows the CPU scheduler nice value as set for the + * process owning the GPU context. + */ + int nice; }; /* From patchwork Tue Apr 5 14:53:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12801696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89741C433FE for ; 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a="241353412" X-IronPort-AV: E=Sophos;i="5.90,236,1643702400"; d="scan'208";a="241353412" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2022 07:54:19 -0700 X-IronPort-AV: E=Sophos;i="5.90,236,1643702400"; d="scan'208";a="608470346" Received: from pmulcahy-mobl.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.235.32]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2022 07:54:18 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Subject: [PATCH 3/3] drm/i915: Inherit submitter nice when scheduling requests Date: Tue, 5 Apr 2022 15:53:45 +0100 Message-Id: <20220405145345.3284084-4-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220405145345.3284084-1-tvrtko.ursulin@linux.intel.com> References: <20220405145345.3284084-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Tvrtko Ursulin Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tvrtko Ursulin Inherit submitter nice at point of request submission to account for long running processes getting either externally or self re-niced. Nice value will only apply to requests which originate from user contexts and have default context priority. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_request.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 960bfd517ff7..a777f14e4b87 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1811,8 +1811,11 @@ void i915_request_add(struct i915_request *rq) /* XXX placeholder for selftests */ rcu_read_lock(); ctx = rcu_dereference(rq->context->gem_context); - if (ctx) + if (ctx) { attr = ctx->sched; + if (attr.priority == I915_CONTEXT_DEFAULT_PRIORITY) + attr.nice = task_nice(current); + } rcu_read_unlock(); __i915_request_queue(rq, &attr);