From patchwork Tue Apr 5 16:08:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12801759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 380BFC433FE for ; Tue, 5 Apr 2022 16:08:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 19EE1C385AA; Tue, 5 Apr 2022 16:08:49 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 01C40C385A8; Tue, 5 Apr 2022 16:08:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 01C40C385A8 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 20F2222248; Tue, 5 Apr 2022 18:08:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649174924; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3odAN6Em2/FjwJHL8RWzQ78BiwMrPTpdrGtZRc272oI=; b=Gc01Cfv9kOW/4lv4YeNgO9lxwBiYOy6PIR7zmY9AfRMYj5FIRpXUASQxRQ+vvcyameRuWm v9UltLyG7MCH0MSfen1fmgTS/iJHlKiXKgaSQrtUNazMyDUH7glQus/ExvSlGR9xppaf3i htwq6MrpA+nUDCwPIc70udu+HrRIUq8= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Michael Walle Subject: [PATCH v3 1/7] ARM: dts: lan966x: swap dma channels for crypto node Date: Tue, 5 Apr 2022 18:08:31 +0200 Message-Id: <20220405160837.4093563-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405160837.4093563-1-michael@walle.cc> References: <20220405160837.4093563-1-michael@walle.cc> MIME-Version: 1.0 The YAML binding (crypto/atmel,at91sam9g46-aes.yaml) mandates the order of the channels. Swap them to pass devicetree validation. Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291") Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/lan966x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 604a41269ebe..a99ffb4cfb8a 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -114,9 +114,9 @@ aes: crypto@e004c000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xe004c000 0x100>; interrupts = ; - dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, - <&dma0 AT91_XDMAC_DT_PERID(12)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "aes_clk"; }; From patchwork Tue Apr 5 16:08:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12801760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87EA4C4332F for ; Tue, 5 Apr 2022 16:08:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 6ED9FC385A7; Tue, 5 Apr 2022 16:08:50 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id CED60C385A0; Tue, 5 Apr 2022 16:08:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org CED60C385A0 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 7EC402224D; Tue, 5 Apr 2022 18:08:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649174926; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vCEvTZ/O30k3nO+2jrdVl0gFAUtDTetFzbLFbAwJZ9U=; b=Il/jXmECXZEwfX9+DjKuh+tIOw5DxeqKj6wLyYM++VANeZ+7XGRt09Zn1lvJlEoa5xjSof dtfHPZqCtlL9Q744O1sqpVg+hOuU/NcqgApHYYiyScVG7yu2LA4SAdsbGqJMP7bKnrWuy4 iFmZL/vU+agNMZQArdjEMbSCYDYg29E= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Michael Walle Subject: [PATCH v3 2/7] ARM: dts: lan966x: add sgpio node Date: Tue, 5 Apr 2022 18:08:32 +0200 Message-Id: <20220405160837.4093563-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405160837.4093563-1-michael@walle.cc> References: <20220405160837.4093563-1-michael@walle.cc> MIME-Version: 1.0 Add the device tree node for the SGPIO IP block reused from the SparX-5. Keep the node disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/lan966x.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index a99ffb4cfb8a..4c7beebbd1ef 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -223,6 +223,32 @@ gpio: pinctrl@e2004064 { #interrupt-cells = <2>; }; + sgpio: gpio@e2004190 { + compatible = "microchip,sparx5-sgpio"; + reg = <0xe2004190 0x118>; + clocks = <&sys_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgpio_in: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sgpio_out: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + }; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; From patchwork Tue Apr 5 16:08:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12801761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2BDFC433EF for ; Tue, 5 Apr 2022 16:08:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id B1C63C385A4; Tue, 5 Apr 2022 16:08:52 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id C6DE6C385A0; Tue, 5 Apr 2022 16:08:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org C6DE6C385A0 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 262BB2224F; Tue, 5 Apr 2022 18:08:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649174927; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iTjJ/DlqGlB4KU5V2+oNHmLmbkHl/GSxV7xd7CiwzNc=; b=RgJsiwfILuKJCsY8+3oJcObhGC2VBqBDyUB6M8+CfWkJQgWGbuJvyW5qd+dDnKbq660TMy Ekr/aod0aiZfAEG2qnPNnBEkz89LGT0L6lu4wyNVEeZ4Lh5mun/LB7lIJN4Y5Z82oQ9PmH hDperpebx6swNwQ3e1wfw8DIpe+5mZA= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Michael Walle Subject: [PATCH v3 3/7] ARM: dts: lan966x: add missing uart DMA channel Date: Tue, 5 Apr 2022 18:08:33 +0200 Message-Id: <20220405160837.4093563-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405160837.4093563-1-michael@walle.cc> References: <20220405160837.4093563-1-michael@walle.cc> MIME-Version: 1.0 The usart node of the flexcom3 block is missing the DMA channels. Add it. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/lan966x.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 4c7beebbd1ef..e9d6c16d04cf 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -144,6 +144,9 @@ usart3: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; clocks = <&nic_clk>; clock-names = "usart"; atmel,fifo-size = <32>; From patchwork Tue Apr 5 16:08:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12801763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 347FFC4332F for ; Tue, 5 Apr 2022 16:08:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 195D8C385A9; Tue, 5 Apr 2022 16:08:54 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 18662C385A0; Tue, 5 Apr 2022 16:08:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 18662C385A0 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 85B5422255; Tue, 5 Apr 2022 18:08:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649174929; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yOxddNobkG29CG4y5YoXQEAGgvfg9n1rTfCuIDFre0A=; b=cZzpRljaNUvDJAkqSLGiEmVvdluyyTyNu0gChI6jqsE3XcgxAXjbhf1opHhFNeisVVYRu7 RIOdf5WvHvJb2UQ+qnPVNgi98dmJnu2teE+HeBvrl3pKZ06KQZRswxe9dhGyTOVoan6JUU Lj5evrmR0hUhB2gk/7w6YTIj/y0KcJ0= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Michael Walle Subject: [PATCH v3 4/7] ARM: dts: lan966x: add all flexcom usart nodes Date: Tue, 5 Apr 2022 18:08:34 +0200 Message-Id: <20220405160837.4093563-5-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405160837.4093563-1-michael@walle.cc> References: <20220405160837.4093563-1-michael@walle.cc> MIME-Version: 1.0 Add all the remaining usart nodes for the flexcom block. Although the DMA channels are specified, DMA is not enabled by default because break detection doesn't work with DMA. Keep the nodes disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/lan966x.dtsi | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index e9d6c16d04cf..ae3ac08cfc3b 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -92,6 +92,19 @@ flx0: flexcom@e0040000 { #size-cells = <1>; ranges = <0x0 0xe0040000 0x800>; status = "disabled"; + + usart0: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -102,6 +115,19 @@ flx1: flexcom@e0044000 { #size-cells = <1>; ranges = <0x0 0xe0044000 0x800>; status = "disabled"; + + usart1: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -129,6 +155,19 @@ flx2: flexcom@e0060000 { #size-cells = <1>; ranges = <0x0 0xe0060000 0x800>; status = "disabled"; + + usart2: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -181,6 +220,19 @@ flx4: flexcom@e0070000 { #size-cells = <1>; ranges = <0x0 0xe0070000 0x800>; status = "disabled"; + + usart4: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; timer0: timer@e008c000 { From patchwork Tue Apr 5 16:08:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12801762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F4CDC433F5 for ; Tue, 5 Apr 2022 16:08:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 5CDA5C385A5; Tue, 5 Apr 2022 16:08:53 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 20C2EC385A7; Tue, 5 Apr 2022 16:08:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 20C2EC385A7 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 3AB2A22258; Tue, 5 Apr 2022 18:08:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649174930; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VmrF2s9a0zsVi05pMwxqMdgIb42SRoi4+ICmOQzDKGA=; b=aAdNkAzy+Gx9uqzAVUf/+VVLk24DHTm52lb+2xqkypsjx6wUYCLVzYb69BWyhTXOnv+sRf jwiV8Bk1D3kGB/py8GK+w0Uo9JAW1diZZo+i8UmQktiEZFidhOxjJ1aj4DYhBxk9m2tbUB MIWP099YobK4+0dkbWplTKvW9Z39oFw= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Michael Walle Subject: [PATCH v3 5/7] ARM: dts: lan966x: add flexcom SPI nodes Date: Tue, 5 Apr 2022 18:08:35 +0200 Message-Id: <20220405160837.4093563-6-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405160837.4093563-1-michael@walle.cc> References: <20220405160837.4093563-1-michael@walle.cc> MIME-Version: 1.0 Add all the SPI nodes for the flexcom IP block. Keep them disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/lan966x.dtsi | 75 ++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index ae3ac08cfc3b..a37f2e58a1c2 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -105,6 +105,21 @@ usart0: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi0: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -128,6 +143,21 @@ usart1: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi1: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -168,6 +198,21 @@ usart2: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -191,6 +236,21 @@ usart3: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; dma0: dma-controller@e0068000 { @@ -233,6 +293,21 @@ usart4: serial@200 { atmel,fifo-size = <32>; status = "disabled"; }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; timer0: timer@e008c000 { From patchwork Tue Apr 5 16:08:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12801764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BEB55C433FE for ; Tue, 5 Apr 2022 16:08:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 98874C385A1; Tue, 5 Apr 2022 16:08:53 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id AFD07C385A9; Tue, 5 Apr 2022 16:08:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org AFD07C385A9 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id A99672225B; Tue, 5 Apr 2022 18:08:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649174930; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0zWa7FnAehsT5VQr7sLCyyvpTKbFiugxFLtDfUCAJuI=; b=XunTJuQUxA29p74sdfOJKB1N2HvxSmZ0uPGck97xXobh1uOy3pi/IYKdu9N/gVf3ARji9B KsoYqS9YUv6tJqzpmpWWKIersCDxmIp+yuWq3lXHL8/bfeKbRKJ4cyUaUsklfF/rtYFdrC LEMI86uujTakJSp3WTJiDx4Y+cJaze4= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Michael Walle Subject: [PATCH v3 6/7] ARM: dts: lan966x: add flexcom I2C nodes Date: Tue, 5 Apr 2022 18:08:36 +0200 Message-Id: <20220405160837.4093563-7-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405160837.4093563-1-michael@walle.cc> References: <20220405160837.4093563-1-michael@walle.cc> MIME-Version: 1.0 Add all I2C nodes of the flexcom IP blocks. The driver supports FIFO, DMA or both combined. But the latter isn't working correctly. Thus, skip the fifo-size property for now. DMA is doing single byte reads in this case. Keep the nodes disabled by default. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index a37f2e58a1c2..342c8cee2b9a 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -120,6 +120,19 @@ spi0: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx1: flexcom@e0044000 { @@ -158,6 +171,19 @@ spi1: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>, + <&dma0 AT91_XDMAC_DT_PERID(4)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; trng: rng@e0048000 { @@ -213,6 +239,19 @@ spi2: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, + <&dma0 AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; flx3: flexcom@e0064000 { @@ -251,6 +290,19 @@ spi3: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>, + <&dma0 AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; dma0: dma-controller@e0068000 { @@ -308,6 +360,19 @@ spi4: spi@400 { #size-cells = <0>; status = "disabled"; }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>, + <&dma0 AT91_XDMAC_DT_PERID(10)>; + dma-names = "tx", "rx"; + clocks = <&nic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; timer0: timer@e008c000 { From patchwork Tue Apr 5 16:08:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 12801765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5D98C433EF for ; Tue, 5 Apr 2022 16:08:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 9F60DC385A4; Tue, 5 Apr 2022 16:08:54 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 517ADC385A8; Tue, 5 Apr 2022 16:08:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 517ADC385A8 Authentication-Results: smtp.kernel.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=walle.cc Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 31CE422260; Tue, 5 Apr 2022 18:08:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649174931; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2p3sjpS/Bg3o28UgK7piCHL/zRE/gDoVsSlTwfbWAqQ=; b=hMCfN8z+XOdJahCnW0raIQnxmiUTsWCzvdBExcEKDAWdGV9SsNa0GQ6pXixZKAW/h3fW5d kj1MS2BRgUJGDEZW4WOmVLXQGm9txK+i09wtdOT6D4zgrw77uGgppPHxW+9rXXWKPhD8Vn GUoS/bPfLvQfqyeLsvp7zUkgSBz/oNM= From: Michael Walle To: Kavyasree Kotagiri , Nicolas Ferre List-Id: Cc: Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Claudiu Beznea , Tudor.Ambarus@microchip.com, Michael Walle Subject: [PATCH v3 7/7] ARM: dts: lan966x: add basic Kontron KSwitch D10 support Date: Tue, 5 Apr 2022 18:08:37 +0200 Message-Id: <20220405160837.4093563-8-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405160837.4093563-1-michael@walle.cc> References: <20220405160837.4093563-1-michael@walle.cc> MIME-Version: 1.0 Add basic support for the Kontron KSwitch D10 MMT. It comes in two variants: "6G-2GS" which features 6 Gigabit copper ports and two SFP cages and "8G" which features 6 Gigbabit copper ports (where two are 2.5G capable). For now the following is supported and working: - Kernel console - SFP cages I2C bus and mux - SPI - SGPIO - Watchdog Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/Makefile | 4 +- ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 77 +++++++++++++++++++ .../lan966x-kontron-kswitch-d10-mmt-8g.dts | 13 ++++ .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 75 ++++++++++++++++++ 4 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..54beef7c1810 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -742,7 +742,9 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb dtb-$(CONFIG_SOC_LAN966) += \ - lan966x-pcb8291.dtb + lan966x-pcb8291.dtb \ + lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \ + lan966x-kontron-kswitch-d10-mmt-8g.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts new file mode 100644 index 000000000000..9cf0b791a355 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 6G-2GS"; + compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; + + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&sgpio_out 3 2 GPIO_ACTIVE_HIGH>, + <&sgpio_out 3 3 GPIO_ACTIVE_HIGH>; + i2c-parent = <&i2c4>; + + i2c4_0: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4_1: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c4_0>; + los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c4_1>; + los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <2500>; + tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c4: i2c@600 { + pinctrl-0 = <&fc4_b_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&gpio { + fc4_b_pins: fc4-b-i2c-pins { + /* SCL, SDA */ + pins = "GPIO_57", "GPIO_58"; + function = "fc4_b"; + }; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts new file mode 100644 index 000000000000..4b35f6c46e7f --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for the Kontron KSwitch D10 MMT 8G + */ + +/dts-v1/; +#include "lan966x-kontron-kswitch-d10-mmt.dtsi" + +/ { + model = "Kontron KSwitch D10 MMT 8G"; + compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921", + "microchip,lan9668", "microchip,lan966"; +}; diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi new file mode 100644 index 000000000000..4178fb0bd9c5 --- /dev/null +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common part of the device tree for the Kontron KSwitch D10 MMT + */ + +/dts-v1/; +#include "lan966x.dtsi" + +/ { + aliases { + serial0 = &usart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 56 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; + + usart0: serial@200 { + pinctrl-0 = <&usart0_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&gpio { + usart0_pins: usart0-pins { + /* RXD, TXD */ + pins = "GPIO_25", "GPIO_26"; + function = "fc0_b"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1 */ + pins = "GPIO_32", "GPIO_33", "GPIO_34"; + function = "sgpio_a"; + }; + + sgpio_b_pins: sgpio-b-pins { + /* LD */ + pins = "GPIO_64"; + function = "sgpio_b"; + }; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>; + pinctrl-names = "default"; + bus-frequency = <8000000>; + /* arbitrary range because all GPIOs are in software mode */ + microchip,sgpio-port-ranges = <0 11>; + status = "okay"; + + sgpio_in: gpio@0 { + ngpios = <128>; + }; + + sgpio_out: gpio@1 { + ngpios = <128>; + }; +}; + +&watchdog { + status = "okay"; +};