From patchwork Tue Apr 5 18:47:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12801905 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3C12C43219 for ; Tue, 5 Apr 2022 20:16:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237242AbiDEULs (ORCPT ); Tue, 5 Apr 2022 16:11:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573294AbiDESt0 (ORCPT ); Tue, 5 Apr 2022 14:49:26 -0400 X-Greylist: delayed 116333 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 05 Apr 2022 11:47:23 PDT Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [217.70.178.232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DECCEAF1E0; Tue, 5 Apr 2022 11:47:23 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id EE4CF200007; Tue, 5 Apr 2022 18:47:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649184441; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=H31g2lSzg7n7VxTobwZqrUHtLT3mR7JfXrSowetcS0w=; b=EQxDMFEwl4Uxy8D2SwWeQ8tAQ+2j2I/zKbmGibaOzOVWJoZmunWjeF3lcUcR8DeYJkhEvY abGqGR71XtqDseu8jLNaClkZZpO7sYWiO78kDpbCrS8+QboA2xSH91qLv5HdyFNhMwbUH9 pWuhCApaCc/SLHyplkTin48tYeGFe0powHkt/6UCZu8CabRQA1C5C56W3m/fco8oDb+XZR bRxW/LLJctxd4MRQWOai45lQVw5DyIMYzHftJAV6/9I0ufMBgw+///8Hy1cWBEGWnjevXb Invmw8YRhSNc35i5XHPgZUx0wrQ2HMhuDCUKxspmm599ZMXc5xVuX9T1W84tYQ== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni Cc: Rob Herring , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-rtc@vger.kernel.org, Miquel Raynal Subject: [PATCH 1/7] dt-bindings: rtc: rzn1: Describe the RZN1 RTC Date: Tue, 5 Apr 2022 20:47:10 +0200 Message-Id: <20220405184716.1578385-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220405184716.1578385-1-miquel.raynal@bootlin.com> References: <20220405184716.1578385-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add new binding file for this RTC. Signed-off-by: Miquel Raynal --- .../bindings/rtc/renesas,rzn1-rtc.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml new file mode 100644 index 000000000000..903f0cd361fa --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rzn1-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs Real-Time Clock DT bindings + +maintainers: + - Miquel Raynal + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a06g032-rtc + - const: renesas,rzn1-rtc + + reg: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + items: + - const: alarm + - const: timer + - const: pps + + clocks: + maxItems: 1 + + clock-names: + const: hclk + + start-year: true + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - start-year + +unevaluatedProperties: false + +examples: + - | + #include + #include + rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = , + , + ; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + start-year = <2000>; + }; From patchwork Tue Apr 5 18:47:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12801908 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCBF6C433EF for ; Tue, 5 Apr 2022 20:16:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239290AbiDEUMQ (ORCPT ); Tue, 5 Apr 2022 16:12:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573295AbiDESt0 (ORCPT ); Tue, 5 Apr 2022 14:49:26 -0400 Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [IPv6:2001:4b98:dc4:8::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4BFCAF1DD; Tue, 5 Apr 2022 11:47:25 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id CEBCB200006; Tue, 5 Apr 2022 18:47:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649184443; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0wCROVhxQkzi01xQZ7CtsJyXoDnqptRHhKKgXAf97I8=; b=nZgbol2lDFRyYnzqBtJaMKxRbItRYY9JnbB1a5Y+UcpARzJUkFKNDstOqUNCes3VX8N/2f c7Xn9vYwgvePaycby+DlY5IFtH6sCptZ0SL2r6cjsf+IFGpwVY+6ny3X0NqWYDjhQ0UMHG /3gywrTtSC/Ye3t1OQkQgIiH19PGwe9Li9hCeI530bBQbxme/WXNAZ6Cfk4AOC6fxf2xdG 3ntESKddPzvde6rL1rlZG9PL1Xe2zwoYk97tncuZ8A/7I8F4HLVDFSHgfZDtALzvulePyn c7/o1sy3kD7K9I7oLpiPdMQssy5xBY0/gFkks6b5dHF6tDMESJ4PVJRzwqJwgQ== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni Cc: Rob Herring , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-rtc@vger.kernel.org, Miquel Raynal Subject: [PATCH 2/7] soc: renesas: rzn1-sysc: Export a function to enable/disable the RTC Date: Tue, 5 Apr 2022 20:47:11 +0200 Message-Id: <20220405184716.1578385-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220405184716.1578385-1-miquel.raynal@bootlin.com> References: <20220405184716.1578385-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org There are two RTC registers located within the system controller. Like with the dmamux register, let's add a new helper to enable/disable the power, reset and clock of the RTC. Signed-off-by: Miquel Raynal --- drivers/clk/renesas/r9a06g032-clocks.c | 49 +++++++++++++++++++ include/linux/soc/renesas/r9a06g032-sysctrl.h | 2 + 2 files changed, 51 insertions(+) diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 1df56d7ab3e1..7e61db39a43b 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -26,6 +26,13 @@ #include #define R9A06G032_SYSCTRL_DMAMUX 0xA0 +#define R9A06G032_SYSCTRL_PWRCTRL_RTC 0x140 +#define R9A06G032_SYSCTRL_PWRCTRL_RTC_CLKEN BIT(0) +#define R9A06G032_SYSCTRL_PWRCTRL_RTC_RST BIT(1) +#define R9A06G032_SYSCTRL_PWRCTRL_RTC_IDLE_REQ BIT(2) +#define R9A06G032_SYSCTRL_PWRCTRL_RTC_RSTN_FW BIT(3) +#define R9A06G032_SYSCTRL_PWRSTAT_RTC 0x144 +#define R9A06G032_SYSCTRL_PWRSTAT_RTC_IDLE BIT(1) struct r9a06g032_gate { u16 gate, reset, ready, midle, @@ -343,6 +350,48 @@ int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) } EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); +/* Exported helper to enable/disable the RTC */ +int r9a06g032_sysctrl_enable_rtc(bool enable) +{ + unsigned long flags; + u32 val; + + if (!sysctrl_priv) + return -EPROBE_DEFER; + + spin_lock_irqsave(&sysctrl_priv->lock, flags); + + if (enable) { + val = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val &= ~R9A06G032_SYSCTRL_PWRCTRL_RTC_RST; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val |= R9A06G032_SYSCTRL_PWRCTRL_RTC_CLKEN; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val |= R9A06G032_SYSCTRL_PWRCTRL_RTC_RSTN_FW; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val &= ~R9A06G032_SYSCTRL_PWRCTRL_RTC_IDLE_REQ; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRSTAT_RTC); + if (val & R9A06G032_SYSCTRL_PWRSTAT_RTC_IDLE) + return -EIO; + } else { + val = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val |= R9A06G032_SYSCTRL_PWRCTRL_RTC_IDLE_REQ; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val &= ~R9A06G032_SYSCTRL_PWRCTRL_RTC_RSTN_FW; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val &= ~R9A06G032_SYSCTRL_PWRCTRL_RTC_CLKEN; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + val |= R9A06G032_SYSCTRL_PWRCTRL_RTC_RST; + writel(val, sysctrl_priv->reg + R9A06G032_SYSCTRL_PWRCTRL_RTC); + } + + spin_unlock_irqrestore(&sysctrl_priv->lock, flags); + + return 0; +} +EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_enable_rtc); + /* register/bit pairs are encoded as an uint16_t */ static void clk_rdesc_set(struct r9a06g032_priv *clocks, diff --git a/include/linux/soc/renesas/r9a06g032-sysctrl.h b/include/linux/soc/renesas/r9a06g032-sysctrl.h index 066dfb15cbdd..914c8789149c 100644 --- a/include/linux/soc/renesas/r9a06g032-sysctrl.h +++ b/include/linux/soc/renesas/r9a06g032-sysctrl.h @@ -4,8 +4,10 @@ #ifdef CONFIG_CLK_R9A06G032 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val); +int r9a06g032_sysctrl_enable_rtc(bool enable); #else static inline int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) { return -ENODEV; } +static inline int r9a06g032_sysctrl_enable_rtc(bool enable) { return -ENODEV; } #endif #endif /* __LINUX_SOC_RENESAS_R9A06G032_SYSCTRL_H__ */ From patchwork Tue Apr 5 18:47:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12801907 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F32FBC43217 for ; Tue, 5 Apr 2022 20:16:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238497AbiDEULv (ORCPT ); Tue, 5 Apr 2022 16:11:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573297AbiDESt1 (ORCPT ); Tue, 5 Apr 2022 14:49:27 -0400 Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [217.70.178.232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC42DAF1F5; Tue, 5 Apr 2022 11:47:27 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id D200820000A; Tue, 5 Apr 2022 18:47:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649184446; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TWMoZhDjM/+WmkcVl9lPWw2Y2HJMKjePrD8Lfn6Z1QQ=; b=kmSfnDSfdqUn/u+Kpd+TfbT8Z8fFve2Ctng/hk9Ov6nCnETgIrllvUfCB2Xsq8LakTCb63 iK5V8e8qafuPdqRRljKLaftMgvsgxJ3Bdmfw0pFLXXQmidMOwDdtdILeeuDx2Tt0ALiBzF G5JtYimeBkXHXXixO4alYrrVM6Dqo+7XLsq2hQ+XtMoIIgrM9acp0Zgsm/5/JaaX0ocwgn JVmQjzV2AJ7XGVVckdntYWRoVCG4NK8QWD1GotM1EIDxhDWj/nqyaHOYpD/AyYJgiejjIH QmXcD7Da4SXadwxCl2/Kc88K2qk6JXqB9EKhjVZDQATTZiUcB9watO1vPXRklw== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni Cc: Rob Herring , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-rtc@vger.kernel.org, Michel Pollet , Miquel Raynal Subject: [PATCH 3/7] rtc: rzn1: Add new RTC driver Date: Tue, 5 Apr 2022 20:47:12 +0200 Message-Id: <20220405184716.1578385-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220405184716.1578385-1-miquel.raynal@bootlin.com> References: <20220405184716.1578385-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Michel Pollet Add a basic RTC driver for the RZ/N1. Signed-off-by: Michel Pollet Co-developed-by: Miquel Raynal Signed-off-by: Miquel Raynal --- drivers/rtc/Kconfig | 7 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-rzn1.c | 255 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 263 insertions(+) create mode 100644 drivers/rtc/rtc-rzn1.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 41c65b4d2baf..f4d72c5b99ea 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1548,6 +1548,13 @@ config RTC_DRV_RS5C313 help If you say yes here you get support for the Ricoh RS5C313 RTC chips. +config RTC_DRV_RZN1 + tristate "Renesas RZN1 RTC" + depends on ARCH_RZN1 || COMPILE_TEST + depends on OF && HAS_IOMEM + help + If you say yes here you get support for the Renesas RZ/N1 RTC. + config RTC_DRV_GENERIC tristate "Generic RTC support" # Please consider writing a new RTC driver instead of using the generic diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2d827d8261d5..fb04467b652d 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -151,6 +151,7 @@ obj-$(CONFIG_RTC_DRV_RX6110) += rtc-rx6110.o obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o +obj-$(CONFIG_RTC_DRV_RZN1) += rtc-rzn1.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c new file mode 100644 index 000000000000..15c533333930 --- /dev/null +++ b/drivers/rtc/rtc-rzn1.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas RZN1 Real Time Clock interface for Linux + * + * Copyright: + * - 2014 Renesas Electronics Europe Limited + * - 2022 Schneider Electric + * + * Authors: + * - Michel Pollet , + * - Miquel Raynal + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RZN1_RTC_CTL0 0x00 +#define RZN1_RTC_CTL0_SLSB_SUBU 0 +#define RZN1_RTC_CTL0_SLSB_SCMP BIT(4) +#define RZN1_RTC_CTL0_AMPM BIT(5) +#define RZN1_RTC_CTL0_CE BIT(7) + +#define RZN1_RTC_CTL1 0x04 +#define RZN1_RTC_CTL1_ALME BIT(4) + +#define RZN1_RTC_CTL2 0x08 +#define RZN1_RTC_CTL2_WAIT BIT(0) +#define RZN1_RTC_CTL2_WST BIT(1) +#define RZN1_RTC_CTL2_WUST BIT(5) + +#define RZN1_RTC_SEC 0x14 +#define RZN1_RTC_MIN 0x18 +#define RZN1_RTC_HOUR 0x1c +#define RZN1_RTC_WEEK 0x20 +#define RZN1_RTC_DAY 0x24 +#define RZN1_RTC_MONTH 0x28 +#define RZN1_RTC_YEAR 0x2c + +#define RZN1_RTC_SUBU 0x38 +#define RZN1_RTC_SUBU_DEV BIT(7) +#define RZN1_RTC_SUBU_DECR BIT(6) + +#define RZN1_RTC_ALM 0x40 +#define RZN1_RTC_ALH 0x44 +#define RZN1_RTC_ALW 0x48 + +#define RZN1_RTC_SECC 0x4c +#define RZN1_RTC_MINC 0x50 +#define RZN1_RTC_HOURC 0x54 +#define RZN1_RTC_WEEKC 0x58 +#define RZN1_RTC_DAYC 0x5c +#define RZN1_RTC_MONTHC 0x60 +#define RZN1_RTC_YEARC 0x64 + +struct rzn1_rtc { + struct rtc_device *rtcdev; + void __iomem *base; + struct clk *clk; +}; + +static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm) +{ + tm->tm_sec = readl(rtc->base + RZN1_RTC_SECC); + tm->tm_min = readl(rtc->base + RZN1_RTC_MINC); + tm->tm_hour = readl(rtc->base + RZN1_RTC_HOURC); + tm->tm_wday = readl(rtc->base + RZN1_RTC_WEEKC); + tm->tm_mday = readl(rtc->base + RZN1_RTC_DAYC); + tm->tm_mon = readl(rtc->base + RZN1_RTC_MONTHC); + tm->tm_year = readl(rtc->base + RZN1_RTC_YEARC); +} + +static unsigned int rzn1_rtc_tm_to_wday(struct rtc_time *tm) +{ + time64_t time; + unsigned int days; + u32 secs; + + time = rtc_tm_to_time64(tm); + days = div_s64_rem(time, 86400, &secs); + + /* day of the week, 1970-01-01 was a Thursday */ + return (days + 4) % 7; +} + +static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + u32 secs; + + rzn1_rtc_get_time_snapshot(rtc, tm); + secs = readl(rtc->base + RZN1_RTC_SECC); + if (tm->tm_sec != secs) + rzn1_rtc_get_time_snapshot(rtc, tm); + + tm->tm_sec = bcd2bin(tm->tm_sec); + tm->tm_min = bcd2bin(tm->tm_min); + tm->tm_hour = bcd2bin(tm->tm_hour); + tm->tm_wday = bcd2bin(tm->tm_wday); + tm->tm_mday = bcd2bin(tm->tm_mday); + tm->tm_mon = bcd2bin(tm->tm_mon); + tm->tm_year = bcd2bin(tm->tm_year); + + dev_dbg(dev, "%d-%d-%d(%d)T%d:%d:%d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + return 0; +} + +static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + u32 val; + int ret; + + tm->tm_sec = bin2bcd(tm->tm_sec); + tm->tm_min = bin2bcd(tm->tm_min); + tm->tm_hour = bin2bcd(tm->tm_hour); + tm->tm_wday = bin2bcd(rzn1_rtc_tm_to_wday(tm)); + tm->tm_mday = bin2bcd(tm->tm_mday); + tm->tm_mon = bin2bcd(tm->tm_mon); + tm->tm_year = bin2bcd(tm->tm_year); + + /* Hold the counter */ + val = readl(rtc->base + RZN1_RTC_CTL2); + val |= RZN1_RTC_CTL2_WAIT; + writel(val, rtc->base + RZN1_RTC_CTL2); + + /* Wait for the counter to stop: two 32k clock cycles */ + usleep_range(61, 100); + ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val, + val & RZN1_RTC_CTL2_WST, 0, 100); + if (!ret) { + writel(tm->tm_sec, rtc->base + RZN1_RTC_SEC); + writel(tm->tm_min, rtc->base + RZN1_RTC_MIN); + writel(tm->tm_hour, rtc->base + RZN1_RTC_HOUR); + writel(tm->tm_wday, rtc->base + RZN1_RTC_WEEK); + writel(tm->tm_mday, rtc->base + RZN1_RTC_DAY); + writel(tm->tm_mon, rtc->base + RZN1_RTC_MONTH); + writel(tm->tm_year, rtc->base + RZN1_RTC_YEAR); + } + + /* Release the counter back */ + val &= ~RZN1_RTC_CTL2_WAIT; + writel(val, rtc->base + RZN1_RTC_CTL2); + + return ret; +} + +static const struct rtc_class_ops rzn1_rtc_ops = { + .read_time = rzn1_rtc_read_time, + .set_time = rzn1_rtc_set_time, +}; + +static int rzn1_rtc_probe(struct platform_device *pdev) +{ + struct rzn1_rtc *rtc; + int ret; + + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + platform_set_drvdata(pdev, rtc); + + rtc->clk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(rtc->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->clk), "Missing hclk\n"); + + rtc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rtc->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n"); + + rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtcdev)) + return PTR_ERR(rtc); + + rtc->rtcdev->range_max = 3178591199UL; /* 100 years */ + rtc->rtcdev->ops = &rzn1_rtc_ops; + + ret = r9a06g032_sysctrl_enable_rtc(true); + if (ret) + return ret; + + ret = clk_prepare_enable(rtc->clk); + if (ret) + goto disable_rtc; + + /* + * Ensure the clock counter is enabled. + * Set 24-hour mode and possible oscillator offset compensation in SUBU mode. + */ + writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU, + rtc->base + RZN1_RTC_CTL0); + + /* Disable all interrupts */ + writel(0, rtc->base + RZN1_RTC_CTL1); + + /* Enable counter operation */ + writel(0, rtc->base + RZN1_RTC_CTL2); + + ret = devm_rtc_register_device(rtc->rtcdev); + if (ret) { + dev_err(&pdev->dev, "Failed to register RTC\n"); + goto disable_clk; + } + + return 0; + +disable_clk: + clk_disable_unprepare(rtc->clk); +disable_rtc: + r9a06g032_sysctrl_enable_rtc(false); + + return ret; +} + +static int rzn1_rtc_remove(struct platform_device *pdev) +{ + struct rzn1_rtc *rtc = platform_get_drvdata(pdev); + + clk_disable_unprepare(rtc->clk); + r9a06g032_sysctrl_enable_rtc(false); + + return 0; +} + +static const struct of_device_id rzn1_rtc_of_match[] = { + { .compatible = "renesas,rzn1-rtc" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rzn1_rtc_of_match); + +static struct platform_driver rzn1_rtc_driver = { + .probe = rzn1_rtc_probe, + .remove = rzn1_rtc_remove, + .driver = { + .name = "rzn1-rtc", + .owner = THIS_MODULE, + .of_match_table = rzn1_rtc_of_match, + }, +}; +module_platform_driver(rzn1_rtc_driver); + +MODULE_AUTHOR("Michel Pollet X-Patchwork-Id: 12801910 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E745BC433F5 for ; Tue, 5 Apr 2022 20:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240095AbiDEUMd (ORCPT ); Tue, 5 Apr 2022 16:12:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573299AbiDESta (ORCPT ); Tue, 5 Apr 2022 14:49:30 -0400 Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [IPv6:2001:4b98:dc4:8::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAFC1AF1E0; Tue, 5 Apr 2022 11:47:29 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 8647F20000B; Tue, 5 Apr 2022 18:47:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649184448; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=H8tLfC+MynAaFO+mev5ezH5oTeB1BvcIj8rvqhct6iM=; b=ErDyOXfHK2ru67T6pT5LPPq/vggqKQPYGjV4yIiDG9xgEKVwAYEmVS91vIG1Trgb3yZHMS xubP8707x/4lMyExERUIW4alJRr/BpFU2ZLWMB6X0REd3qZvcwlNMD4ipDncebUHPpUO2z XFCbHA361kjQLiYPr3rzXPiJ0UQmQLtyTppgEzhjHSnkDdb3bf9aPjBttr7Nhd1pcCuPyk KKiGlH5vVjGoQo3PFdA72EuWd8c8OK4AUS0/BqdY9ZrDCAah8VMEc2+UBBta2bm09+to7O qpIo6001z3vpw7I+kHdfN0kpB3jWOdtZVBAQiAqYRFjA2mCdKzGs1oNTa1p7gQ== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni Cc: Rob Herring , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-rtc@vger.kernel.org, Miquel Raynal Subject: [PATCH 4/7] rtc: rzn1: Add alarm support Date: Tue, 5 Apr 2022 20:47:13 +0200 Message-Id: <20220405184716.1578385-5-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220405184716.1578385-1-miquel.raynal@bootlin.com> References: <20220405184716.1578385-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The RZN1 RTC can trigger an interrupt when reaching a particular date up to 7 days ahead. Bring support for this alarm. One drawback though, the granularity is about a minute. Signed-off-by: Miquel Raynal --- drivers/rtc/rtc-rzn1.c | 108 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c index 15c533333930..85c5a68944a0 100644 --- a/drivers/rtc/rtc-rzn1.c +++ b/drivers/rtc/rtc-rzn1.c @@ -154,14 +154,110 @@ static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm) return ret; } +static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id) +{ + struct rzn1_rtc *rtc = dev_id; + + rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF); + + return IRQ_HANDLED; +} + +static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + u32 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); + + if (enable) + ctl1 |= RZN1_RTC_CTL1_ALME; + else + ctl1 &= ~RZN1_RTC_CTL1_ALME; + + writel(ctl1, rtc->base + RZN1_RTC_CTL1); + + return 0; +} + +static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + struct rtc_time *tm = &alrm->time; + unsigned int min, hour, wday, delta_days; + u32 ctl1; + int ret; + + ret = rzn1_rtc_read_time(dev, tm); + if (ret) + return ret; + + min = readl(rtc->base + RZN1_RTC_ALM); + hour = readl(rtc->base + RZN1_RTC_ALH); + wday = readl(rtc->base + RZN1_RTC_ALW); + + tm->tm_sec = 0; + tm->tm_min = bcd2bin(min); + tm->tm_hour = bcd2bin(hour); + delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7; + tm->tm_wday = fls(wday) - 1; + tm->tm_mday += delta_days; + if (delta_days > rtc_month_days(tm->tm_mon, tm->tm_year)) { + tm->tm_mday %= rtc_month_days(tm->tm_mon, tm->tm_year); + tm->tm_mon++; + } + if (tm->tm_mon > 12) { + tm->tm_mon %= 12; + tm->tm_year++; + } + + ctl1 = readl(rtc->base + RZN1_RTC_CTL1); + alrm->enabled = !!(ctl1 & RZN1_RTC_CTL1_ALME); + + return 0; +} + +static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + struct rtc_time *tm = &alrm->time, tm_now; + unsigned long alarm, farest; + unsigned int days_ahead, wday; + int ret; + + ret = rzn1_rtc_read_time(dev, &tm_now); + if (ret) + return ret; + + /* We cannot set alarms more than one week ahead */ + farest = rtc_tm_to_time64(&tm_now) + (7 * 86400); + alarm = rtc_tm_to_time64(tm); + if (time_after(alarm, farest)) + return -EOPNOTSUPP; + + /* Convert alarm day into week day */ + days_ahead = tm->tm_mday - tm_now.tm_mday; + wday = (tm_now.tm_wday + days_ahead) % 7; + + writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM); + writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH); + writel(BIT(wday), rtc->base + RZN1_RTC_ALW); + + rzn1_rtc_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + static const struct rtc_class_ops rzn1_rtc_ops = { .read_time = rzn1_rtc_read_time, .set_time = rzn1_rtc_set_time, + .read_alarm = rzn1_rtc_read_alarm, + .set_alarm = rzn1_rtc_set_alarm, + .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, }; static int rzn1_rtc_probe(struct platform_device *pdev) { struct rzn1_rtc *rtc; + int alarm_irq; int ret; rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); @@ -178,12 +274,17 @@ static int rzn1_rtc_probe(struct platform_device *pdev) if (IS_ERR(rtc->base)) return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n"); + alarm_irq = platform_get_irq(pdev, 0); + if (alarm_irq < 0) + return dev_err_probe(&pdev->dev, alarm_irq, "Missing timer IRQ\n"); + rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev); if (IS_ERR(rtc->rtcdev)) return PTR_ERR(rtc); rtc->rtcdev->range_max = 3178591199UL; /* 100 years */ rtc->rtcdev->ops = &rzn1_rtc_ops; + set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features); ret = r9a06g032_sysctrl_enable_rtc(true); if (ret) @@ -206,6 +307,13 @@ static int rzn1_rtc_probe(struct platform_device *pdev) /* Enable counter operation */ writel(0, rtc->base + RZN1_RTC_CTL2); + ret = devm_request_irq(&pdev->dev, alarm_irq, rzn1_rtc_alarm_irq, 0, + dev_name(&pdev->dev), rtc); + if (ret) { + dev_err(&pdev->dev, "RTC timer interrupt not available\n"); + goto disable_clk; + } + ret = devm_rtc_register_device(rtc->rtcdev); if (ret) { dev_err(&pdev->dev, "Failed to register RTC\n"); From patchwork Tue Apr 5 18:47:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12801911 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D62AFC4332F for ; Tue, 5 Apr 2022 20:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240397AbiDEUMf (ORCPT ); Tue, 5 Apr 2022 16:12:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573300AbiDEStb (ORCPT ); Tue, 5 Apr 2022 14:49:31 -0400 Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [217.70.178.232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BED27AF1F0; Tue, 5 Apr 2022 11:47:31 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 850E1200004; Tue, 5 Apr 2022 18:47:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649184450; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HU1wc5MsgG96qTLzOLNsJmhZ3anFEAxSiwSuwGVQASk=; b=oGRU0W1seWtDq+NuHL5v458Z8ppx4eB/GvwGMk94NwbLYPLTa+oQV3iXVRI1CtwSKT2s32 XMm89XB/msM2DghJkfJYN1ge8GgQB6YdO8smFdVqya8rd0Yp0tiLgz9Pvn+HlF058B3zF2 mVinZFnos1y3nMQwEvxgvhZBIb8nm3LQM0mAmGcs/5kPeEDZXNSJwJttqYB504XM3Eu6M3 Nn+4EW4t3BsWnFXH4F3K5Ui+k2KesIBNJcYImUSPKLgtkQ0w6A+U50asPIsctoSoxhpkkQ mHWw/VsB1hImdExNqjjXhb06KMyMSy/RwIWzsxzbxOwndxo34mr6AosZoNORCw== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni Cc: Rob Herring , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-rtc@vger.kernel.org, Miquel Raynal Subject: [PATCH 5/7] rtc: rzn1: Add oscillator offset support Date: Tue, 5 Apr 2022 20:47:14 +0200 Message-Id: <20220405184716.1578385-6-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220405184716.1578385-1-miquel.raynal@bootlin.com> References: <20220405184716.1578385-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The RZN1 RTC can compensate the imprecision of the oscillator up to approximately 190ppm. Seconds can last slightly shorter or longer depending on the configuration. Below ~65ppm of correction, we can change the time spent in a second every minute, which is the most accurate compensation that the RTC can offer. Above, the compensation will be active every 20s. Signed-off-by: Miquel Raynal --- drivers/rtc/rtc-rzn1.c | 73 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c index 85c5a68944a0..64eb1ff20a24 100644 --- a/drivers/rtc/rtc-rzn1.c +++ b/drivers/rtc/rtc-rzn1.c @@ -246,12 +246,85 @@ static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) return 0; } +static int rzn1_rtc_read_offset(struct device *dev, long *offset) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + unsigned int ppb_per_step; + bool subtract; + u32 val; + + val = readl(rtc->base + RZN1_RTC_SUBU); + ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051; + subtract = val & RZN1_RTC_SUBU_DECR; + val &= 0x3F; + + if (!val) + *offset = 0; + else if (subtract) + *offset = -(((~val) & 0x3F) + 1) * ppb_per_step; + else + *offset = (val - 1) * ppb_per_step; + + return 0; +} + +static int rzn1_rtc_set_offset(struct device *dev, long offset) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + unsigned int steps, ppb_per_step; + int stepsh, stepsl; + u32 val; + int ret; + + /* + * Check which resolution mode (every 20 or 60s) can be used. + * Between 2 and 124 clock pulses can be added or substracted. + * + * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is + * close to 3051 ppb. In 60s mode, the resolution is closer to 1017. + */ + stepsh = DIV_ROUND_CLOSEST(offset, 1017); + stepsl = DIV_ROUND_CLOSEST(offset, 3051); + + if (stepsh >= -0x3E && stepsh <= 0x3E) { + ppb_per_step = 1017; + steps = stepsh; + val |= RZN1_RTC_SUBU_DEV; + } else if (stepsl >= -0x3E && stepsl <= 0x3E) { + ppb_per_step = 3051; + steps = stepsl; + } else { + return -ERANGE; + } + + if (!steps) + return 0; + + if (steps > 0) { + val |= steps + 1; + } else { + val |= RZN1_RTC_SUBU_DECR; + val |= (~(-steps - 1)) & 0x3F; + } + + ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val, + !(val & RZN1_RTC_CTL2_WUST), 100, 2000000); + if (ret) + return ret; + + writel(val, rtc->base + RZN1_RTC_SUBU); + + return 0; +} + static const struct rtc_class_ops rzn1_rtc_ops = { .read_time = rzn1_rtc_read_time, .set_time = rzn1_rtc_set_time, .read_alarm = rzn1_rtc_read_alarm, .set_alarm = rzn1_rtc_set_alarm, .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, + .read_offset = rzn1_rtc_read_offset, + .set_offset = rzn1_rtc_set_offset, }; static int rzn1_rtc_probe(struct platform_device *pdev) From patchwork Tue Apr 5 18:47:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12801912 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08294C43217 for ; Tue, 5 Apr 2022 20:17:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240845AbiDEUMk (ORCPT ); Tue, 5 Apr 2022 16:12:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573302AbiDESte (ORCPT ); Tue, 5 Apr 2022 14:49:34 -0400 Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [217.70.178.232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0AECAF1E0; Tue, 5 Apr 2022 11:47:33 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 88418200008; Tue, 5 Apr 2022 18:47:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649184452; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5VgkvEnP5b6St7Fp3o3CiWue0Qq0QtYCZ+H9lR4xV74=; b=EvtzmemGu+VW/O34YilZ5smr0nIJGAu9gZYrdqsRAzToOBgE5O/NtykvyGz8iW62mjbyeP Gf+p3cW+qxE9XVv7MasQidJQ5VJV80pjuiUNCJpOHiOT5msDV5pPAb8pD5zhDdyWOsXFDT viy5tfF48XQgDh+hc9z+BAdv3NkQaGxJpcVYOdVjNR9AcTphoHQmBcvJNjViX9j3McLUSa 56ZxjXFzwBq8hQUHBMrL1PlIkCb7buze6Ec1sPTk+kn09xlI+IzchQSAqvm7JOihXtcRgB CaUEVMA3tB5r/nAVKMzsjEBuGJtPbroclRf8aPD1T2zNnMPJTW0XiA5jIyRM3g== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni Cc: Rob Herring , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-rtc@vger.kernel.org, Miquel Raynal Subject: [PATCH 6/7] MAINTAINERS: Add myself as maintainer of the RZN1 RTC driver Date: Tue, 5 Apr 2022 20:47:15 +0200 Message-Id: <20220405184716.1578385-7-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220405184716.1578385-1-miquel.raynal@bootlin.com> References: <20220405184716.1578385-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org After contributing it, I'll volunteer to maintain it. Signed-off-by: Miquel Raynal Acked-by: Geert Uytterhoeven --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 120d3ae57a4b..a2bafa05ca60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16849,6 +16849,14 @@ S: Supported F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml F: drivers/iio/adc/rzg2l_adc.c +RENESAS RZ/N1 RTC CONTROLLER DRIVER +M: Miquel Raynal +L: linux-rtc@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml +F: drivers/rtc/rtc-rzn1.c + RENESAS R-CAR GEN3 & RZ/N1 NAND CONTROLLER DRIVER M: Miquel Raynal L: linux-mtd@lists.infradead.org From patchwork Tue Apr 5 18:47:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12801906 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22D6BC433EF for ; Tue, 5 Apr 2022 20:16:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238592AbiDEULy (ORCPT ); Tue, 5 Apr 2022 16:11:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1573304AbiDESth (ORCPT ); Tue, 5 Apr 2022 14:49:37 -0400 Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [217.70.178.232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56E1AAF1F0; Tue, 5 Apr 2022 11:47:35 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 908BC200006; Tue, 5 Apr 2022 18:47:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1649184454; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Xxdt0tyZWd8zeGpcOomewbA36qGbMLLM+1tWmHX19c8=; b=NJFDnHyej9QXSnfYFN+Nd9Y6DySfU/M34GWjlzY/xKl5ohq8pspgXHHbCZ2VnRB6xm0mP6 pDB8+w8a6Ja8ftDsQQcTAX4Y9+9t2IGNZxprl72OGFuwe3M4bOKdFEM/s6tZd8DbozcxvY EsyPdSEv0o2UzQhmFBdP/4mG4nhq6ySpMYMKVAWwQSnErp7mYGxQk0LiLKh2ErQ6ww2iW1 qUY/zR8rzya5GfuKAfkTn1wx58+DOm5aToTNEIYkhdjngk8rTw2H8j6bsK7X2OtwYYdfom 8TsYmWS9rROGKzFBvJKQrrB0BHzA5i13oSCo21Hi6wWlyM6cLTwSOEg4P0xU6Q== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni Cc: Rob Herring , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Stephen Boyd , Michael Turquette , linux-clk@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , linux-rtc@vger.kernel.org, Miquel Raynal Subject: [PATCH 7/7] ARM: dts: r9a06g032: Describe the RTC Date: Tue, 5 Apr 2022 20:47:16 +0200 Message-Id: <20220405184716.1578385-8-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220405184716.1578385-1-miquel.raynal@bootlin.com> References: <20220405184716.1578385-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Describe the SoC RTC which counts time and provides alarm support. Signed-off-by: Miquel Raynal --- arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 4288b935fcea..7d380a38c7cd 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -103,6 +103,18 @@ dmamux: dma-router@a0 { }; }; + rtc0: rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = , + , + ; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + status = "disabled"; + }; + uart0: serial@40060000 { compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; reg = <0x40060000 0x400>;