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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2022 15:17:17.6962 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 234cff5e-0043-42a0-8cc6-08da17e089ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4149 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Timo Alho Current clock initialization causes intermediate registering of orphan clocks (i.e. a clock without a parent registered). CCF keeps track of orphan clocks and any time a new clock is registered, it will loop through the list of orphan and queries if the parent is now available. This operation triggers a clk operation(s), which is an IPC with BPMP-FW. Hence, due to the order of which the clock appear currently, this causes >5000 IPC messages to be sent to BPMP-FW during clock initialization. Optimize the clock probing by registering clocks hierarchically from root clock towards leafs. Signed-off-by: Timo Alho [ Checkpatch warnings fixed by Jon Hunter ] Signed-off-by: Jon Hunter --- drivers/clk/tegra/clk-bpmp.c | 72 ++++++++++++++++++++++++++++-------- 1 file changed, 56 insertions(+), 16 deletions(-) diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c index 6ecf18f71c32..bacaa468e114 100644 --- a/drivers/clk/tegra/clk-bpmp.c +++ b/drivers/clk/tegra/clk-bpmp.c @@ -448,15 +448,29 @@ static int tegra_bpmp_probe_clocks(struct tegra_bpmp *bpmp, return count; } +static unsigned int +tegra_bpmp_clk_id_to_index(const struct tegra_bpmp_clk_info *clocks, + unsigned int num_clocks, unsigned int id) +{ + unsigned int i; + + for (i = 0; i < num_clocks; i++) + if (clocks[i].id == id) + return i; + + return UINT_MAX; +} + static const struct tegra_bpmp_clk_info * tegra_bpmp_clk_find(const struct tegra_bpmp_clk_info *clocks, unsigned int num_clocks, unsigned int id) { unsigned int i; - for (i = 0; i < num_clocks; i++) - if (clocks[i].id == id) - return &clocks[i]; + i = tegra_bpmp_clk_id_to_index(clocks, num_clocks, id); + + if (i < num_clocks) + return &clocks[i]; return NULL; } @@ -539,31 +553,57 @@ tegra_bpmp_clk_register(struct tegra_bpmp *bpmp, return clk; } +static void tegra_bpmp_register_clocks_one(struct tegra_bpmp *bpmp, + struct tegra_bpmp_clk_info *infos, + unsigned int i, + unsigned int count) +{ + unsigned int j; + struct tegra_bpmp_clk_info *info; + struct tegra_bpmp_clk *clk; + + if (bpmp->clocks[i]) { + /* already registered */ + return; + } + + info = &infos[i]; + for (j = 0; j < info->num_parents; ++j) { + unsigned int p_id = info->parents[j]; + unsigned int p_i = tegra_bpmp_clk_id_to_index(infos, count, + p_id); + if (p_i < count) + tegra_bpmp_register_clocks_one(bpmp, infos, p_i, count); + } + + clk = tegra_bpmp_clk_register(bpmp, info, infos, count); + if (IS_ERR(clk)) { + dev_err(bpmp->dev, + "failed to register clock %u (%s): %ld\n", + info->id, info->name, PTR_ERR(clk)); + /* intentionally store the error pointer to + * bpmp->clocks[i] to avoid re-attempting the + * registration later + */ + } + + bpmp->clocks[i] = clk; +} + static int tegra_bpmp_register_clocks(struct tegra_bpmp *bpmp, struct tegra_bpmp_clk_info *infos, unsigned int count) { - struct tegra_bpmp_clk *clk; unsigned int i; bpmp->num_clocks = count; - bpmp->clocks = devm_kcalloc(bpmp->dev, count, sizeof(clk), GFP_KERNEL); + bpmp->clocks = devm_kcalloc(bpmp->dev, count, sizeof(struct tegra_bpmp_clk), GFP_KERNEL); if (!bpmp->clocks) return -ENOMEM; for (i = 0; i < count; i++) { - struct tegra_bpmp_clk_info *info = &infos[i]; - - clk = tegra_bpmp_clk_register(bpmp, info, infos, count); - if (IS_ERR(clk)) { - dev_err(bpmp->dev, - "failed to register clock %u (%s): %ld\n", - info->id, info->name, PTR_ERR(clk)); - continue; - } - - bpmp->clocks[i] = clk; + tegra_bpmp_register_clocks_one(bpmp, infos, i, count); } return 0; From patchwork Wed Apr 6 15:17:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 12803822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3BBDC433F5 for ; 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Wed, 6 Apr 2022 08:17:16 -0700 From: Jon Hunter To: Peter De Schrijver , Michael Turquette , Stephen Boyd , Thierry Reding CC: , , "Rajkumar Kasirajan" , Jon Hunter Subject: [PATCH 2/2] clk: tegra: replace round_rate with determine_rate Date: Wed, 6 Apr 2022 16:17:01 +0100 Message-ID: <20220406151701.262056-2-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220406151701.262056-1-jonathanh@nvidia.com> References: <20220406151701.262056-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a79d8e25-3ca5-466d-714d-08da17e08aea X-MS-TrafficTypeDiagnostic: DM4PR12MB5215:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ruPZPppnWF4J8mKbDeJb6cbEdIv1+0ghz4OVk8avHG2SC0I6hWj1rwPxVfSWSpmDhnqoXkG1sTVzbHkeK/XqQsdbAVS1NImBHgY9+daRpCulb9MVcNRM6LEURn2Buy8vTPKC9bY+a0eAJvAKvIVBaCua8oFoPv1ZCkG0QHqa80lBgIKF34XEsHGj5DYKxsfYlZ+cU76XpS27Tomkdc/xbsaIt93Ko2i9dCHta6ODQnoq2L2jLaCwoXTAkz83NWwRxKeROkav6hFh6iDXQIzdv0p/7LHYqN2xQg0lLJ9p+CEgsY0B95NhnmUQDQfk0JxHWfJrwRkdY7f4Zc0tsQ/hFCwmH1o/q/Sw4QnV9Mm1ca/Bthz2oLfzDfOqIoPVacFNITA+XZjtzWCOm6XGmj9Urv69eujpYeTpmeDFrgZidPqcQskgwohjQo6CNdQey5upPqv/NrVzJIuHlM/cfUfde9U2XShtQmWsDZBMTcyUs/9EuRU9ghzqBfgfGc7FTFTCxOpGQB/cr+Z7p3xVn3VkQEXFYuDxB+3wdkHInH/NtKaGcv7tD5TJyKoWrsqiMWgLWXomBXEwfJbMcxMAkyHlmmuSHUq1GHtaoPKWZm+0mzVtxSLqTSuKKwUS+ipsOTVG9guuS0obm/W8yzDIX3+yOrvg8Lb2bO/McHCFIlgYI+oA7N7Swz37n/Npn8AHar3moABYg46I+lFbnrprLwkv7g== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(4326008)(8676002)(70206006)(70586007)(316002)(54906003)(110136005)(36860700001)(36756003)(81166007)(86362001)(356005)(40460700003)(82310400005)(83380400001)(2616005)(1076003)(26005)(186003)(508600001)(6666004)(7696005)(8936002)(47076005)(336012)(426003)(2906002)(5660300002)(107886003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2022 15:17:19.5986 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a79d8e25-3ca5-466d-714d-08da17e08aea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5215 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Rajkumar Kasirajan Replace round_rate callback with determine_rate which can consider max_rate imposed by clk_set_max_rate while rounding clock rate. Note that if the determine_rate callback is defined it will be called instead of the round_rate callback when calling clk_round_rate(). By using determine_rate, the max rate returned when calling clk_round_rate() is now limited by the current max_rate. Signed-off-by: Rajkumar Kasirajan [ Checkpatch warning fixed and commit message updated by Jon Hunter ] Signed-off-by: Jon Hunter --- drivers/clk/tegra/clk-bpmp.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c index bacaa468e114..3748a39dae7c 100644 --- a/drivers/clk/tegra/clk-bpmp.c +++ b/drivers/clk/tegra/clk-bpmp.c @@ -164,15 +164,18 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw, return response.rate; } -static long tegra_bpmp_clk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int tegra_bpmp_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *rate_req) { struct tegra_bpmp_clk *clk = to_tegra_bpmp_clk(hw); struct cmd_clk_round_rate_response response; struct cmd_clk_round_rate_request request; struct tegra_bpmp_clk_message msg; + unsigned long rate; int err; + rate = min(max(rate_req->rate, rate_req->min_rate), rate_req->max_rate); + memset(&request, 0, sizeof(request)); request.rate = min_t(u64, rate, S64_MAX); @@ -188,7 +191,9 @@ static long tegra_bpmp_clk_round_rate(struct clk_hw *hw, unsigned long rate, if (err < 0) return err; - return response.rate; + rate_req->rate = (unsigned long)response.rate; + + return 0; } static int tegra_bpmp_clk_set_parent(struct clk_hw *hw, u8 index) @@ -290,7 +295,7 @@ static const struct clk_ops tegra_bpmp_clk_rate_ops = { .unprepare = tegra_bpmp_clk_unprepare, .is_prepared = tegra_bpmp_clk_is_prepared, .recalc_rate = tegra_bpmp_clk_recalc_rate, - .round_rate = tegra_bpmp_clk_round_rate, + .determine_rate = tegra_bpmp_clk_determine_rate, .set_rate = tegra_bpmp_clk_set_rate, }; @@ -299,7 +304,7 @@ static const struct clk_ops tegra_bpmp_clk_mux_rate_ops = { .unprepare = tegra_bpmp_clk_unprepare, .is_prepared = tegra_bpmp_clk_is_prepared, .recalc_rate = tegra_bpmp_clk_recalc_rate, - .round_rate = tegra_bpmp_clk_round_rate, + .determine_rate = tegra_bpmp_clk_determine_rate, .set_parent = tegra_bpmp_clk_set_parent, .get_parent = tegra_bpmp_clk_get_parent, .set_rate = tegra_bpmp_clk_set_rate,