From patchwork Fri Apr 8 08:00:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D2AC433F5 for ; Fri, 8 Apr 2022 07:58:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230061AbiDHIAZ (ORCPT ); Fri, 8 Apr 2022 04:00:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229870AbiDHIAX (ORCPT ); Fri, 8 Apr 2022 04:00:23 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4524A101F2D; Fri, 8 Apr 2022 00:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404700; x=1680940700; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1okvSdmZsloK4HJrpOO9mV8tLTBZw76e7Q+USvhaazI=; b=gGlATX5QhZaeJzry4fLdt04d7HRdNmRWrhxBntzHu4S2nSgcMuuNXl4p nv4WuBwcdE2Y05OsCFD9br/SSkIyksqHPBUvMxyfaodX4/xREln4TgeUO wc+JzeHNoM4V/PvW4vcA+X0i/cFCHk4Ril1SWRKbsoc37LgzYe5wX3afY 20NfkzE+rt+RV/yWCdzi+PcVWjQQInbbO6c9XtFYJ9AUiRpT6Mk+8NYis E2l6zlTthvw9VWrozbMl9Yb3/7kv92B8+NFyexNZs8gMvwcy6YcqBRadK Kad3KgsXGVL8YXKeHAL89l/3WnkgXmmSvRjtw+Lsro4YcMeCqSuqwvf2E A==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="159403637" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:20 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:19 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:16 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 01/10] ARM: dts: at91: use generic name for reset controller Date: Fri, 8 Apr 2022 11:00:22 +0300 Message-ID: <20220408080031.2527232-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Use generic name for reset controller of AT91 devices to comply with DT specifications. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel --- arch/arm/boot/dts/at91sam9260.dtsi | 2 +- arch/arm/boot/dts/at91sam9261.dtsi | 2 +- arch/arm/boot/dts/at91sam9263.dtsi | 2 +- arch/arm/boot/dts/at91sam9g45.dtsi | 2 +- arch/arm/boot/dts/at91sam9n12.dtsi | 2 +- arch/arm/boot/dts/at91sam9rl.dtsi | 2 +- arch/arm/boot/dts/at91sam9x5.dtsi | 2 +- arch/arm/boot/dts/sam9x60.dtsi | 2 +- arch/arm/boot/dts/sama5d2.dtsi | 2 +- arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d4.dtsi | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 7368347c9357..9d9820db9482 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -123,7 +123,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 7adc36ca8a46..259aca565305 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -603,7 +603,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_xtal", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index fe45d96239c9..c080df8c2312 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -151,7 +151,7 @@ tcb0: timer@fff7c000 { clock-names = "t0_clk", "slow_clk"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&slow_xtal>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 2ab730fd6472..09794561c7ce 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -137,7 +137,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 0785389f5507..556f35ce49e3 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -126,7 +126,7 @@ pmc: pmc@fffffc00 { interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; }; - rstc@fffffe00 { + reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 730d1182c73e..12c634811820 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -766,7 +766,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - rstc@fffffd00 { + reset-controller@fffffd00 { compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 395e883644cd..ea3b11336c79 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -134,7 +134,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index ec45ced3cde6..211e743e2597 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -671,7 +671,7 @@ pmc: pmc@fffffc00 { clock-names = "td_slck", "md_slck", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "microchip,sam9x60-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k 0>; diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 09c741e8ecb8..769befc06b57 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -662,7 +662,7 @@ securam: sram@f8044000 { ranges = <0 0xf8044000 0x1420>; }; - reset_controller: rstc@f8048000 { + reset_controller: reset-controller@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index d1841bffe3c5..ab124c09f70e 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1003,7 +1003,7 @@ pmc: pmc@fffffc00 { clock-names = "slow_clk", "main_xtal"; }; - reset_controller: rstc@fffffe00 { + reset_controller: reset-controller@fffffe00 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfffffe00 0x10>; clocks = <&clk32k>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index f6e3e6f57252..bc41d302dbf3 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -729,7 +729,7 @@ pmecc: ecc-engine@ffffc070 { }; }; - reset_controller: rstc@fc068600 { + reset_controller: reset-controller@fc068600 { compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; reg = <0xfc068600 0x10>; clocks = <&clk32k>; From patchwork Fri Apr 8 08:00:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 442ECC4321E for ; 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X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="151988423" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:24 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:23 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:19 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea , Rob Herring Subject: [PATCH v3 02/10] dt-bindings: reset: convert Atmel/Microchip reset controller to YAML Date: Fri, 8 Apr 2022 11:00:23 +0300 Message-ID: <20220408080031.2527232-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Convert Atmel/Microchip reset controller to YAML. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/atmel-sysregs.txt | 15 ------ .../reset/atmel,at91sam9260-reset.yaml | 49 +++++++++++++++++++ 2 files changed, 49 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 16eef600d599..ab1b352344ae 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -25,21 +25,6 @@ System Timer (ST) required properties: Its subnodes can be: - watchdog: compatible should be "atmel,at91rm9200-wdt" -RSTC Reset Controller required properties: -- compatible: Should be "atmel,-rstc". - can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" - it also can be "microchip,sam9x60-rstc" -- reg: Should contain registers location and length -- clocks: phandle to input clock. - -Example: - - rstc@fffffd00 { - compatible = "atmel,at91sam9260-rstc"; - reg = <0xfffffd00 0x10>; - clocks = <&clk32k>; - }; - RAMC SDRAM/DDR Controller required properties: - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml new file mode 100644 index 000000000000..34c40b875e20 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/atmel,at91sam9260-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip System Reset Controller + +maintainers: + - Claudiu Beznea + +description: | + The system reset controller can be used to reset the CPU. + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91sam9260-rstc + - atmel,at91sam9g45-rstc + - atmel,sama5d3-rstc + - microchip,sam9x60-rstc + - items: + - const: atmel,sama5d3-rstc + - const: atmel,at91sam9g45-rstc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + + reset-controller@fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; + }; From patchwork Fri Apr 8 08:00:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5312BC433EF for ; Fri, 8 Apr 2022 07:58:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230150AbiDHIAh (ORCPT ); Fri, 8 Apr 2022 04:00:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230110AbiDHIAb (ORCPT ); Fri, 8 Apr 2022 04:00:31 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9582816E205; 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Fri, 8 Apr 2022 00:58:27 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:24 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea , Rob Herring Subject: [PATCH v3 03/10] dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings Date: Fri, 8 Apr 2022 11:00:24 +0300 Message-ID: <20220408080031.2527232-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add documentation for SAMA7G5 reset controller. Compared with previous versions of reset controllers this one contains support for resetting in SoC devices (e.g. USB PHYs). Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- .../reset/atmel,at91sam9260-reset.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml index 34c40b875e20..98465d26949e 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -10,7 +10,8 @@ maintainers: - Claudiu Beznea description: | - The system reset controller can be used to reset the CPU. + The system reset controller can be used to reset the CPU. In case of + SAMA7G5 it can also reset some devices (e.g. USB PHYs). properties: compatible: @@ -21,21 +22,39 @@ properties: - atmel,at91sam9g45-rstc - atmel,sama5d3-rstc - microchip,sam9x60-rstc + - microchip,sama7g5-rstc - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc reg: - maxItems: 1 + minItems: 1 + items: + - description: base registers for system reset control + - description: registers for device specific reset control clocks: maxItems: 1 + "#reset-cells": + const: 1 + required: - compatible - reg - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,sama7g5-rstc + then: + required: + - "#reset-cells" + additionalProperties: false examples: From patchwork Fri Apr 8 08:00:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23810C433FE for ; Fri, 8 Apr 2022 07:58:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230181AbiDHIAk (ORCPT ); Fri, 8 Apr 2022 04:00:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230141AbiDHIAg (ORCPT ); Fri, 8 Apr 2022 04:00:36 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDC1A133162; Fri, 8 Apr 2022 00:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404711; x=1680940711; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YOmvHW09br4wqaZ9CNGSAXTcoCFrHeEMZh+iZBddp2Y=; b=gEGmsNHoRFzi25fdjW84QDOVfkdiXzNCpyT0ZBo7zpvZ57jZEWcTVR2t 3RcdKZOJ58xD3uwbdIymntxyDAMIfTdBXirQH5LXPVQ1Ng5eg52ME7V8p pIbI+Sz5VW5UC2OHWRLva5viUG2D7vZPUlZxdGlcqK1durgOqrUaopM/6 Btxu/R5/Ul+qLqlgZBu4fLqwSQSYrvamMKgMSpd3w+x0aTM7zxJPa/NmO DGs3cdEfGsgdYbYD6IiXf46HXNaNlW43Cvr6Ej4gAjX8LK7M5eJAV8CXp VXsRA2kaPrZc8R6+gHEN5oUMWrrramwe1gvE1chsgYIHxvblUP0CY1/wb w==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="168919696" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:31 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:28 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 04/10] dt-bindings: reset: add sama7g5 definitions Date: Fri, 8 Apr 2022 11:00:25 +0300 Message-ID: <20220408080031.2527232-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add reset bindings for SAMA7G5. At the moment only USB PHYs are included. Signed-off-by: Claudiu Beznea Acked-by: Philipp Zabel Acked-by: Rob Herring --- include/dt-bindings/reset/sama7g5-reset.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 include/dt-bindings/reset/sama7g5-reset.h diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h new file mode 100644 index 000000000000..2116f41d04e0 --- /dev/null +++ b/include/dt-bindings/reset/sama7g5-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_SAMA7G5_H +#define __DT_BINDINGS_RESET_SAMA7G5_H + +#define SAMA7G5_RESET_USB_PHY1 4 +#define SAMA7G5_RESET_USB_PHY2 5 +#define SAMA7G5_RESET_USB_PHY3 6 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ From patchwork Fri Apr 8 08:00:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99492C433EF for ; Fri, 8 Apr 2022 07:58:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230172AbiDHIAo (ORCPT ); Fri, 8 Apr 2022 04:00:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230177AbiDHIAj (ORCPT ); Fri, 8 Apr 2022 04:00:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 651ED114DCF; Fri, 8 Apr 2022 00:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404715; x=1680940715; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JTDMVVeRAftI6o86ZjLgMdKfDtLtM/8TSv3TYrBRguw=; b=sTisuAtyYEUmY8ZcsEwTBZYv3crdGuMXX4B3mTn7m4jsnkXb4tZq+r/9 jJJzLBmcF+GkpWye5w09V3g7x+rzshseYGvq8/7RFf60xzhiE+Zn6uQZj A5j6mJWqrU2wp5mLoxD7MZGnTrDbwsMkUhmkMzFfaKS/FirSPH+rzvPub SikIT0p+geFXslwTIQppAqTweGrPP2HwX4Jcx1dsxLQ0N55LM0kuUe7l+ wozkdd9gRB+4ndBCtwLWQlch98NXF2VyIkdq98Wt0xLYbUGBEw7/O2IoG ulKvZk2iRFDjHqTy0A/jQNOtj8cye0Kz50lFm+4BGTlcKbld4bUTZc9LN A==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="168919716" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:34 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:31 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 05/10] power: reset: at91-reset: document structures and enums Date: Fri, 8 Apr 2022 11:00:26 +0300 Message-ID: <20220408080031.2527232-6-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document structures and enums. Signed-off-by: Claudiu Beznea --- drivers/power/reset/at91-reset.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 64def79d557a..e62798750b6b 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -39,6 +39,17 @@ #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ +/** + * enum reset_type - reset types + * @RESET_TYPE_GENERAL: first power-up reset + * @RESET_TYPE_WAKEUP: return from backup mode + * @RESET_TYPE_WATCHDOG: watchdog fault + * @RESET_TYPE_SOFTWARE: processor reset required by software + * @RESET_TYPE_USER: NRST pin detected low + * @RESET_TYPE_CPU_FAIL: CPU clock failure detection + * @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault + * @RESET_TYPE_ULP2: ULP2 reset + */ enum reset_type { RESET_TYPE_GENERAL = 0, RESET_TYPE_WAKEUP = 1, @@ -50,6 +61,15 @@ enum reset_type { RESET_TYPE_ULP2 = 8, }; +/** + * struct at91_reset - AT91 reset specific data structure + * @rstc_base: base address for system reset + * @ramc_base: array with base addresses of RAM controllers + * @sclk: slow clock + * @nb: reset notifier block + * @args: SoC specific system reset arguments + * @ramc_lpr: SDRAM Controller Low Power Register + */ struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; From patchwork Fri Apr 8 08:00:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20322C433FE for ; Fri, 8 Apr 2022 07:59:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230207AbiDHIB1 (ORCPT ); Fri, 8 Apr 2022 04:01:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230209AbiDHIAn (ORCPT ); Fri, 8 Apr 2022 04:00:43 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57C4927CE1A; Fri, 8 Apr 2022 00:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404719; x=1680940719; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0e0YH0Rg0+RZ78xVEZkAn/PzbIGpQvxvmrrugnXNfzs=; b=RHaxdTyCbSTePSnM/ODbaVf0qo1tAOXng/BLy1HSMq8swttf33h1KrAV kxZuCqaqDZ1Mya3SSw7M54dfZwi751sUEPI1Iaq9njU1Na4PUU8qCVKcr vTkDQ05xc2yNJK9DtZ0+bIolIO1AUde9N2Ed54jgimWfWDMPyZDB9q6rK RyT4YAP3NWbB0V31fdmL3T7xziu5mvN3k/iChwG44f4g4+uM/5iam1qhR v2qi9hl8f52+mmVkHs93O8JI0FJS5/HGbAzwDlWaw6fqAxU6vv4hl38Yi jwnyKHBfE6Jj9nsNsn1iHZIIxw3vqt/ONZ8N+PSGGxXmEEj1DZZcWU/C7 w==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="168919728" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:38 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:38 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:35 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 06/10] power: reset: at91-reset: add at91_reset_data Date: Fri, 8 Apr 2022 11:00:27 +0300 Message-ID: <20220408080031.2527232-7-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add struct at91_reset_data to keep per platform related information. This is a prerequisite for adding reset_controller_dev support. Signed-off-by: Claudiu Beznea --- drivers/power/reset/at91-reset.c | 38 ++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index e62798750b6b..1b2aca3f490d 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -79,6 +79,16 @@ struct at91_reset { u32 ramc_lpr; }; +/** + * struct at91_reset_data - AT91 reset data + * @reset_args: SoC specific system reset arguments + * @n_device_reset: number of device resets + */ +struct at91_reset_data { + u32 reset_args; + u32 n_device_reset; +}; + /* * unless the SDRAM is cleanly shutdown before we hit the * reset register it can be left driving the data bus and @@ -173,29 +183,34 @@ static const struct of_device_id at91_ramc_of_match[] = { { /* sentinel */ } }; +static const struct at91_reset_data sam9260 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST, +}; + +static const struct at91_reset_data samx7 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST), + .data = &sam9260, }, { .compatible = "atmel,at91sam9g45-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,sama5d3-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,samx7-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { .compatible = "microchip,sam9x60-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { /* sentinel */ } }; @@ -204,6 +219,7 @@ MODULE_DEVICE_TABLE(of, at91_reset_of_match); static int __init at91_reset_probe(struct platform_device *pdev) { const struct of_device_id *match; + const struct at91_reset_data *data; struct at91_reset *reset; struct device_node *np; int ret, idx = 0; @@ -233,9 +249,13 @@ static int __init at91_reset_probe(struct platform_device *pdev) } match = of_match_node(at91_reset_of_match, pdev->dev.of_node); + if (!match || !match->data) + return -ENODEV; + + data = match->data; reset->nb.notifier_call = at91_reset; reset->nb.priority = 192; - reset->args = (u32)match->data; + reset->args = data->reset_args; reset->sclk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(reset->sclk)) From patchwork Fri Apr 8 08:00:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86AC2C433FE for ; Fri, 8 Apr 2022 07:59:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230245AbiDHIBX (ORCPT ); Fri, 8 Apr 2022 04:01:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230291AbiDHIBE (ORCPT ); Fri, 8 Apr 2022 04:01:04 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D287A8BF3C; Fri, 8 Apr 2022 00:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404722; x=1680940722; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MkfU6AYy6h1+kktDQXhPAMGLkiZB1whdbpVqDFoL51U=; b=CeMKVYbFp9lqJgYzzT2TviHHNry0PgDVyLDR/5hMBdb6KSeEQnpE6Tcy YejsFvB1f6lggAwclE4RypjhwXB1IKuN/U2Ik8NHAkiI3TEkLpsKcEKJ9 +amiaj1TABl78Yz7rao96NUiXdp99JOGUh9RH/0+B8MUAvGLYmso+PGyV ePg0L50bcdvNnhQ1FVWkE49jQ7ghd9twafymZ+Fj4dY5APbHYJFWHvxH8 sc4+PzSGLQ5MY4653Qx+JBj7mZwD0p3h64hu9+T2TceMKXPTz91x1Jkck PtZOfaxUWanO54abwgHZsymgdO0PTjiWQMhkwUAOHyZ3ItswfEP2js5eA A==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="91735414" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:41 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:41 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:38 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 07/10] power: reset: at91-reset: add reset_controller_dev support Date: Fri, 8 Apr 2022 11:00:28 +0300 Message-ID: <20220408080031.2527232-8-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org SAMA7G5 reset controller has 5 extra lines that goes to different devices (3 lines to USB PHYs, 1 line to DDR controller, 1 line to DDR PHY controller). These reset lines could be requested by different controller drivers (e.g. USB PHY driver) and these controllers' drivers could assert/deassert these lines when necessary. Thus add support for reset_controller_dev which brings this functionality. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel --- drivers/power/reset/at91-reset.c | 106 +++++++++++++++++++++++++++++-- 1 file changed, 102 insertions(+), 4 deletions(-) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 1b2aca3f490d..e25d8d38a2f8 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -17,10 +17,13 @@ #include #include #include +#include #include #include +#include + #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ @@ -65,7 +68,10 @@ enum reset_type { * struct at91_reset - AT91 reset specific data structure * @rstc_base: base address for system reset * @ramc_base: array with base addresses of RAM controllers + * @dev_base: base address for devices reset * @sclk: slow clock + * @rcdev: reset controller device + * @lock: lock for devices reset register access * @nb: reset notifier block * @args: SoC specific system reset arguments * @ramc_lpr: SDRAM Controller Low Power Register @@ -73,12 +79,17 @@ enum reset_type { struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; + void __iomem *dev_base; struct clk *sclk; + struct reset_controller_dev rcdev; + spinlock_t lock; struct notifier_block nb; u32 args; u32 ramc_lpr; }; +#define to_at91_reset(r) container_of(r, struct at91_reset, rcdev) + /** * struct at91_reset_data - AT91 reset data * @reset_args: SoC specific system reset arguments @@ -216,6 +227,87 @@ static const struct of_device_id at91_reset_of_match[] = { }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); +static int at91_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&reset->lock, flags); + val = readl_relaxed(reset->dev_base); + if (assert) + val |= BIT(id); + else + val &= ~BIT(id); + writel_relaxed(val, reset->dev_base); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int at91_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, true); +} + +static int at91_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, false); +} + +static int at91_reset_dev_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + u32 val; + + val = readl_relaxed(reset->dev_base); + + return !!(val & BIT(id)); +} + +static const struct reset_control_ops at91_reset_ops = { + .assert = at91_reset_assert, + .deassert = at91_reset_deassert, + .status = at91_reset_dev_status, +}; + +static int at91_reset_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + if (reset_spec->args[0] < SAMA7G5_RESET_USB_PHY1 || + reset_spec->args[0] > SAMA7G5_RESET_USB_PHY3) + return -EINVAL; + + return reset_spec->args[0]; +} + +static int at91_rcdev_init(struct at91_reset *reset, + const struct at91_reset_data *data, + struct platform_device *pdev) +{ + if (!data->n_device_reset) + return 0; + + reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1, + NULL); + if (IS_ERR(reset->dev_base)) + return -ENODEV; + + spin_lock_init(&reset->lock); + reset->rcdev.ops = &at91_reset_ops; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = data->n_device_reset; + reset->rcdev.of_reset_n_cells = 1; + reset->rcdev.of_xlate = at91_reset_of_xlate; + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + static int __init at91_reset_probe(struct platform_device *pdev) { const struct of_device_id *match; @@ -269,6 +361,10 @@ static int __init at91_reset_probe(struct platform_device *pdev) platform_set_drvdata(pdev, reset); + ret = at91_rcdev_init(reset, data, pdev); + if (ret) + goto disable_clk; + if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) { u32 val = readl(reset->rstc_base + AT91_RSTC_MR); @@ -277,14 +373,16 @@ static int __init at91_reset_probe(struct platform_device *pdev) } ret = register_restart_handler(&reset->nb); - if (ret) { - clk_disable_unprepare(reset->sclk); - return ret; - } + if (ret) + goto disable_clk; at91_reset_status(pdev, reset->rstc_base); return 0; + +disable_clk: + clk_disable_unprepare(reset->sclk); + return ret; } static int __exit at91_reset_remove(struct platform_device *pdev) From patchwork Fri Apr 8 08:00:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67713C433F5 for ; Fri, 8 Apr 2022 07:59:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230300AbiDHIBX (ORCPT ); Fri, 8 Apr 2022 04:01:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230321AbiDHIBE (ORCPT ); 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08 Apr 2022 00:58:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:45 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:42 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 08/10] power: reset: at91-reset: add support for SAMA7G5 Date: Fri, 8 Apr 2022 11:00:29 +0300 Message-ID: <20220408080031.2527232-9-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add support for SAMA7G5 including reset_controller_dev support for 3 lines (which are USB PHYs). Signed-off-by: Claudiu Beznea --- drivers/power/reset/at91-reset.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index e25d8d38a2f8..80bf0c023c17 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -202,6 +202,11 @@ static const struct at91_reset_data samx7 = { .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, }; +static const struct at91_reset_data sama7g5 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, + .n_device_reset = 3, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", @@ -223,6 +228,10 @@ static const struct of_device_id at91_reset_of_match[] = { .compatible = "microchip,sam9x60-rstc", .data = &samx7, }, + { + .compatible = "microchip,sama7g5-rstc", + .data = &sama7g5, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); From patchwork Fri Apr 8 08:00:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54FBBC433EF for ; Fri, 8 Apr 2022 07:59:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230452AbiDHIBL (ORCPT ); Fri, 8 Apr 2022 04:01:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230185AbiDHIBG (ORCPT ); Fri, 8 Apr 2022 04:01:06 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCAED11A568; Fri, 8 Apr 2022 00:58:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404732; x=1680940732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Bi4lSLV0zLBBZOD2CzxtM5qbY8InuCSGS8Woi7tp1Q=; b=qNOfvuaHWRNx9NJjRdeaWHepw/edUE5Vqo51xfe3mzhMFErpu6MXDeXg 8u8itYC+rorUnWsw1N0g1Qswc9zWi68J6mJJT0mGQOSVAv3KcCg2nNktt bD6/SBHIy6I1cKx7OgVXtuz+foERmZ24NYtAH042F78C3UbluMrC6IeP2 9KS2fDc4nDAqOjZeqzVjsv6s/WdQsenZTSqldk/HYE7emYFSbckm8ar3b Hxo1+xRVMpkvu3nQ6uyMZUyd+TLgm5wvvrfLuCEZeUnwP0FefCuJ8XbPE atJoQUIF/zR/qUq0dcHZhU3HhVejJzdRmNW42u3jdpB1fxHtMRN4RuQWy A==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="159403684" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:49 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:46 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 09/10] ARM: dts: at91: sama7g5: add reset-controller node Date: Fri, 8 Apr 2022 11:00:30 +0300 Message-ID: <20220408080031.2527232-10-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add reset controller node. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..aa0e72d4d2d5 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -122,6 +122,13 @@ pmc: pmc@e0018000 { clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; From patchwork Fri Apr 8 08:00:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12806259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 317B9C4332F for ; Fri, 8 Apr 2022 07:59:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230379AbiDHIBM (ORCPT ); Fri, 8 Apr 2022 04:01:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230358AbiDHIBH (ORCPT ); Fri, 8 Apr 2022 04:01:07 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A418D29689F; Fri, 8 Apr 2022 00:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649404734; x=1680940734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sxYyjrK7igJydMiwAHuSHa3rYPohXNdb9pi8bMAAvkw=; b=EmV2joN2Je9tx3U1j3A5VOasq6h02rFdOev7pmgsM98N8jS/6PIGTi4o s9hgsnHhMKt61u++ZbjdrBOj/zTd9fe66Czp6Xr0uQo18iLa6gD6Q1yW0 ln6OOAa3vxHGXpplpKytqrERgl7DGRIWUb4lferxOaJArYcAm0qP9qhai xXnDbk9it9qlC6megSI0VfoWdI+45vGO8lAtoaZdiadAN2oK9Mh+7+yS4 ZWIUTDIGd0lKIJVzoBGYdxBLmTKhc0bCnXQZp62lEPVkvl0kJIaSfZVw8 EYIJjDHOYxeuDI3tOWfMbEacsJGeDMopcNauc1pF5WjLqk/n9uBQTxiPO g==; X-IronPort-AV: E=Sophos;i="5.90,244,1643698800"; d="scan'208";a="159403694" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 00:58:54 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 00:58:53 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 00:58:49 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 10/10] ARM: configs: sama7: enable CONFIG_RESET_CONTROLLER Date: Fri, 8 Apr 2022 11:00:31 +0300 Message-ID: <20220408080031.2527232-11-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220408080031.2527232-1-claudiu.beznea@microchip.com> References: <20220408080031.2527232-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Enable CONFIG_RESET_CONTROLLER. It is necessary for resetting individual in SoC devices. Signed-off-by: Claudiu Beznea Acked-by: Nicolas Ferre --- arch/arm/configs/sama7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 0368068e04d9..ce20bef1246e 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -180,6 +180,7 @@ CONFIG_IIO_SW_TRIGGER=y CONFIG_AT91_SAMA5D2_ADC=y CONFIG_PWM=y CONFIG_PWM_ATMEL=y +CONFIG_RESET_CONTROLLER=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_FANOTIFY=y