From patchwork Fri Apr 8 14:36:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12806847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B3D1C433EF for ; Fri, 8 Apr 2022 14:38:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4Ilcsbj9e3hbBJK9XIOIsnPm11TZ2KgYzQpBdPcMdE0=; b=eHohWsCKQH1olA 4VYRATwPuzek3A15dKgtwGEIvEcPC9rVVtjRVhSEmYX6C3MpKlUhPqU0+o+BKzTo0wG+E6xWcLGKI G4F7jCJe5VYf4MmXZNU3PkaloBfJLRC1f+GQlX974fwCWsxQreEdXEkob13lz3fwHX4QqpJQS9WGx rFIg5HqstonHnYmhycMjN1LAKVistfSSU/bDgsiFMH8DfpnjB8ZV7O1L2k7vtekUCJPz/BgdRhycU RMrNqLY0vh5DJE3f817MFGqK+IPb7VXj4eyRJZ7IG8UBlF1gtQdY7UcCORFNKUz1ZN053AKRBRvej IqTduAOZ+Uy1tOOR2HSA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkG-0000dh-CR; Fri, 08 Apr 2022 14:37:52 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkD-0000bY-09 for linux-riscv@lists.infradead.org; Fri, 08 Apr 2022 14:37:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649428669; x=1680964669; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BVZx33NKupiZCfwz779hCCkPFx236F041juK4+XrqfM=; b=pWPX84O5PBjo5WMLTv1Dr2IwgQWmrSj5138Paqjzz2zxaaBKcMiN5eD5 HVxlWRKTLvaqZR5gz5eKTL7OF5KKZ16tj62W9BfBZVzWcAnKNGq/aUues gk+rbXC/GA2/31BgSdNmDpBp5yJDflybhlDWJdODdm0e1conXFCvCsZKK HvVZure2PDYE15wzGM4MrAp+56uDpD7RlSzJTFOeb7DDE60mlT3iUEUlM aQbRN+pAb1i5S13OoFfnLP4EwuSecYYoKXV6ZnekJ/gVqCv/OZE/9nzdM gIIg/46iyhcVICyxf+uF/JjJbNNsqv0zqlsf+Ci8TWc9H7BLapAv8oTnc g==; X-IronPort-AV: E=Sophos;i="5.90,245,1643698800"; d="scan'208";a="152027968" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 07:37:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 07:37:45 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 07:37:41 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 1/7] dt-bindings: clk: mpfs document msspll dri registers Date: Fri, 8 Apr 2022 14:36:41 +0000 Message-ID: <20220408143646.3693104-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_073749_127525_B2BCF2E7 X-CRM114-Status: UNSURE ( 7.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org As there are two sections of registers that are responsible for clock configuration on the PolarFire SoC: add the dynamic reconfiguration interface section to the binding & describe what each of the sections are used for. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- .../devicetree/bindings/clock/microchip,mpfs.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 0c15afa2214c..42919df322ab 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -22,7 +22,14 @@ properties: const: microchip,mpfs-clkcfg reg: - maxItems: 1 + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, axi, ahb and + rtc/mtimer reference clocks as well as enable and reset for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss pll clocks: maxItems: 1 @@ -51,7 +58,7 @@ examples: #size-cells = <2>; clkcfg: clock-controller@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&ref>; #clock-cells = <1>; }; From patchwork Fri Apr 8 14:36:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12806849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9998C433F5 for ; Fri, 8 Apr 2022 14:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YmRBDqzYavqJXyBmh5Ypgle8J7V7hXNUzq7cJZeAQMc=; b=ir2CSHS9ulUZyw 2DheJCBpJtkH08DV4FI7cy7v9E2qn5b13dNBwuAgE409CUm4LS5Xp/KQOEYuGAjjcrBJnB/zgNmKE l9Uzzzu5C3ypsNRwTWA8TvZJs9Vt4bpJMNvqVXpW5I0uEoCt7+yOoMRE8wMT7f8Mearq83tfDwPcK 07GMjK2NY7CEXwoOzCdAoSOwKHPeKl3FxE1oWACqVEFqQ3Lz8vZfj2AOcEiILwo4aR6vSYXsjCTb3 Hy3ZeajPi+CDpL0yxZjIljnLLT5JuyMlpqxfkavqkYIqruu49HXRMBLNV61pUB3OxOCA426EUzKYz 50eBzY+kDamOxGsOmdPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkK-0000gW-IH; Fri, 08 Apr 2022 14:37:56 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkE-0000dE-TY for linux-riscv@lists.infradead.org; Fri, 08 Apr 2022 14:37:52 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649428670; x=1680964670; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z2Bl5qGTo3dfoTtGTbFb0RM34Y/R4subC/+ygZpA6i0=; b=2FbMk+pDFICKvsWN2pRlixOQ8CZafx1dQPaok08xB6eJ6s+Rvoc50YIO AX/ZDOcHbFVbXSMgXZZB629xIYFIwAL2+CWbm/pQeQSPfVi8oSAi095md BBcC7FREAYhx0z7+puYAaZgzShgGa+qq4e+fjfB2ONE72VxPiNem0qRLC dl3TVrLhzN1FNAceBvmlOFugUNAc2DDP5k7ubDEUei/fcWyOgMTOnMk1m GuGsnAfgv630NEOF/UzH9sQKsT3f9xmZoHexN1cjfsfQpGKBjaurYFdzF 9tbg8RUILhGRHFUrggSAUZcYjVeiIobEoHP9VM3nz47NFihh1FQrmGHLP Q==; X-IronPort-AV: E=Sophos;i="5.90,245,1643698800"; d="scan'208";a="154925644" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 07:37:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 07:37:48 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 07:37:45 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 2/7] dt-bindings: clk: mpfs: add defines for two new clocks Date: Fri, 8 Apr 2022 14:36:42 +0000 Message-ID: <20220408143646.3693104-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_073751_051166_3F89942C X-CRM114-Status: UNSURE ( 8.53 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The RTC reference and MSSPLL were previously not documented or defined, as they were unused. Add their defines to the PolarFire SoC header. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- include/dt-bindings/clock/microchip,mpfs-clock.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 73f2a9324857..3cba46b9191f 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -1,15 +1,18 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* * Daire McNamara, - * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ #define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ +#define CLK_MSSPLL 34 + #define CLK_CPU 0 #define CLK_AXI 1 #define CLK_AHB 2 +#define CLK_RTCREF 33 #define CLK_ENVM 3 #define CLK_MAC0 4 From patchwork Fri Apr 8 14:36:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12806848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A189C433FE for ; Fri, 8 Apr 2022 14:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=l3UsyZq91i79YqjDRzQpDaQm6CEhifhtAh/cFYG8bws=; b=Y0EuJ+SfmzzsWc BgG9Zl3FnONVy0LHFfY9a2EhOwk78+yWGhTxPT+anTPHDKAZ66uBwzUf17ilPtbHknRF2ZIGAYKk3 OuG0x2SDxAttVs/YK6tHIpagaL6+PWNxfd6/7lit9cu8OvJFrExbpopNie3Z6hjPv47Nxgj9nt1jy 72phTr9S0VWsvKRG7Cr12qL3FVcBVhQyFq9toaCbRyiFbTGPHQTzIxVnwupnPJk7J/y4c42b0GE5d ns7+HtGBZQ+glJLJdvlqPasVLS6Sm5gx0as9BPHI+vWq4ogi8NSOCjI9L1jnfBFJ2eXDByT/+NFCn RJzXjrgEyTHH5/GaJdEQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkM-0000hk-LM; Fri, 08 Apr 2022 14:37:58 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkH-0000dt-9T for linux-riscv@lists.infradead.org; Fri, 08 Apr 2022 14:37:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649428673; x=1680964673; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RVSiySLuyH36Oge4rtu7xhraomGEeU6vHquQBOWopMw=; b=rvva9Is8riJL6jI/klLavxEASAdY8hsmy54wGjv9vb1EbBFZERNS7YQ2 mb1OIB1Kxlfv77BlsKa1OEH2xWMotdL26zYcIECBjOoirdmSexZbPQb8z Kp5JBoBso5GSIL5DhKB1Cviq/nkdmySq+lsB5OBXvOh/OjHdqCY976lbZ 0VBzAODBCu8cSDpp78DzM5sVbLhQQRfRbO/3FV5qXGyJXXZbDf9YRxcBB fHW6LIwTQVv9VyDeCj3SYxqarVGuP9DK4m/1s24JeJ95gswuJgKnDq6dY SKm5DFlxCrqi78D8W9fofHR+eOMAHu436ICEI4OvQERa6EZeEL1PcB2QF w==; X-IronPort-AV: E=Sophos;i="5.90,245,1643698800"; d="scan'208";a="91773250" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 07:37:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 07:37:52 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 07:37:49 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 3/7] dt-bindings: rtc: add refclk to mpfs-rtc Date: Fri, 8 Apr 2022 14:36:43 +0000 Message-ID: <20220408143646.3693104-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_073753_427154_0679737D X-CRM114-Status: UNSURE ( 8.25 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The rtc on PolarFire SoC does not use the AHB clock as its reference frequency, but rather a 1 MHz refclk that it shares with MTIMER. Add this second clock to the binding as a required property. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- .../bindings/rtc/microchip,mfps-rtc.yaml | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml index a2e984ea3553..1ffd97dbe6b9 100644 --- a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -31,11 +31,18 @@ properties: to that of the RTC's count register. clocks: - maxItems: 1 + items: + - description: | + AHB clock + - description: | + Reference clock: divided by the prescaler to create a time-based strobe (typically 1 Hz) + for the calendar counter. By default, the rtc on the PolarFire SoC shares it's reference + with MTIMER so this will be a 1 MHz clock. clock-names: items: - const: rtc + - const: rtcref required: - compatible @@ -48,11 +55,12 @@ additionalProperties: false examples: - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" rtc@20124000 { compatible = "microchip,mpfs-rtc"; reg = <0x20124000 0x1000>; - clocks = <&clkcfg 21>; - clock-names = "rtc"; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; interrupts = <80>, <81>; }; ... From patchwork Fri Apr 8 14:36:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12806851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F9A6C433FE for ; Fri, 8 Apr 2022 14:38:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wZ40EKkWKZUZN8/ZeOxxH4ROSUbkn7mzyIhOm7q/6n8=; b=uf7EUQng+w1F+/ 6jbjT1nIC4D1Z7UNuxM7Tv4115N+Mk/BLvGJnNurSlWJFc8dGS7fxuDbluGxCdC9mYVVMSL4COOfL q03DT5ae1PN7DB98FSzKRP+fBGBZSqeE2mW92YBIxOmVS6GWQ0TwDvt9WRVVQTCUl1I440KXIkE+U MsZ/8ildArMCZY2t5eIuPgBRS/j4uDPzObm5D1oe/GwmspcE3/FNrIzv2D+xqYW5PNRqovhwmcdit gma52eX++scCeobj2b+QGpuE/3R4RvzWvNZ4nQKaDnumfgCO/Q2IV+Yk0BQGioQhDLRCwMIfnoAlL p7rIF8uDWCP5JX9ysW9A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkb-0000qT-5s; Fri, 08 Apr 2022 14:38:13 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkK-0000dE-Ia for linux-riscv@lists.infradead.org; Fri, 08 Apr 2022 14:37:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649428676; x=1680964676; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s6k0EMPVNadnlFbw35LTdz10rsLBmzoHZSYS6p8TPBc=; b=p3e6EY7OSsl85NMzu2a0GJwZ8yfLdEI3sJoGEhqOzeUlQ1CmucMx92bV gjxLW9dLVok9TgiDjAIU/fP8X3kYi90Qcv2oMrwkZaL/C1tJCYZALReyL VU8YdIrW7aU0YRvoh1v4k2oq+8YZPrkgmglnE4Y9L6xdpY1kyXjarplk4 Ue4BNKcMst/1zu2Fm8buALsLhz+rxRM5nyPtI/79I2FbEHx+fWBBA25vX 1eZNDj8Sp42VxeI/3L8euMFhmbU8ibCL8pZCrf44gk48anTuUIozPBdO2 GseSvWIGkJj8DXq/i71KIb1n52ac/0yov7DOgpbJuNm3J/x3vjuP+hHyS Q==; X-IronPort-AV: E=Sophos;i="5.90,245,1643698800"; d="scan'208";a="154925651" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 07:37:56 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 07:37:55 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 07:37:52 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 4/7] clk: microchip: mpfs: re-parent the configurable clocks Date: Fri, 8 Apr 2022 14:36:44 +0000 Message-ID: <20220408143646.3693104-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_073756_773406_D80D5EC4 X-CRM114-Status: GOOD ( 23.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently the mpfs clock driver uses a reference clock called the "msspll", set in the device tree, as the parent for the cpu/axi/ahb (config) clocks. The frequency of the msspll is determined by the FPGA bitstream & the bootloader configures the clock to match the bitstream. The real reference is provided by a 100 or 125 MHz off chip oscillator. However, the msspll clock is not actually the parent of all clocks on the system - the reference clock for the rtc/mtimer actually has the off chip oscillator as its parent. In order to fix this, add support for reading the configuration of the msspll & reparent the "config" clocks so that they are derived from this clock rather than the reference in the device tree. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- @Stephen/Mike: Is it acceptable to add the recalc rate without a set rate? If not lmk and I will add one. drivers/clk/microchip/clk-mpfs.c | 151 +++++++++++++++++++++++++++---- 1 file changed, 132 insertions(+), 19 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index c82a79a5979f..66251a5f4a03 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -11,19 +11,46 @@ #include /* address offset of control registers */ +#define REG_MSSPLL_REF_CR 0x08u +#define REG_MSSPLL_POSTDIV_CR 0x10u +#define REG_MSSPLL_SSCG_2_CR 0x2Cu #define REG_CLOCK_CONFIG_CR 0x08u #define REG_SUBBLK_CLOCK_CR 0x84u +#define MSSPLL_FBDIV_SHIFT 0x00u +#define MSSPLL_FBDIV_WIDTH 0x0Cu +#define MSSPLL_REFDIV_SHIFT 0x08u +#define MSSPLL_REFDIV_WIDTH 0x06u +#define MSSPLL_POSTDIV_SHIFT 0x08u +#define MSSPLL_POSTDIV_WIDTH 0x07u +#define MSSPLL_FIXED_DIV 4u + struct mpfs_clock_data { void __iomem *base; + void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; }; +struct mpfs_msspll_hw_clock { + void __iomem *base; + unsigned int id; + u32 reg_offset; + u32 shift; + u32 width; + u32 flags; + struct clk_hw hw; + struct clk_init_data init; +}; + +#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) + struct mpfs_cfg_clock { const struct clk_div_table *table; unsigned int id; + u32 reg_offset; u8 shift; u8 width; + u8 flags; }; struct mpfs_cfg_hw_clock { @@ -54,7 +81,7 @@ struct mpfs_periph_hw_clock { */ static DEFINE_SPINLOCK(mpfs_clk_lock); -static const struct clk_parent_data mpfs_cfg_parent[] = { +static const struct clk_parent_data mpfs_ext_ref[] = { { .index = 0 }, }; @@ -68,6 +95,75 @@ static const struct clk_div_table mpfs_div_ahb_table[] = { { 0, 0 } }; +static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 mult, ref_div, postdiv; + + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; + postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); + + return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); +} + +static const struct clk_ops mpfs_clk_msspll_ops = { + .recalc_rate = mpfs_clk_msspll_recalc_rate, +}; + +#define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ + .id = _id, \ + .shift = _shift, \ + .width = _width, \ + .reg_offset = _offset, \ + .flags = _flags, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ +} + +static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { + CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, + MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), +}; + +static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, + void __iomem *base) +{ + msspll_hw->base = base; + + return devm_clk_hw_register(dev, &msspll_hw->hw); +} + +static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, + unsigned int num_clks, struct mpfs_clock_data *data) +{ + void __iomem *base = data->msspll_base; + unsigned int i; + int ret; + + for (i = 0; i < num_clks; i++) { + struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; + + ret = mpfs_clk_register_msspll(dev, msspll_hw, base); + if (ret) + return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", + CLK_MSSPLL); + + data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; + } + + return 0; +} + +/* + * "CFG" clocks + */ + static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); @@ -75,10 +171,10 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p void __iomem *base_addr = cfg_hw->sys_base; u32 val; - val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift; + val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; val &= clk_div_mask(cfg->width); - return prate / (1u << val); + return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); } static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) @@ -104,11 +200,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned return divider_setting; spin_lock_irqsave(&mpfs_clk_lock, flags); - - val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR); + val = readl_relaxed(base_addr + cfg->reg_offset); val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); val |= divider_setting << cfg->shift; - writel_relaxed(val, base_addr + REG_CLOCK_CONFIG_CR); + writel_relaxed(val, base_addr + cfg->reg_offset); spin_unlock_irqrestore(&mpfs_clk_lock, flags); @@ -121,19 +216,23 @@ static const struct clk_ops mpfs_clk_cfg_ops = { .set_rate = mpfs_cfg_clk_set_rate, }; -#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags) { \ - .cfg.id = _id, \ - .cfg.shift = _shift, \ - .cfg.width = _width, \ - .cfg.table = _table, \ - .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_cfg_ops, \ - _flags), \ +#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ + .cfg.id = _id, \ + .cfg.shift = _shift, \ + .cfg.width = _width, \ + .cfg.table = _table, \ + .cfg.reg_offset = _offset, \ + .cfg.flags = _flags, \ + .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ } static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { - CLK_CFG(CLK_CPU, "clk_cpu", mpfs_cfg_parent, 0, 2, mpfs_div_cpu_axi_table, 0), - CLK_CFG(CLK_AXI, "clk_axi", mpfs_cfg_parent, 2, 2, mpfs_div_cpu_axi_table, 0), - CLK_CFG(CLK_AHB, "clk_ahb", mpfs_cfg_parent, 4, 2, mpfs_div_ahb_table, 0), + CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0, + REG_CLOCK_CONFIG_CR), + CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0, + REG_CLOCK_CONFIG_CR), + CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, + REG_CLOCK_CONFIG_CR), }; static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, @@ -159,13 +258,17 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->cfg.id); - id = cfg_hws[i].cfg.id; + id = cfg_hw->cfg.id; data->hw_data.hws[id] = &cfg_hw->hw; } return 0; } +/* + * peripheral clocks - devices connected to axi or ahb buses. + */ + static int mpfs_periph_clk_enable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); @@ -312,8 +415,9 @@ static int mpfs_clk_probe(struct platform_device *pdev) unsigned int num_clks; int ret; - /* CLK_RESERVED is not part of cfg_clks nor periph_clks, so add 1 */ - num_clks = ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1; + /* CLK_RESERVED is not part of clock arrays, so add 1 */ + num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) + + ARRAY_SIZE(mpfs_periph_clks) + 1; clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); if (!clk_data) @@ -323,8 +427,17 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (IS_ERR(clk_data->base)) return PTR_ERR(clk_data->base); + clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(clk_data->msspll_base)) + return PTR_ERR(clk_data->msspll_base); + clk_data->hw_data.num = num_clks; + ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), + clk_data); + if (ret) + return ret; + ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); if (ret) return ret; From patchwork Fri Apr 8 14:36:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12806854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7EE3C433EF for ; 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08 Apr 2022 07:37:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 07:37:59 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 07:37:56 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 5/7] clk: microchip: mpfs: rename sys_base to base Date: Fri, 8 Apr 2022 14:36:45 +0000 Message-ID: <20220408143646.3693104-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_073800_052252_D9417194 X-CRM114-Status: GOOD ( 12.11 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Having added a second set of registers for the msspll, sys_base no longer really makes sense as a variable name. Renaming it to base will make it consistent with mpfs_clock_data & several function arguments. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 66251a5f4a03..f22d4b40ef28 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -55,7 +55,7 @@ struct mpfs_cfg_clock { struct mpfs_cfg_hw_clock { struct mpfs_cfg_clock cfg; - void __iomem *sys_base; + void __iomem *base; struct clk_hw hw; struct clk_init_data init; }; @@ -69,7 +69,7 @@ struct mpfs_periph_clock { struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; - void __iomem *sys_base; + void __iomem *base; struct clk_hw hw; }; @@ -168,7 +168,7 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; + void __iomem *base_addr = cfg_hw->base; u32 val; val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; @@ -189,7 +189,7 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; + void __iomem *base_addr = cfg_hw->base; unsigned long flags; u32 val; int divider_setting; @@ -236,9 +236,9 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { }; static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, - void __iomem *sys_base) + void __iomem *base) { - cfg_hw->sys_base = sys_base; + cfg_hw->base = base; return devm_clk_hw_register(dev, &cfg_hw->hw); } @@ -246,14 +246,14 @@ static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *c static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; + void __iomem *base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; - ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); + ret = mpfs_clk_register_cfg(dev, cfg_hw, base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->cfg.id); @@ -273,7 +273,7 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; + void __iomem *base_addr = periph_hw->base; u32 reg, val; unsigned long flags; @@ -292,7 +292,7 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; + void __iomem *base_addr = periph_hw->base; u32 reg, val; unsigned long flags; @@ -309,7 +309,7 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; + void __iomem *base_addr = periph_hw->base; u32 reg; reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); @@ -379,9 +379,9 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { }; static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, - void __iomem *sys_base) + void __iomem *base) { - periph_hw->sys_base = sys_base; + periph_hw->base = base; return devm_clk_hw_register(dev, &periph_hw->hw); } @@ -389,14 +389,14 @@ static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_cl static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; + void __iomem *base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; - ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); + ret = mpfs_clk_register_periph(dev, periph_hw, base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->periph.id); From patchwork Fri Apr 8 14:36:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12806852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 063DCC433EF for ; Fri, 8 Apr 2022 14:38:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 8 Apr 2022 07:37:59 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 6/7] clk: microchip: mpfs: add RTCREF clock control Date: Fri, 8 Apr 2022 14:36:46 +0000 Message-ID: <20220408143646.3693104-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_073803_972759_26873D57 X-CRM114-Status: GOOD ( 12.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The reference clock used by the PolarFire SoC's onboard rtc was missing from the clock driver. Add this clock at the "config" clock level, with the external reference clock as its parent. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index f22d4b40ef28..4a506d0140d4 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -15,6 +15,7 @@ #define REG_MSSPLL_POSTDIV_CR 0x10u #define REG_MSSPLL_SSCG_2_CR 0x2Cu #define REG_CLOCK_CONFIG_CR 0x08u +#define REG_RTC_CLOCK_CR 0x0Cu #define REG_SUBBLK_CLOCK_CR 0x84u #define MSSPLL_FBDIV_SHIFT 0x00u @@ -95,6 +96,17 @@ static const struct clk_div_table mpfs_div_ahb_table[] = { { 0, 0 } }; +/* + * The only two supported reference clock frequencies for the PolarFire SoC are + * 100 and 125 MHz, as the rtc reference is required to be 1 MHz. + * It therefore only needs to have divider table entries corresponding to + * divide by 100 and 125. + */ +static const struct clk_div_table mpfs_div_rtcref_table[] = { + { 100, 100 }, { 125, 125 }, + { 0, 0 } +}; + static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); @@ -233,6 +245,16 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { REG_CLOCK_CONFIG_CR), CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, REG_CLOCK_CONFIG_CR), + { + .cfg.id = CLK_RTCREF, + .cfg.shift = 0, + .cfg.width = 12, + .cfg.table = mpfs_div_rtcref_table, + .cfg.reg_offset = REG_RTC_CLOCK_CR, + .cfg.flags = CLK_DIVIDER_ONE_BASED, + .hw.init = + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), + } }; static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, @@ -351,7 +373,7 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), - CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(AHB), 4, 0), + CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0), CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), From patchwork Fri Apr 8 14:36:47 2022 Content-Type: text/plain; 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Rename the msspllclk node to mssrefclk since this is now the input to, not the output of, the msspll clock. Control of the msspll clock has been moved into the clock configurator, so add the register range for it to the clk configurator. Finally, add a new output of the clock config block which will provide the 1M reference clock for the MTIMER and the rtc. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 +- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index cd2fe80fa81a..3392153dd0f1 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -45,7 +45,7 @@ ddrc_cache_hi: memory@1000000000 { }; &refclk { - clock-frequency = <600000000>; + clock-frequency = <125000000>; }; &mmuart1 { diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 3b48b7f35410..746c4d4e7686 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -141,7 +141,7 @@ cpu4_intc: interrupt-controller { }; }; - refclk: msspllclk { + refclk: mssrefclk { compatible = "fixed-clock"; #clock-cells = <0>; }; @@ -190,7 +190,7 @@ plic: interrupt-controller@c000000 { clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&refclk>; #clock-cells = <1>; }; @@ -393,8 +393,8 @@ rtc: rtc@20124000 { reg = <0x0 0x20124000 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <80>, <81>; - clocks = <&clkcfg CLK_RTC>; - clock-names = "rtc"; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; status = "disabled"; };