From patchwork Mon Apr 11 06:55:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12808554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C77EC4321E for ; Mon, 11 Apr 2022 06:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245137AbiDKG6c (ORCPT ); Mon, 11 Apr 2022 02:58:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245123AbiDKG62 (ORCPT ); Mon, 11 Apr 2022 02:58:28 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3981F2AC56; Sun, 10 Apr 2022 23:56:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660175; x=1681196175; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=8WoLxVpJwsGyepr056PagqgtM+agMi/R0Cz0UrtHKc0=; b=qJIYUCVdvRo7djC0CqQwA3hSF0XL9tyOUHxPeTdAn3t/7vM/URZ6Hl6j MXDdgauAnqhQJNk6fR5tyVYXJALOwAAciDjy7RS6i+1U3hPXnQkWmJ1KK sSVooTsflTHSzKyclpppk/Wpk+rPiXo9fPv8cKpWsl6crQ5UbcaO6NfXR g=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:15 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:13 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:52 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 31C2D3A9B; Mon, 11 Apr 2022 12:25:51 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes Date: Mon, 11 Apr 2022 12:25:37 +0530 Message-Id: <1649660143-22400-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add reserved memory nodes to the SDX65 dtsi as defined by the memory map. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 +++++++++++++++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 45 ++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index ad99f56..5d51cc4 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -23,6 +23,27 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_dsm: mpss_dsm_region@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; + + ipa_fw_mem: ipa_fw_region@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: mpss_adsp_region@90800000 { + no-map; + reg = <0x90800000 0x10000000>; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7e2697f..365df74 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -66,6 +66,51 @@ reg = <0x8fee0000 0x20000>; no-map; }; + + secdata_mem: secdata_region@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + hyp_mem: hyp_region@8fd00000 { + no-map; + reg = <0x8fd00000 0x80000>; + }; + + aop_mem: aop_regions@8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + access_control_mem: access_control_region@8fd80000 { + no-map; + reg = <0x8fd80000 0x80000>; + }; + + smem_mem: smem_region@8fe20000 { + no-map; + reg = <0x8fe20000 0xc0000>; + }; + + tz_mem: tz_mem_region@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + }; + + tz_apps_mem: tz_apps_mem_region@90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + + tz_heap_mem: tz_heap_region@8fcad000 { + no-map; + reg = <0x8fcad000 0x40000>; + }; + + llcc_tcm_mem: llcc_tcm_region@15800000 { + no-map; + reg = <0x15800000 0x800000>; + }; }; soc: soc { From patchwork Mon Apr 11 06:55:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12808556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 448BCC433EF for ; Mon, 11 Apr 2022 06:56:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245155AbiDKG6f (ORCPT ); Mon, 11 Apr 2022 02:58:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245130AbiDKG6b (ORCPT ); Mon, 11 Apr 2022 02:58:31 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 841172AE10; Sun, 10 Apr 2022 23:56:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660177; x=1681196177; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=mjQU6c8wuWG8/rxJT2YYtKSSiAfz4IOR5/Ce9q0IxPc=; b=KgZ2utrO6Nx2Sls8ZZdCkVAgqVM3FpYC/i/Oqq+++n3yoxhB/jConIbs Mn+6KoWrxPGD+cVp2jP+tbIHwbltXUSAa1EteIDUbK9oRDU9ZAGTta0i0 3zNDKClibYnACDe1M9DtrxkbV3ZVdQlnoujIuhuOAxUHz/068bNcGfHzH A=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:17 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:15 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:52 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id B12483AA0; Mon, 11 Apr 2022 12:25:51 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 2/7] dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible Date: Mon, 11 Apr 2022 12:25:38 +0530 Message-Id: <1649660143-22400-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence, document the compatible with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Rohit Agarwal --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 6a8cc26..e1023e8 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -24,6 +24,7 @@ Required properties: "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; + "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" NOTE that some old device tree files may be floating around that only have the string "qcom,sdhci-msm-v4" without the SoC compatible string From patchwork Mon Apr 11 06:55:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12808557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DD4DC433EF for ; Mon, 11 Apr 2022 06:56:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245177AbiDKG6l (ORCPT ); Mon, 11 Apr 2022 02:58:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245124AbiDKG6d (ORCPT ); Mon, 11 Apr 2022 02:58:33 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66C702AC5F; Sun, 10 Apr 2022 23:56:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660179; x=1681196179; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+KRMi56LVuC86kOFkBF4O8ESf02mAw9nnU+hNYWAH/Y=; b=rAc57Nx/nGjipDWyoTivQwXoNUPOAeDozpyz+YLp7vpnEhXbM6eoOIKL JpjqGC/Vb0be4hTZmywl8HzbVDrFoXbQGATObgFphPpnJ/f0maia91uwk Kr0C/WItqMOG4OOxFr0pYlRtVJKKUA8rwLAEMwqdg74xwHt6O96vjMJ18 s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:19 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:17 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:53 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 3509B3AA2; Mon, 11 Apr 2022 12:25:52 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller Date: Mon, 11 Apr 2022 12:25:39 +0530 Message-Id: <1649660143-22400-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add devicetree support for SDHCI controller found in Qualcomm SDX65 platform. The SDHCI controller is based on the MSM SDHCI v5 IP. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 365df74..632ac78 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -168,6 +168,19 @@ #interrupt-cells = <2>; }; + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>; From patchwork Mon Apr 11 06:55:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12808555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9D00C43219 for ; Mon, 11 Apr 2022 06:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245143AbiDKG6e (ORCPT ); Mon, 11 Apr 2022 02:58:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245127AbiDKG6a (ORCPT ); Mon, 11 Apr 2022 02:58:30 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61A292AE0F; Sun, 10 Apr 2022 23:56:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660177; x=1681196177; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=4sArmmPqK1fpsAra+ctcw1Mg8/kPFO/JwQ40cELNy00=; b=T4R6Bey9+JlfXjVcnQcqUtdIiy2cxpfH1t14aPnk+6V72T1JMvXo1vvG QphbyzjR7nmiIKNciYbBAq3iZn4K36V53HJMPgfS9HTYZyDnk32KkPRIa 3QFf5mXQQqLs+FE9gKbv9YqZsQvQvQiM9y8Q9r+iG3QchjwuW2RGipVx2 Y=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:17 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:15 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:53 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id BC73C37D9; Mon, 11 Apr 2022 12:25:52 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 4/7] dt-bindings: arm-smmu: Add binding for SDX65 SMMU Date: Mon, 11 Apr 2022 12:25:40 +0530 Message-Id: <1649660143-22400-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add devicetree binding for Qualcomm SDX65 SMMU. Signed-off-by: Rohit Agarwal --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index da5381c..1f99bff 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -39,6 +39,7 @@ properties: - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 + - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 From patchwork Mon Apr 11 06:55:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12808551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFBD8C433F5 for ; Mon, 11 Apr 2022 06:56:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245107AbiDKG6Z (ORCPT ); Mon, 11 Apr 2022 02:58:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236475AbiDKG6Z (ORCPT ); Mon, 11 Apr 2022 02:58:25 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 929CA2A25E; Sun, 10 Apr 2022 23:56:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660171; x=1681196171; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=SPn7rGfpCdKX5BixSOyXy7nTS1C2Ef91VXqrhvWkrS4=; b=bifZ/ONFdc8+Kw/P+M4RC3weZByYW/1FoZLoLTgYYM3wHcwkh1GifZ9f K2j3H7MpXuj4Nbdod6LoU6WXyVyz2TxCZ+ytkbmY5igwM/8eqpMBaGJr0 N2r2ZumcnvznHOzPalae9XhQeB/KEoHJ7incWdSVWNiBRDZaBzNKmGI29 o=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:11 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:09 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:54 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 4B7773A9B; Mon, 11 Apr 2022 12:25:53 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Date: Mon, 11 Apr 2022 12:25:41 +0530 Message-Id: <1649660143-22400-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a node for the ARM SMMU found in the SDX65. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 632ac78..2481769 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -181,6 +181,46 @@ status = "disabled"; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>; From patchwork Mon Apr 11 06:55:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12808553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A62EC433F5 for ; Mon, 11 Apr 2022 06:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245134AbiDKG6b (ORCPT ); Mon, 11 Apr 2022 02:58:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245122AbiDKG62 (ORCPT ); Mon, 11 Apr 2022 02:58:28 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 571E02AC5E; Sun, 10 Apr 2022 23:56:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660175; x=1681196175; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=aN1KTb9hnCejWsZRGrTW4ZKJH2xj1O2qH1Fk8k6TrPM=; b=tsDaj+T5zwaIP7y7YGtIja/Ph339sB1jWuYRLwMKCgvFpcbVcOZGr+Lp L39BJhBRCL/3Z3xMq47GcuYX/45ytEsAUZklVWapO1kPy/dPWxgbqRLkB NGt5lJnZWSfKXbdRj/QEJ/PkGEgMcufwxqDk3hiiXNsdNXi7mG5uA7Jtt s=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:15 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:13 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:55 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 3E1BF37D9; Mon, 11 Apr 2022 12:25:54 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Date: Mon, 11 Apr 2022 12:25:42 +0530 Message-Id: <1649660143-22400-7-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 2481769..5c28c94 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -168,6 +168,12 @@ #interrupt-cells = <2>; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; From patchwork Mon Apr 11 06:55:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12808558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E371C433F5 for ; Mon, 11 Apr 2022 06:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245153AbiDKG6l (ORCPT ); Mon, 11 Apr 2022 02:58:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245133AbiDKG6c (ORCPT ); Mon, 11 Apr 2022 02:58:32 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA322AE11; Sun, 10 Apr 2022 23:56:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660178; x=1681196178; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=nQG1bLVYjKXaO4pl95NzaFxrNoh/8TEGG6qEbyOTkeU=; b=UZ2188xMzVQ3L418NYl8rzAIf9jPqfRFsq6IVNTwNZj3t/g6J0o3oUR7 kJCLyrJPuOGDP2T5hBq11+/M56mhWUhnYkGjJ1feCS9M7Yxii4Z6tSivN wm50G1GdIR0miqdf6R38ALnaldw2aiA/WvvHlZFpwvnTLulBA/Z/sj8vP o=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:17 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:16 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:55 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id DCADE3A9B; Mon, 11 Apr 2022 12:25:54 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 7/7] ARM: dts: qcom: sdx65: Add Shared memory manager support Date: Mon, 11 Apr 2022 12:25:43 +0530 Message-Id: <1649660143-22400-8-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add smem node to support shared memory manager on SDX65 platform. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 5c28c94..b0eec91 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -174,6 +174,12 @@ #hwlock-cells = <1>; }; + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>;