From patchwork Mon Apr 11 17:28:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 12809468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EA5EC433F5 for ; Mon, 11 Apr 2022 17:28:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id C3F75C385A4; Mon, 11 Apr 2022 17:28:52 +0000 (UTC) Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 56BA4C385A3 for ; Mon, 11 Apr 2022 17:28:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 56BA4C385A3 Authentication-Results: smtp.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.kernel.org; spf=fail smtp.mailfrom=broadcom.com Received: by mail-pl1-f177.google.com with SMTP id s10so6933996plg.9 for ; Mon, 11 Apr 2022 10:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LTXw5BX/UmLXxE/RpLtiTphfUFT81VmSFPHgQOf8Z/o=; b=H0ywk/tpMKYL7CyGtE6Ld65piieEjiy1iAAeWXV9d8WStXK/tWviPrZHeBKRQ3ldxY BjeCj0WTXuyqQDWj8SCvjF+HOO7c97hMmLrQD4tpaJGg7Yt5XMs+8rchAhfYSh/+Uf/c LvqBUYh4iRvsITzGV2lguZETITiLAUvD50InY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LTXw5BX/UmLXxE/RpLtiTphfUFT81VmSFPHgQOf8Z/o=; b=JjG3llRatiCL1sLd3RXJpQA71L7YU+Oq4q6cQWUz6hcErQm7G/jyTz7DGW3u5lQpbV 0uP+YV3FqQMux11ssqDgjx6epBLGTovbHN34Hc58O7mTqcNfL+3VJcyREEZGmDRAuTF4 2dhrf3N2CEXHGyd3oYtHZvRKczLzSKtI41DOasMVU/emLvrhwX+rhbgnrJKzgBl/zxnG FKkyVYB2Uf+KD8qdqfHaxtIvDxbsiYTGYglhscCh1I4P1+QTPj/ZdQNhmQtp0PsAN49S DzrJe2ZjR3ApEMZQs500aHfuqZaOltLOw56I1rrdHiF7r7WFCxaNZrO02HxdmmHKjtL3 psyw== X-Gm-Message-State: AOAM532sDma12Zne0fJi3oyfQt1GLlZ5BBq/dY62S1DylFFSYH/+u0qU fAVezzGPq00v+Qi7IIo6+CMShCzJwmdONg== X-Google-Smtp-Source: ABdhPJwR8EU+eQ73Sdbwj3pypko1N1dlMZZStQcmYURY8FTdsPOxXEX18C6WQjs3hzVYiFZ1xNsUAg== X-Received: by 2002:a17:90a:c58b:b0:1cb:64f5:131c with SMTP id l11-20020a17090ac58b00b001cb64f5131cmr270856pjt.204.1649698130751; Mon, 11 Apr 2022 10:28:50 -0700 (PDT) Received: from T3500-3.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id d23-20020a17090a02d700b001bf6ef9daafsm85428pjd.38.2022.04.11.10.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 10:28:49 -0700 (PDT) From: William Zhang To: Broadcom Kernel List List-Id: Cc: Samyon Furman , Joel Peshkin , Florian Fainelli , Dan Beygelman , Tomer Yacoby , Anand Gore , Kursad Oney , William Zhang , Arnd Bergmann , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH 3/5] ARM: dts: add dts files for bcmbca soc 47622 Date: Mon, 11 Apr 2022 10:28:13 -0700 Message-Id: <20220411172815.20916-4-william.zhang@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220411172815.20916-1-william.zhang@broadcom.com> References: <20220411172815.20916-1-william.zhang@broadcom.com> Add dts for ARMv7 based broadband SoC BCM47622. bcm47622.dtsi is the SoC description dts header and bcm947622.dts is a simple dts file for Broadcom BCM947622 Reference board that only enable the UART port. Signed-off-by: William Zhang --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm47622.dtsi | 126 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm947622.dts | 30 ++++++++ 3 files changed, 158 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47622.dtsi create mode 100644 arch/arm/boot/dts/bcm947622.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..ff0054d55590 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -179,6 +179,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2q-marvell-dmp.dtb dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi new file mode 100644 index 000000000000..b41116dbfa6a --- /dev/null +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm47622"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x818000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + periph-bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts new file mode 100644 index 000000000000..6f083724ab8e --- /dev/null +++ b/arch/arm/boot/dts/bcm947622.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm47622.dtsi" + +/ { + model = "Broadcom BCM947622 Reference Board"; + compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};