From patchwork Mon Apr 11 18:45:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12809487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC282C433FE for ; Mon, 11 Apr 2022 18:46:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349235AbiDKSsb (ORCPT ); Mon, 11 Apr 2022 14:48:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349224AbiDKSs3 (ORCPT ); Mon, 11 Apr 2022 14:48:29 -0400 Received: from mail.tkos.co.il (guitar.tkos.co.il [84.110.109.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFD871BEA1 for ; Mon, 11 Apr 2022 11:46:13 -0700 (PDT) Received: from tarshish.tkos.co.il (unknown [10.0.8.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.tkos.co.il (Postfix) with ESMTPS id 62411440850; Mon, 11 Apr 2022 21:45:39 +0300 (IDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1649702739; bh=A46Vf+O4fgj2Kf0M0kC0BdmGePrGz2TiFZvx75W3cnA=; h=From:To:Cc:Subject:Date:From; b=N2g2iTk0YcZJ/fbTR48Cllipjd9yWh5Z2VbR7YoraOYNZokky2pSj5r5/AGYd+xbx oHWY87iNCDMm8Kec2KLrigF3pKvbN6zGq1zixtwjamXAL7wFEuEeJVjUUJn9ksGnff xbIoCYUmdXr118yy3HOHPjqMWb5xko7sPOG86P1rtV8kQro2HZ0P7WzmWzJYL5lN6c sAh0327dKc9JrZuLFeAw6+6sz+AfvUQjwRtvSbfkQWwt0XBiF9Lv7B6mO3QpMNW47A q3AVtybBpE9oh+qVf4b1nlOYybBWV4uJ7RGrjNCrJUAmQO4bibd21CuEYcqRDVEWrp igLKj0tcHNpDA== From: Baruch Siach To: Mark Brown Cc: Baruch Siach , linux-spi@vger.kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Date: Mon, 11 Apr 2022 21:45:27 +0300 Message-Id: X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Baruch Siach Some SPI devices latch MOSI bits on one clock phase, but produce valid MISO bits on the other phase. Add SPI_RX_CPHA_FLIP mode to instruct the controller driver to flip CPHA for Rx (MISO) only transfers. Signed-off-by: Baruch Siach --- include/uapi/linux/spi/spi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/spi/spi.h b/include/uapi/linux/spi/spi.h index 236a85f08ded..9d5f58059703 100644 --- a/include/uapi/linux/spi/spi.h +++ b/include/uapi/linux/spi/spi.h @@ -27,6 +27,7 @@ #define SPI_TX_OCTAL _BITUL(13) /* transmit with 8 wires */ #define SPI_RX_OCTAL _BITUL(14) /* receive with 8 wires */ #define SPI_3WIRE_HIZ _BITUL(15) /* high impedance turnaround */ +#define SPI_RX_CPHA_FLIP _BITUL(16) /* flip CPHA on Rx only xfer */ /* * All the bits defined above should be covered by SPI_MODE_USER_MASK. @@ -36,6 +37,6 @@ * These bits must not overlap. A static assert check should make sure of that. * If adding extra bits, make sure to increase the bit index below as well. */ -#define SPI_MODE_USER_MASK (_BITUL(16) - 1) +#define SPI_MODE_USER_MASK (_BITUL(17) - 1) #endif /* _UAPI_SPI_H */ From patchwork Mon Apr 11 18:45:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12809486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 254BAC433EF for ; Mon, 11 Apr 2022 18:46:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345246AbiDKSsb (ORCPT ); Mon, 11 Apr 2022 14:48:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235803AbiDKSs3 (ORCPT ); Mon, 11 Apr 2022 14:48:29 -0400 Received: from mail.tkos.co.il (guitar.tkos.co.il [84.110.109.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C517B1FCDB for ; Mon, 11 Apr 2022 11:46:13 -0700 (PDT) Received: from tarshish.tkos.co.il (unknown [10.0.8.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.tkos.co.il (Postfix) with ESMTPS id E4910440871; Mon, 11 Apr 2022 21:45:39 +0300 (IDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1649702740; bh=MEOSG85g2flAtn4jfkWx1n0E434b5qbnpSikVvx4Ey4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ggKBNpTY8yeIEbIjwa0+Jgv0UwqtpzgIutbvnQN6S/BpPIOzXmxCHiFr/1DjlILYc 58x4oCKI1VAq3T75FehJN+rslpGWdzV4u4QOWyA10vQ9iQN52K3ROtoyb3NA+GmNka aHasahmVS7h/7waE9Dwc1rGkd27MFQVwdmzmjRoq4I/1divqCsRpIIXlEndueoIuGI KiRG0J6AaEb9a8HeXsDtiPzhqO7H+COVQMTb3gLH9gIV/Svr9O547ejS78oIXuTzwt RIZ20lKd7yZk7m+20Bp4cit5dN3ZtFk7XxzgKCZQ0526J5zvrpYfj3V90nuvE2JR/E b2vLDO+QIxS5w== From: Baruch Siach To: Mark Brown Cc: Baruch Siach , linux-spi@vger.kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] spi: spidev: add SPI_RX_CPHA_FLIP Date: Mon, 11 Apr 2022 21:45:28 +0300 Message-Id: <6ae31ad24f8252418878b21a8759a04b78726dac.1649702729.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Baruch Siach Allow userspace to set SPI_RX_CPHA_FLIP mode bit using the SPI_IOC_WR_MODE32 ioctl. Signed-off-by: Baruch Siach --- drivers/spi/spidev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 968dab2f5e3d..ff1a959fb30f 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -63,7 +63,8 @@ static DECLARE_BITMAP(minors, N_SPI_MINORS); | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ | SPI_NO_CS | SPI_READY | SPI_TX_DUAL \ | SPI_TX_QUAD | SPI_TX_OCTAL | SPI_RX_DUAL \ - | SPI_RX_QUAD | SPI_RX_OCTAL) + | SPI_RX_QUAD | SPI_RX_OCTAL \ + | SPI_RX_CPHA_FLIP) struct spidev_data { dev_t devt; From patchwork Mon Apr 11 18:45:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12809485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A70F8C433F5 for ; Mon, 11 Apr 2022 18:46:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234834AbiDKSsb (ORCPT ); Mon, 11 Apr 2022 14:48:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345246AbiDKSs3 (ORCPT ); Mon, 11 Apr 2022 14:48:29 -0400 Received: from mail.tkos.co.il (golan.tkos.co.il [84.110.109.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4818038AB for ; Mon, 11 Apr 2022 11:46:14 -0700 (PDT) Received: from tarshish.tkos.co.il (unknown [10.0.8.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.tkos.co.il (Postfix) with ESMTPS id A9CE24409C6; Mon, 11 Apr 2022 21:45:40 +0300 (IDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1649702741; bh=a4PADMrOZphilip+jA6MTxHROEeyp5oVgUJ7MCvUAS4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NaZsMfHeMXLbihLO1EmoNfCKIUUUZDB/zm/eP8P184sWg2yb26dw1V6nMk6Ss1s9l A920WuOfub+DeIX7vldOhogbQ7dDMNaTdg9CnZzdzjerzgmp+/IVzBJ55aS2o3yOEH /9YLhvJH/D6oEh7wi4Ddcl0P1UsR4Eoz4g9V2OjTCsGLLNCJeQTFvVhzPNiRl+ZSOF q/KJrNPSpJwPpdgl+eAlbIR4wK3K3mEcpK8/nqjiylleolZoA5QxgQN/xjdnLwTupz NJEIo+UMFN4HmmdU2k5PkP6oBxlIdXYpsvTGRugqeTL3SQSzOeT/Y8Q/XhOINPxIU9 DVWn2509nIoeg== From: Baruch Siach To: Mark Brown Cc: Baruch Siach , linux-spi@vger.kernel.org, Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] spi: spi-imx: add support for SPI_RX_CPHA_FLIP Date: Mon, 11 Apr 2022 21:45:29 +0300 Message-Id: X-Mailer: git-send-email 2.35.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Baruch Siach When SPI_RX_CPHA_FLIP is set, flip CPHA on Rx only transfers. This is useful to access devices that use inverted CPHA for MISO vs MOSI signals. Only support the mx51/mx53 variants for now. Tested on i.MX6ULL based system. Signed-off-by: Baruch Siach --- drivers/spi/spi-imx.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index b2dd0a4d2446..4e1bfe2f043a 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -108,6 +108,7 @@ struct spi_imx_data { const void *tx_buf; unsigned int txfifo; /* number of words pushed in tx FIFO */ unsigned int dynamic_burst; + bool rx_only; /* Slave mode */ bool slave_mode; @@ -554,11 +555,6 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, else cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); - if (spi->mode & SPI_CPHA) - cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); - else - cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); - if (spi->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); @@ -606,6 +602,24 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, return 0; } +static void mx51_configure_cpha(struct spi_imx_data *spi_imx, + struct spi_device *spi) +{ + bool cpha = (spi->mode & SPI_CPHA); + bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; + u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); + + /* Flip cpha logical value iff flip_cpha */ + cpha ^= flip_cpha; + + if (cpha) + cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + else + cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + + writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); +} + static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, struct spi_device *spi) { @@ -627,6 +641,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); spi_imx->spi_bus_clk = clk; + mx51_configure_cpha(spi_imx, spi); + /* * ERR009165: work in XHC mode instead of SMC as PIO on the chips * before i.mx6ul. @@ -1251,6 +1267,9 @@ static int spi_imx_setupxfer(struct spi_device *spi, else spi_imx->usedma = false; + spi_imx->rx_only = ((t->tx_buf == NULL) + || (t->tx_buf == spi->controller->dummy_tx)); + if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { spi_imx->rx = mx53_ecspi_rx_slave; spi_imx->tx = mx53_ecspi_tx_slave; @@ -1655,6 +1674,9 @@ static int spi_imx_probe(struct platform_device *pdev) is_imx53_ecspi(spi_imx)) spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; + if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) + spi_imx->bitbang.master->mode_bits |= SPI_RX_CPHA_FLIP; + if (is_imx51_ecspi(spi_imx) && device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) /*