From patchwork Wed Apr 13 19:26:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 12812508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8825C433EF for ; Wed, 13 Apr 2022 19:27:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 9A36FC385A8; Wed, 13 Apr 2022 19:27:17 +0000 (UTC) Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 6AA38C385A4 for ; Wed, 13 Apr 2022 19:27:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 6AA38C385A4 Authentication-Results: smtp.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.kernel.org; spf=fail smtp.mailfrom=broadcom.com Received: by mail-pl1-f178.google.com with SMTP id s14so2776355plk.8 for ; Wed, 13 Apr 2022 12:27:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yvFa8H0mMTOpjnP0RxGKxwsNyQcGzrjPQCGmX/jCjzg=; b=GKiFAB79FrW+ZY1W4YR5e9e5EGkP4oZyWZtEu71+P1ZJoVdvpUNZeiB1jBKLfpA/t6 Q818orw+f2rOEE/8Hot/+QgPhBp2eMfA2LKpP/IL9nwcwNsvyw0cjfyrWnvyQJi1pv+U lUhTQ44NB/ck8d2ELwU4T4Lvw+2GieEV9pNgY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yvFa8H0mMTOpjnP0RxGKxwsNyQcGzrjPQCGmX/jCjzg=; b=s1sJGYXfyYQq1UdW6snMWqoEbRkZEihbduhokYbBUik4Nv5U6WFicJIbXpogxFMWeG zw7/0nd0Ua4IoOy6P0hhvPn98qyfLI8TpX1CJee+32IqdCApfethbVfr1czmxeVLELMw /3UWVDckJJIYy1yYs3+9L3k3usHJvd3auC8c9NbBmQxDy/EBO045ojasVqpEn+szxT9D 3wVfcuu1asoauLQRu7UCvF7BidVLtJHbrlbznpA074JTD93db02z6l5MsLSWWmSDOckA Kl2+YS6B8kP2XojR4Z5GWF84N2gMdr3793k0L9QNVg03R/YXdD48QjvChPJMh9PkjSz5 Oexg== X-Gm-Message-State: AOAM53172dJ3t4qDBhaVy0mCQMJQPvq67Iz0rTszYJussCDsdG/8apBX NTa6Z+jIiZKiANL2jDas8HPRVg== X-Google-Smtp-Source: ABdhPJzQb0khpocik8a4XS7IQBwyQXlDJ5DkNxubVaeZP4oBZJuwH0YHiX6SU7rDKdlk7nWXZ5DCHQ== X-Received: by 2002:a17:90b:1d04:b0:1c7:b10f:e33d with SMTP id on4-20020a17090b1d0400b001c7b10fe33dmr258845pjb.165.1649878035034; Wed, 13 Apr 2022 12:27:15 -0700 (PDT) Received: from T3500-3.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00505d9277cb3sm8624906pfn.38.2022.04.13.12.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Apr 2022 12:27:14 -0700 (PDT) From: William Zhang To: linux-arm-kernel@lists.infradead.org List-Id: Cc: Broadcom Kernel List , Kursad Oney , Joel Peshkin , Anand Gore , Dan Beygelman , Florian Fainelli , William Zhang , Arnd Bergmann , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH v2 3/5] ARM: dts: add dts files for bcmbca soc 47622 Date: Wed, 13 Apr 2022 12:26:43 -0700 Message-Id: <20220413192645.7067-4-william.zhang@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220413192645.7067-1-william.zhang@broadcom.com> References: <20220413192645.7067-1-william.zhang@broadcom.com> Add dts for ARMv7 based broadband SoC BCM47622. bcm47622.dtsi is the SoC description dts header and bcm947622.dts is a simple dts file for Broadcom BCM947622 Reference board that only enable the UART port. Signed-off-by: William Zhang --- Changes for V2: * Update compatible string and node name in bcm47622.dtsi arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm47622.dtsi | 126 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm947622.dts | 30 ++++++++ 3 files changed, 158 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47622.dtsi create mode 100644 arch/arm/boot/dts/bcm947622.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..ff0054d55590 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -179,6 +179,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2q-marvell-dmp.dtb dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi new file mode 100644 index 000000000000..c016e12b7372 --- /dev/null +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm47622", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x818000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts new file mode 100644 index 000000000000..6f083724ab8e --- /dev/null +++ b/arch/arm/boot/dts/bcm947622.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm47622.dtsi" + +/ { + model = "Broadcom BCM947622 Reference Board"; + compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};