From patchwork Thu Apr 14 09:28:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12813215 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FE0417C2 for ; Thu, 14 Apr 2022 09:28:36 +0000 (UTC) Received: by mail-wr1-f44.google.com with SMTP id b19so6048985wrh.11 for ; Thu, 14 Apr 2022 02:28:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Av8EzP8d6KVoQi/yXwkBOAZabP9Xc8kXclRu9dT4+Lw=; b=XW/DvwVmRs0u+HPVCBNJh0m4E34d8hn5teI5p4MFlw1AwT0QGpyDrvDYKeFL04RmRK jvJG4o7qAJeCTCf9MHamgs4HLvZ9Sp1qgwjYT6HwHxwOr7ayhQgJeTOVefciIbCRRfcN kAIWOaIp3+4P5k1D8vWT9Ug6Fw28yDxDjq/go= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Av8EzP8d6KVoQi/yXwkBOAZabP9Xc8kXclRu9dT4+Lw=; b=vvP9A+zOoojhiAoRwSCWmMWjNp+CMg1oFccN9ZSxWQnkXY0czAuvskl+eJ98KvLcAI /EgDY8jb91lKhkYtNFvgfpa2031moGSLfWQu/k3aeFye44sMTSdX4RqcyBaMEf1C/8Ag MA5ts+z8JhlONsfoxe+w8V+8hZYz1XyvSyFHP/verIrjBZ/TdhTmsGt2uoghmR/D2kjJ ji6qqpHHI6jUx+Kyt8flJqPA5gR4Naw73d/93OkQzvkGo/F9njRe2zGo1Cvl6soTcSbn 6UbiEi6LKlrg8xK4YikFMGu7+31OgPc7O1ZNhzPCu/XBVOLuFH/c37jio4flGTv2tKAs 24eA== X-Gm-Message-State: AOAM530IqdYaNzOFnPdGoqExxTgNv7TACP7XExK+aQVS2UPIi43c3IEC NWMZ1OykMaKAY6M8kCARJpovhA== X-Google-Smtp-Source: ABdhPJwICPNoTiCyXovM+uFrLY1cRUMc9NSi0tZTBQi5obLIMnAkksH5rZ/OUVje2hYRLnI13kqUcw== X-Received: by 2002:adf:d1c7:0:b0:205:dc0e:383a with SMTP id b7-20020adfd1c7000000b00205dc0e383amr1370718wrd.335.1649928514435; Thu, 14 Apr 2022 02:28:34 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id bg8-20020a05600c3c8800b0038e4c5967besm1698099wmb.3.2022.04.14.02.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Apr 2022 02:28:34 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v4 1/4] dt-bindings: add mfd/cros_ec definitions Date: Thu, 14 Apr 2022 09:28:28 +0000 Message-Id: <20220414092831.3717684-2-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220414092831.3717684-1-fabiobaltieri@chromium.org> References: <20220414092831.3717684-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a dt-bindings include file for cros_ec devicetree definition, define a pair of special purpose PWM channels in it. Signed-off-by: Fabio Baltieri Acked-by: Rob Herring --- include/dt-bindings/mfd/cros_ec.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/mfd/cros_ec.h diff --git a/include/dt-bindings/mfd/cros_ec.h b/include/dt-bindings/mfd/cros_ec.h new file mode 100644 index 000000000000..3b29cd049578 --- /dev/null +++ b/include/dt-bindings/mfd/cros_ec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * DTS binding definitions used for the Chromium OS Embedded Controller. + * + * Copyright (c) 2022 The Chromium OS Authors. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MFD_CROS_EC_H +#define _DT_BINDINGS_MFD_CROS_EC_H + +/* Typed channel for keyboard backlight. */ +#define CROS_EC_PWM_DT_KB_LIGHT 0 +/* Typed channel for display backlight. */ +#define CROS_EC_PWM_DT_DISPLAY_LIGHT 1 +/* Number of typed channels. */ +#define CROS_EC_PWM_DT_COUNT 2 + +#endif From patchwork Thu Apr 14 09:28:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12813216 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F08F37B for ; Thu, 14 Apr 2022 09:28:36 +0000 (UTC) Received: by mail-wr1-f41.google.com with SMTP id m14so6080466wrb.6 for ; Thu, 14 Apr 2022 02:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EI3aTLR3kZ/7o/ypPML1uz1j1gkp6fUYT50vDoeqrt8=; b=MCUjT0/lXL5lIjMWgZu0d8wayePTcccWJTZoE7NfAJuSSfDH8EBY7hH0Sf2jXnCfTF oxnWjsCwp43x0K3TOs4kCnYnJsrzymPc0UAN+WwI2brDlmDylUkxVv0YYH94MNr3ljgP lSJQvppPewdLqC3GbQ0t8HbsfOyEZb+YQwjiQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EI3aTLR3kZ/7o/ypPML1uz1j1gkp6fUYT50vDoeqrt8=; b=ZjoL35vvXqUp8uzs7YjNeYpefctjNu/M+R6FQDfyeXrD4ny343+02Hfb4iY0So4Q6w AdrmfycHns9gTaKlrhRepQQkv5rdaYI07fTod2Y2+OBOdxeNN+IWhhl2LHNXNn2ChFOi a4ixiRiqtLYSQRpw2eIPzego2TprmA4Z4QqLVmtECDk3aZHZ2RuMNH/kalNRY1fNvZ/6 RH6MEjIm+tslwo7bvX5yboR9JUfaw3hyW6NbHAyhNEYkYjzOlXF034x3qKwRtfEnAX+j PeB2mmMlFESD0w7+xvh2mqYpycL2ma/bcedW8OdmpnJOpOxCVGA0g/dE+h89sWqlWSBj 1RBA== X-Gm-Message-State: AOAM533ZBSnemue4kawM+SXYNvEJnAHejgMmVAduN3KGpsgMlLGWALqW ZaRXkwOtZJqhCpHlMvymCD01fg== X-Google-Smtp-Source: ABdhPJxKT8AeK9HaPvUrB7RHjH335zMFPNbVP4pvTRWtdYfo2RjwG+KhFSRBarDuueoZrX8Cy0OvYw== X-Received: by 2002:a05:6000:2ac:b0:20a:7732:4bb6 with SMTP id l12-20020a05600002ac00b0020a77324bb6mr198482wry.538.1649928515280; Thu, 14 Apr 2022 02:28:35 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id bg8-20020a05600c3c8800b0038e4c5967besm1698099wmb.3.2022.04.14.02.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Apr 2022 02:28:34 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v4 2/4] pwm: pwm-cros-ec: add channel type support Date: Thu, 14 Apr 2022 09:28:29 +0000 Message-Id: <20220414092831.3717684-3-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220414092831.3717684-1-fabiobaltieri@chromium.org> References: <20220414092831.3717684-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for EC_PWM_TYPE_DISPLAY_LIGHT and EC_PWM_TYPE_KB_LIGHT pwm types to the PWM cros_ec_pwm driver. This allows specifying one of these PWM channel by functionality, and let the EC firmware pick the correct channel, thus abstracting the hardware implementation from the kernel driver. To use it, define the node with the "google,cros-ec-pwm-type" compatible. Signed-off-by: Fabio Baltieri Reviewed-by: Tzung-Bi Shih --- drivers/pwm/pwm-cros-ec.c | 82 ++++++++++++++++++++++++++++++++------- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 5e29d9c682c3..7f10f56c3eb6 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -12,17 +12,21 @@ #include #include +#include + /** * struct cros_ec_pwm_device - Driver data for EC PWM * * @dev: Device node * @ec: Pointer to EC device * @chip: PWM controller chip + * @use_pwm_type: Use PWM types instead of generic channels */ struct cros_ec_pwm_device { struct device *dev; struct cros_ec_device *ec; struct pwm_chip chip; + bool use_pwm_type; }; /** @@ -58,14 +62,31 @@ static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) kfree(channel); } -static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) +static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type) { + switch (dt_index) { + case CROS_EC_PWM_DT_KB_LIGHT: + *pwm_type = EC_PWM_TYPE_KB_LIGHT; + return 0; + case CROS_EC_PWM_DT_DISPLAY_LIGHT: + *pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT; + return 0; + default: + return -EINVAL; + } +} + +static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index, + u16 duty) +{ + struct cros_ec_device *ec = ec_pwm->ec; struct { struct cros_ec_command msg; struct ec_params_pwm_set_duty params; } __packed buf; struct ec_params_pwm_set_duty *params = &buf.params; struct cros_ec_command *msg = &buf.msg; + int ret; memset(&buf, 0, sizeof(buf)); @@ -75,14 +96,25 @@ static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty) msg->outsize = sizeof(*params); params->duty = duty; - params->pwm_type = EC_PWM_TYPE_GENERIC; - params->index = index; + + if (ec_pwm->use_pwm_type) { + ret = cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index = 0; + } else { + params->pwm_type = EC_PWM_TYPE_GENERIC; + params->index = index; + } return cros_ec_cmd_xfer_status(ec, msg); } -static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) +static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 index) { + struct cros_ec_device *ec = ec_pwm->ec; struct { struct cros_ec_command msg; union { @@ -102,8 +134,17 @@ static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index) msg->insize = sizeof(*resp); msg->outsize = sizeof(*params); - params->pwm_type = EC_PWM_TYPE_GENERIC; - params->index = index; + if (ec_pwm->use_pwm_type) { + ret = cros_ec_dt_type_to_pwm_type(index, ¶ms->pwm_type); + if (ret) { + dev_err(ec->dev, "Invalid PWM type index: %d\n", index); + return ret; + } + params->index = 0; + } else { + params->pwm_type = EC_PWM_TYPE_GENERIC; + params->index = index; + } ret = cros_ec_cmd_xfer_status(ec, msg); if (ret < 0) @@ -133,7 +174,7 @@ static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, */ duty_cycle = state->enabled ? state->duty_cycle : 0; - ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle); + ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle); if (ret < 0) return ret; @@ -149,7 +190,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct cros_ec_pwm *channel = pwm_get_chip_data(pwm); int ret; - ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm); + ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm); if (ret < 0) { dev_err(chip->dev, "error getting initial duty: %d\n", ret); return; @@ -204,13 +245,13 @@ static const struct pwm_ops cros_ec_pwm_ops = { * of PWMs it supports directly, so we have to read the pwm duty cycle for * subsequent channels until we get an error. */ -static int cros_ec_num_pwms(struct cros_ec_device *ec) +static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm) { int i, ret; /* The index field is only 8 bits */ for (i = 0; i <= U8_MAX; i++) { - ret = cros_ec_pwm_get_duty(ec, i); + ret = cros_ec_pwm_get_duty(ec_pwm, i); /* * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM * responses; everything else is treated as an error. @@ -236,6 +277,7 @@ static int cros_ec_pwm_probe(struct platform_device *pdev) { struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent); struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; struct cros_ec_pwm_device *ec_pwm; struct pwm_chip *chip; int ret; @@ -251,17 +293,26 @@ static int cros_ec_pwm_probe(struct platform_device *pdev) chip = &ec_pwm->chip; ec_pwm->ec = ec; + if (of_device_is_compatible(np, "google,cros-ec-pwm-type")) + ec_pwm->use_pwm_type = true; + /* PWM chip */ chip->dev = dev; chip->ops = &cros_ec_pwm_ops; chip->of_xlate = cros_ec_pwm_xlate; chip->of_pwm_n_cells = 1; - ret = cros_ec_num_pwms(ec); - if (ret < 0) { - dev_err(dev, "Couldn't find PWMs: %d\n", ret); - return ret; + + if (ec_pwm->use_pwm_type) { + chip->npwm = CROS_EC_PWM_DT_COUNT; + } else { + ret = cros_ec_num_pwms(ec_pwm); + if (ret < 0) { + dev_err(dev, "Couldn't find PWMs: %d\n", ret); + return ret; + } + chip->npwm = ret; } - chip->npwm = ret; + dev_dbg(dev, "Probed %u PWMs\n", chip->npwm); ret = pwmchip_add(chip); @@ -288,6 +339,7 @@ static int cros_ec_pwm_remove(struct platform_device *dev) #ifdef CONFIG_OF static const struct of_device_id cros_ec_pwm_of_match[] = { { .compatible = "google,cros-ec-pwm" }, + { .compatible = "google,cros-ec-pwm-type" }, {}, }; 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Thu, 14 Apr 2022 02:28:35 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v4 3/4] dt-bindings: update google,cros-ec-pwm documentation Date: Thu, 14 Apr 2022 09:28:30 +0000 Message-Id: <20220414092831.3717684-4-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220414092831.3717684-1-fabiobaltieri@chromium.org> References: <20220414092831.3717684-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update google,cros-ec-pwm node documentation to mention the google,cros-ec-pwm-type compatible. Signed-off-by: Fabio Baltieri --- .../devicetree/bindings/pwm/google,cros-ec-pwm.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 7ab6912a845f..deb9e4488773 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -21,7 +21,14 @@ allOf: properties: compatible: - const: google,cros-ec-pwm + oneOf: + - description: PWM controlled using EC_PWM_TYPE_GENERIC channels. + items: + - const: google,cros-ec-pwm + - description: PWM controlled using CROS_EC_PWM_DT_<...> types. + items: + - const: google,cros-ec-pwm-type + "#pwm-cells": description: The cell specifies the PWM index. const: 1 From patchwork Thu Apr 14 09:28:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Baltieri X-Patchwork-Id: 12813218 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82BB717C3 for ; Thu, 14 Apr 2022 09:28:38 +0000 (UTC) Received: by mail-wr1-f41.google.com with SMTP id t1so6084081wra.4 for ; Thu, 14 Apr 2022 02:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UBu9bKNpcsjBxVmcDi5TeRQJe5h4mzqRMvKt6Hs6yfk=; b=Vewj5Dz7RSg+PeiaWemyvRfbGJIw6goI02YIUIlexhdopKGfuz5QFxWlU/cRgzOEMQ xe4qzReYV1rdCqIdlEwfz8aURRc2+/ASmpJOzJV5zpHGv3JwVlzxiTjxTrcd9QzSqdv8 Zrr/R2ylnxbeTnZ3QFqDHi8umJN4S7DQCp8Io= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UBu9bKNpcsjBxVmcDi5TeRQJe5h4mzqRMvKt6Hs6yfk=; b=erRtJ4sZBHHQk7Z02RCw9IdW4EiDn5f6KV/Ln1EBA75Znei0beKh5783I7K6hduSp2 V7DB/bMQDZkKPh1//luCjK4rch0zL1l5KDs+CflnzU2D6477PhF6oyljC2HhdimrQ4Pb Rmc0YBlogrI2d01WerxX59yR2zneY64jyRfv/bdqGN5qOQGr4C2Bz69VhGOqjGnvTrd+ KTf2UX5bVTNg9iT09CvLaZb2bI+StVmglrbKCEoqIu9iDtHjj8wySlZie1ajN6LJjEtS m7DHWOMm0L8XF3OR7M/xVowaUS92hZWhSRItS85MzCvaNTQ408+Um7CoClatt412WM8k jwzQ== X-Gm-Message-State: AOAM5335g9f+df3i6j5jo0A8n95GVX3hiMPT31esReDrdiQE3lRiyGca GQNXb3LQnNB/wxXfSA+jfbbAOg== X-Google-Smtp-Source: ABdhPJzkPWbyQ3uEjfLiHNYske8Ws1jqaNiWmEv6M26tsYDiZ4KBw96HdYn2xvcVVHlNlUsXbquqjA== X-Received: by 2002:a05:6000:1445:b0:204:1ca1:67b0 with SMTP id v5-20020a056000144500b002041ca167b0mr1376719wrx.507.1649928516912; Thu, 14 Apr 2022 02:28:36 -0700 (PDT) Received: from fabiobaltieri-linux.lan ([37.228.205.1]) by smtp.gmail.com with ESMTPSA id bg8-20020a05600c3c8800b0038e4c5967besm1698099wmb.3.2022.04.14.02.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Apr 2022 02:28:36 -0700 (PDT) From: Fabio Baltieri To: Benson Leung , Guenter Roeck Cc: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Rob Herring , chrome-platform@lists.linux.dev, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabio Baltieri Subject: [PATCH v4 4/4] arm64: dts: address cros-ec-pwm channels by type Date: Thu, 14 Apr 2022 09:28:31 +0000 Message-Id: <20220414092831.3717684-5-fabiobaltieri@chromium.org> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog In-Reply-To: <20220414092831.3717684-1-fabiobaltieri@chromium.org> References: <20220414092831.3717684-1-fabiobaltieri@chromium.org> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update various cros-ec-pwm board definitions to address the keyboard and screen backlight PWM channels by type rather than channel number. This makes the instance independent by the actual hardware configuration, relying on the EC firmware to pick the right channel, and allows dropping few dtsi overrides as a consequence. Changed the node label used to cros_ec_pwm_type to avoid ambiguity about the pwm cell meaning. Signed-off-by: Fabio Baltieri --- .../dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 9 +++++---- .../boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts | 7 ++++--- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 7 ++++--- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 7 ++++--- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 5 +++-- arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 13 files changed, 28 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index dec11a4eb59e..e2554a313deb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -15,13 +15,13 @@ pwmleds { compatible = "pwm-leds"; keyboard_backlight: keyboard-backlight { label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; }; -&cros_ec_pwm { +&cros_ec_pwm_type { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..8474bd3af6eb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,8 +92,8 @@ volume_up { }; &cros_ec { - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; + cros_ec_pwm_type: ec-pwm { + compatible = "google,cros-ec-pwm-type"; #pwm-cells = <1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..ff54687ab8bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include "mt8183.dtsi" #include "mt6358.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index c81805ef2250..aea7c66d95e0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -77,10 +77,6 @@ &ap_spi_fp { status = "okay"; }; -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - &camcc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 732e1181af48..6552e0025f84 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -316,7 +317,7 @@ backlight: backlight { num-interpolated-steps = <64>; default-brightness-level = <951>; - pwms = <&cros_ec_pwm 1>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; pinctrl-names = "default"; @@ -354,7 +355,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -637,8 +638,8 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible = "google,cros-ec-pwm-type"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts index 1779d96c30f6..628ef990433b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -336,7 +337,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -705,8 +706,8 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible = "google,cros-ec-pwm-type"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index dc17f2079695..eb4b0e17adec 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -15,6 +15,7 @@ #include #include +#include #include "sc7280-qcard.dtsi" #include "sc7280-chrome-common.dtsi" @@ -288,7 +289,7 @@ pwmleds { keyboard_backlight: keyboard-backlight { status = "disabled"; label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_KB_LIGHT>; max-brightness = <1023>; }; }; @@ -421,8 +422,8 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible = "google,cros-ec-pwm-type"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index a7c346aa3b02..a797f09e1328 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,8 +20,8 @@ cros_ec: ec@0 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible = "google,cros-ec-pwm-type"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index e7e4cc5936aa..a57951a50cd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include "sdm845.dtsi" @@ -27,7 +28,7 @@ chosen { backlight: backlight { compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 0>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; pinctrl-names = "default"; @@ -708,8 +709,8 @@ cros_ec: ec@0 { pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible = "google,cros-ec-pwm-type"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts index 31ebb4e5fd33..5a076c2564f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -55,10 +55,6 @@ trackpad: trackpad@15 { }; }; -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - &cpu_alert0 { temperature = <65000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3355fb90fa54..28eda361dfe1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -198,6 +198,7 @@ backlight: backlight { power-supply = <&pp3300_disp>; pinctrl-names = "default"; pinctrl-0 = <&bl_en>; + pwms = <&cros_ec_pwm_type CROS_EC_PWM_DT_DISPLAY_LIGHT>; pwm-delay-us = <10000>; }; @@ -462,8 +463,8 @@ ap_i2c_tp: &i2c5 { }; &cros_ec { - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; + cros_ec_pwm_type: pwm { + compatible = "google,cros-ec-pwm-type"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 6863689df06f..e959a33af34b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -84,10 +84,6 @@ thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { }; }; -&backlight { - pwms = <&cros_ec_pwm 1>; -}; - &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..181159e9982d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include "rk3399.dtsi" #include "rk3399-op1-opp.dtsi"