From patchwork Sat Apr 16 02:56:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51C54C433FE for ; Sat, 16 Apr 2022 02:58:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229564AbiDPDBP (ORCPT ); Fri, 15 Apr 2022 23:01:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229481AbiDPDBO (ORCPT ); Fri, 15 Apr 2022 23:01:14 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C95FAD5F; Fri, 15 Apr 2022 19:58:43 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id l7so18201639ejn.2; Fri, 15 Apr 2022 19:58:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wE2qr/C8N+SeuPWgY5wjdcTD2YKeg4j65dO9v6FVK7Y=; b=F2OCCcu3Yi32pKmSFOO3YQMmNVlG5afuE4ct5KM138pnkmOvqblMU1YcxFs9oIK+tp gc/ERhzbuuEdM6N9kbj2z7S1Iye0NOZ9Iyp1O+nnPPah9/ULjQJp22dkzeA/lTEUsl/T 5LYqsL1+EwQcNhvtQteq+zi2PhjZewuAqji/zJnwlD8dgmNyOLsAoA+s26JwnRXSHLIF 8jO+wKXO6P+D+fG/Q0CEmQD8wSlNjNPOANdCTFyFF6JrFZC+RkodGU1bQ+hiNqr9//7i bXb2fZ+KVZXfC64/g4J0ON3nF1k1l9utTTkEhdyQHUjxhyDt7nZIyxncAAJQRUfaLv9F /1Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wE2qr/C8N+SeuPWgY5wjdcTD2YKeg4j65dO9v6FVK7Y=; b=VKO7UzPa93b0Vz+ml8khpqvYUkLiprG5w9QFJxlkvfYQIYQ1GieoxAXcA+dBXxg/2L vQrYrbMiujeFUiCGFEFoH8th80c7J1PWMI3CaKwpYWYeVK2JX8kI7AGnPX8oLZlat8dm VkCdH3HdYHdEEmaX6YrYLe0/e0DMGB4+ptGdXXNcXDkt4GDKys2PdJOVwZ1Qu4r7of4z bLUJfq17Vj8VFvZAavOjgL+iz2lLXPc00jSSN3SXcbhso57AuNP0AMp5eswcsD+pEX5H OOa1vG6rJZWG8/x5iXH02kc/eeKbLpSGpQNTSXiDXWAED/X2EOZqLi4mXkLdYexIU8qa HMDQ== X-Gm-Message-State: AOAM532DomeUkkIK6MKLbGfNziG1rdzA6slRZ17um4nIIrHdQSpaqEHO KuCWYQ7zuOzPS06rATeKngI= X-Google-Smtp-Source: ABdhPJzThm+IKN3OnfUcJODiRHKCu9nM57rh4M5CWwJCIslIanwO9Qk/DcwrnuTAQZ4Xerkf2RTi6A== X-Received: by 2002:a17:907:97cf:b0:6df:846f:ad0a with SMTP id js15-20020a17090797cf00b006df846fad0amr1374427ejc.286.1650077922295; Fri, 15 Apr 2022 19:58:42 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.159]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006e872188edbsm2200915ejb.104.2022.04.15.19.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 19:58:42 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana , Rob Herring Subject: [PATCH RESEND v2 1/9] dt-bindings: clk: qcom: msm8996-apcc: Add CBF Date: Sat, 16 Apr 2022 06:56:29 +0400 Message-Id: <20220416025637.83484-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add CBF clock and reg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- .../devicetree/bindings/clock/qcom,msm8996-apcc.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml index a20cb10636dd..325f8aef53b2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -10,8 +10,8 @@ maintainers: - Loic Poulain description: | - Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster - and clock 1 is for Perf cluster. + Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster, + clock 1 is for Perf cluster, and clock 2 is for Coherent bus fabric (CBF). properties: compatible: @@ -19,7 +19,9 @@ properties: - qcom,msm8996-apcc reg: - maxItems: 1 + items: + - description: Cluster clock registers + - description: CBF clock registers '#clock-cells': const: 1 @@ -49,6 +51,6 @@ examples: - | kryocc: clock-controller@6400000 { compatible = "qcom,msm8996-apcc"; - reg = <0x6400000 0x90000>; + reg = <0x6400000 0x90000>, <0x09a11000 0x10000>; #clock-cells = <1>; }; From patchwork Sat Apr 16 02:56:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4672AC433EF for ; Sat, 16 Apr 2022 02:58:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229481AbiDPDBX (ORCPT ); Fri, 15 Apr 2022 23:01:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229621AbiDPDBS (ORCPT ); Fri, 15 Apr 2022 23:01:18 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CC215B3C6; Fri, 15 Apr 2022 19:58:47 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id s18so18255400ejr.0; Fri, 15 Apr 2022 19:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cKj4GsjkvCLxphsJLv+6Hci1YlI8gLSSD4ZLBL6UMd0=; b=SVa9E9Xy76r8k25gbN8Q/LINPOLriAA1UsCaTPjz7ZbH3Jatqtea/kE9HQ8OPEwTc+ nDxGkPKJkxRAqjDbn0rIFAfT4/ZmPoOdfqms+o7MG7ywExI6TBF/Fm4NW8U9mNRL1wfe NQAoScYa4dXp1KzbTY7RQNAxAakOdB67YWS+u4W8d1AjJPbjiydZl/LnQT4s0aNR9jSt wGB9cJihRCZOFi/TJT1oH1EmBEvwsuClaWNHaLoRwJ5z1xZtJXDE81zUUyIhdZ2fCsBv 9+fYMLXotuTtdVZuDA99UgpdYLok4JY435S6JO2hMMOOFmWqslGTN8GA6lSquCh9oR5q tfGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cKj4GsjkvCLxphsJLv+6Hci1YlI8gLSSD4ZLBL6UMd0=; b=LKYRqyC+tWpYWqFELKfHBumtAbOg3L7HmKHOUU0u4S+EpoMG+GGNq1bVFga0++m+lY OlY/GJBG/f/OwDEPEUzIdbhoaNrQL31JKNI8IcsFXWrvMQ6CEqF1Tc1jVSzW/vyvHntT th5KmCk4y4KrpWib5v/5L5Lu1TNsit6MIP6D8e6syMdzTFA9JmZ1oTAo6Wenjxu6WXvW pPohSLyBK5W2SDx34uXupSMpDG0FlJZZ2igumHy9+S+f41HgNJfOJ6umJlnnQLlTm0ld cZxPF6+TadY7PA0zaXI3iS049hu0suP4axdvy0l/UFiJGSteLyQ41NX/MsBG5pI3VQRt KCdg== X-Gm-Message-State: AOAM531PkyDhA2BXhI5y9MtgUDJCQu8f73KWkcrmR6HlyxpyrtUOeNNZ ZhTMcQyCx/v02awa2b+SjGw= X-Google-Smtp-Source: ABdhPJwzNioJqGCDFqkl0SU3Yb9EiGQefjo9Uq/jObUZx9M+SnNfIcEm2CeIHmhMTjw7D6wfwllhKQ== X-Received: by 2002:a17:907:3f10:b0:6da:818d:4525 with SMTP id hq16-20020a1709073f1000b006da818d4525mr1307011ejc.47.1650077925985; Fri, 15 Apr 2022 19:58:45 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.159]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006e872188edbsm2200915ejb.104.2022.04.15.19.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 19:58:45 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana , Rob Herring Subject: [PATCH RESEND v2 2/9] dt-bindings: clk: qcom: msm8996-apcc: Add MSM8996 Pro compatible Date: Sat, 16 Apr 2022 06:56:30 +0400 Message-Id: <20220416025637.83484-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a compatible string for msm8996pro-apcc. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml index 325f8aef53b2..ad77175dda45 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-apcc.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,msm8996-apcc + - qcom,msm8996pro-apcc reg: items: From patchwork Sat Apr 16 02:56:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE596C43219 for ; Sat, 16 Apr 2022 02:58:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229654AbiDPDBX (ORCPT ); Fri, 15 Apr 2022 23:01:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229626AbiDPDBW (ORCPT ); Fri, 15 Apr 2022 23:01:22 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E61C5F258; Fri, 15 Apr 2022 19:58:51 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id g20so11793514edw.6; Fri, 15 Apr 2022 19:58:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZQkWUnAkPP3u4wDz+lMwV1hykNAjw95szW9gvxsGCSo=; b=mEbB3krDIW75iC5+4cIhaXylVcw1BGskjQp0Ie5anGqFXmYfRVl7DJ0RNd55QbWhYq DMcBlD6K9yqvHFAYMz329UxQRxuH2DY0TC7WLAkyt2gfNmjoNLMONXRvEMuL0pXGtj4F GPkGh4Rvy6Y8NeCYZCRHtZxISMIS6t6KOcRCbsiEKALVgH+AGxpif1BAAsvKOWM0go08 PnN6p4F8PZkq1MtPWvWz9Z9mvErs7h+kliy1VLijuNihxDiMLT8bFEx2enMhUKcWlRAl 4PBmw7rV76lkcOPBguidS3WFzCQbfRbPI/X69qy6NIUTGFvZxSDgxufjH+0k0kOi0Km6 JI2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZQkWUnAkPP3u4wDz+lMwV1hykNAjw95szW9gvxsGCSo=; b=yjPB6kip1zSgq4tYv6hPlKiPbdOm9xgLGOj56+sFtmbrjzORUuslbmWAsI7LHLPZrP MUnOUdIG6q0jUBvYvhw9AEKra8nFaruN1rt4yJNcOR096bHm/o3hzstiIcPbbZ2NRv6t DwTtcSZdlSElAWDCfblwAro6OsxcHACxlTvf2MDEqNyLPnmyVasRsrEPoJMQpVpaHc2R sUNzZW6rpwdZ/IbJWvYTegISpl9EM9wgafyq7QgdeQnbqxIQMrZ2o5H2d15mYwY++sVd CtBdz/hbyt70ZhaQt3nb4UeJnG39L3WN4Ga85Nj945FZQs/anK+kAyKAYYknuq7eBhlh 97hA== X-Gm-Message-State: AOAM532Y1Ol0lW3aB9k+MU4nSg3b40eE2b9EkRun38tKvKzDNhdcpv7Q wWIx2aogskzO07GF3wlt8eM= X-Google-Smtp-Source: ABdhPJzwNrPggzMgLHIl78M6jF7LvWuJfTU8GCLc8NNJo0pgq651DFmkcVGAY5WvhKPVche/BtPKSQ== X-Received: by 2002:aa7:de93:0:b0:418:d700:662a with SMTP id j19-20020aa7de93000000b00418d700662amr1924630edv.107.1650077929526; Fri, 15 Apr 2022 19:58:49 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.159]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006e872188edbsm2200915ejb.104.2022.04.15.19.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 19:58:49 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana Subject: [PATCH RESEND v2 3/9] clk: qcom: msm8996-cpu: Add MSM8996 Pro CBF support Date: Sat, 16 Apr 2022 06:56:31 +0400 Message-Id: <20220416025637.83484-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MSM8996 Pro (MSM8996SG) has a /4 divisor on the CBF clock instead of /2. This allows it to reach a lower minimum frequency of 192000000Hz compared to 307200000Hz on regular MSM8996. Add support for setting the CBF clock divisor to /4 for MSM8996 Pro. Signed-off-by: Yassine Oudjana Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/clk-cpu-8996.c | 61 +++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 21 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 8afc271f92d0..231d8224fa16 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -70,11 +70,11 @@ enum _pmux_input { enum { CBF_PLL_INDEX = 1, - CBF_DIV_2_INDEX, + CBF_DIV_INDEX, CBF_SAFE_INDEX }; -#define DIV_2_THRESHOLD 600000000 +#define DIV_THRESHOLD 600000000 #define PWRCL_REG_OFFSET 0x0 #define PERFCL_REG_OFFSET 0x80000 #define MUX_OFFSET 0x40 @@ -142,6 +142,17 @@ static const struct alpha_pll_config cbfpll_config = { .early_output_mask = BIT(3), }; +static const struct alpha_pll_config cbfpll_config_pro = { + .l = 72, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x006, + .pre_div_mask = BIT(12), + .post_div_mask = 0x3 << 8, + .post_div_val = 0x3 << 8, + .main_output_mask = BIT(0), + .early_output_mask = BIT(3), +}; + static struct clk_alpha_pll perfcl_pll = { .offset = PERFCL_REG_OFFSET, .regs = prim_pll_regs, @@ -230,7 +241,8 @@ struct clk_cpu_8996_mux { u8 width; struct notifier_block nb; struct clk_hw *pll; - struct clk_hw *pll_div_2; + struct clk_hw *pll_div; + u8 div; struct clk_regmap clkr; }; @@ -280,11 +292,11 @@ static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); struct clk_hw *parent = cpuclk->pll; - if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { - if (req->rate < (DIV_2_THRESHOLD / 2)) + if (cpuclk->pll_div && req->rate < DIV_THRESHOLD) { + if (req->rate < (DIV_THRESHOLD / cpuclk->div)) return -EINVAL; - parent = cpuclk->pll_div_2; + parent = cpuclk->pll_div; } req->best_parent_rate = clk_hw_round_rate(parent, req->rate); @@ -336,7 +348,8 @@ static struct clk_cpu_8996_mux pwrcl_pmux = { .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, - .pll_div_2 = &pwrcl_smux.clkr.hw, + .pll_div = &pwrcl_smux.clkr.hw, + .div = 2, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -358,7 +371,8 @@ static struct clk_cpu_8996_mux perfcl_pmux = { .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, - .pll_div_2 = &perfcl_smux.clkr.hw, + .pll_div = &perfcl_smux.clkr.hw, + .div = 2, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", @@ -481,19 +495,23 @@ static int qcom_cbf_clk_msm8996_register_clks(struct device *dev, struct regmap *regmap) { int ret; + bool is_pro = of_device_is_compatible(dev->of_node, "qcom,msm8996pro-apcc"); - cbf_mux.pll_div_2 = clk_hw_register_fixed_factor(dev, "cbf_pll_main", - "cbf_pll", CLK_SET_RATE_PARENT, - 1, 2); - if (IS_ERR(cbf_mux.pll_div_2)) { + cbf_mux.div = is_pro ? 4 : 2; + cbf_mux.pll_div = clk_hw_register_fixed_factor(dev, "cbf_pll_main", + "cbf_pll", CLK_SET_RATE_PARENT, + 1, cbf_mux.div); + + if (IS_ERR(cbf_mux.pll_div)) { dev_err(dev, "Failed to initialize cbf_pll_main\n"); - return PTR_ERR(cbf_mux.pll_div_2); + return PTR_ERR(cbf_mux.pll_div); } ret = devm_clk_register_regmap(dev, cbf_msm8996_clks[0]); ret = devm_clk_register_regmap(dev, cbf_msm8996_clks[1]); - clk_alpha_pll_configure(&cbf_pll, regmap, &cbfpll_config); + clk_alpha_pll_configure(&cbf_pll, regmap, is_pro ? + &cbfpll_config_pro : &cbfpll_config); clk_set_rate(cbf_pll.clkr.hw.clk, 614400000); clk_prepare_enable(cbf_pll.clkr.hw.clk); clk_notifier_register(cbf_mux.clkr.hw.clk, &cbf_mux.nb); @@ -575,7 +593,7 @@ static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, qcom_cpu_clk_msm8996_acd_init(base); break; case POST_RATE_CHANGE: - if (cnd->new_rate < DIV_2_THRESHOLD) + if (cnd->new_rate < DIV_THRESHOLD) ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, DIV_2_INDEX); else @@ -600,15 +618,15 @@ static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event, switch (event) { case PRE_RATE_CHANGE: - parent = clk_hw_get_parent_by_index(&cbfclk->clkr.hw, CBF_DIV_2_INDEX); - ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_2_INDEX); + parent = clk_hw_get_parent_by_index(&cbfclk->clkr.hw, CBF_DIV_INDEX); + ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_INDEX); - if (cnd->old_rate > DIV_2_THRESHOLD && cnd->new_rate < DIV_2_THRESHOLD) - ret = clk_set_rate(parent->clk, cnd->old_rate / 2); + if (cnd->old_rate > DIV_THRESHOLD && cnd->new_rate < DIV_THRESHOLD) + ret = clk_set_rate(parent->clk, cnd->old_rate / cbfclk->div); break; case POST_RATE_CHANGE: - if (cnd->new_rate < DIV_2_THRESHOLD) - ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_2_INDEX); + if (cnd->new_rate < DIV_THRESHOLD) + ret = clk_cpu_8996_mux_set_parent(&cbfclk->clkr.hw, CBF_DIV_INDEX); else { parent = clk_hw_get_parent_by_index(&cbfclk->clkr.hw, CBF_PLL_INDEX); ret = clk_set_rate(parent->clk, cnd->new_rate); @@ -676,6 +694,7 @@ static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev) static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = { { .compatible = "qcom,msm8996-apcc" }, + { .compatible = "qcom,msm8996pro-apcc" }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table); From patchwork Sat Apr 16 02:56:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FABDC433F5 for ; Sat, 16 Apr 2022 02:59:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229673AbiDPDB1 (ORCPT ); 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Fri, 15 Apr 2022 19:58:52 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana Subject: [PATCH RESEND v2 4/9] cpufreq: qcom_cpufreq_nvmem: Simplify reading kryo speedbin Date: Sat, 16 Apr 2022 06:56:32 +0400 Message-Id: <20220416025637.83484-5-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MSM8996 and MSM8996 Pro have different OPPs with different dependencies on CPR and CBF levels. Sharing the same OPP tables will make implementing CPR and CBF scaling quite difficult, as it will become necessary to use opp-supported-hw not only to choose CPU OPPs, but to also choose their required CPR and CBF OPPs which are different on the same CPU OPP between MSM8996 and MSM8996 Pro. The best solution would be to make a new device tree for MSM8996 Pro which would override the OPP tables from the existing MSM8996 device tree. In preparation for adding a separate device tree for MSM8996 Pro, skip reading msm-id from smem and just read the speedbin efuse. Signed-off-by: Yassine Oudjana --- drivers/cpufreq/Kconfig.arm | 1 - drivers/cpufreq/qcom-cpufreq-nvmem.c | 75 +++------------------------- 2 files changed, 6 insertions(+), 70 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 954749afb5fe..7d9798bc5753 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -154,7 +154,6 @@ config ARM_QCOM_CPUFREQ_NVMEM tristate "Qualcomm nvmem based CPUFreq" depends on ARCH_QCOM depends on QCOM_QFPROM - depends on QCOM_SMEM select PM_OPP help This adds the CPUFreq driver for Qualcomm Kryo SoC based boards. diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 6dfa86971a75..a2b895a930cb 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -9,8 +9,8 @@ * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables * defines the voltage and frequency value based on the msm-id in SMEM * and speedbin blown in the efuse combination. - * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC - * to provide the OPP framework with required information. + * The qcom-cpufreq-nvmem driver reads efuse value from the SoC to provide the + * OPP framework with required information. * This is used to determine the voltage and frequency value for each OPP of * operating-points-v2 table when it is parsed by the OPP framework. */ @@ -27,22 +27,6 @@ #include #include #include -#include - -#define MSM_ID_SMEM 137 - -enum _msm_id { - MSM8996V3 = 0xF6ul, - APQ8096V3 = 0x123ul, - MSM8996SG = 0x131ul, - APQ8096SG = 0x138ul, -}; - -enum _msm8996_version { - MSM8996_V3, - MSM8996_SG, - NUM_OF_MSM8996_VERSIONS, -}; struct qcom_cpufreq_drv; @@ -142,35 +126,6 @@ static void get_krait_bin_format_b(struct device *cpu_dev, dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver); } -static enum _msm8996_version qcom_cpufreq_get_msm_id(void) -{ - size_t len; - u32 *msm_id; - enum _msm8996_version version; - - msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); - if (IS_ERR(msm_id)) - return NUM_OF_MSM8996_VERSIONS; - - /* The first 4 bytes are format, next to them is the actual msm-id */ - msm_id++; - - switch ((enum _msm_id)*msm_id) { - case MSM8996V3: - case APQ8096V3: - version = MSM8996_V3; - break; - case MSM8996SG: - case APQ8096SG: - version = MSM8996_SG; - break; - default: - version = NUM_OF_MSM8996_VERSIONS; - } - - return version; -} - static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, char **pvs_name, @@ -178,30 +133,13 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, { size_t len; u8 *speedbin; - enum _msm8996_version msm8996_version; *pvs_name = NULL; - msm8996_version = qcom_cpufreq_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); - return -ENODEV; - } - speedbin = nvmem_cell_read(speedbin_nvmem, &len); if (IS_ERR(speedbin)) return PTR_ERR(speedbin); - switch (msm8996_version) { - case MSM8996_V3: - drv->versions = 1 << (unsigned int)(*speedbin); - break; - case MSM8996_SG: - drv->versions = 1 << ((unsigned int)(*speedbin) + 4); - break; - default: - BUG(); - break; - } + drv->versions = 1 << (unsigned int)(*speedbin); kfree(speedbin); return 0; @@ -464,10 +402,9 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list); /* - * Since the driver depends on smem and nvmem drivers, which may - * return EPROBE_DEFER, all the real activity is done in the probe, - * which may be defered as well. The init here is only registering - * the driver and the platform device. + * Since the driver depends on the nvmem driver, which may return EPROBE_DEFER, + * all the real activity is done in the probe, which may be defered as well. + * The init here is only registering the driver and the platform device. */ static int __init qcom_cpufreq_init(void) { From patchwork Sat Apr 16 02:56:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B062C433FE for ; Sat, 16 Apr 2022 02:59:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229632AbiDPDBh (ORCPT ); Fri, 15 Apr 2022 23:01:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229621AbiDPDBe (ORCPT ); Fri, 15 Apr 2022 23:01:34 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C33CF8954; Fri, 15 Apr 2022 19:59:02 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id t11so18118112eju.13; Fri, 15 Apr 2022 19:59:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4yoSPlz/nCpT9f9CFlcsdO73J5/c7HsnuFzDG+XyBWY=; b=lIkUPrzzBFIEbCAJ1I6ahW16LHpV54SkngCNw69KRVk6Zaa3yysF1Q0AawQ6QQAH53 5eIr+tYYEOsbW7gkGQH/lJTdgAiLgx2xxtOfAiLgLRCJR304t5GXTmMMj2BVF5xyNtNn 0OGq+y8VfNmFE14xC2dApUmueGuSiYLjFLWJDu8C7BNMYnNruYMEmFSPVATMAEUcAotA VZMwUMr0W9HOsrM8vbvCp8Ac2AEL15um01Gh4owU0vxiJjCH5vQgntAp4nwuZboVqX2p AVaObAH1YtoQRMA1NR7IAKGnRhUHv311dSYo4XUjltlZ+j4641pxa7vrEMMrocURyw5z CnwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4yoSPlz/nCpT9f9CFlcsdO73J5/c7HsnuFzDG+XyBWY=; b=Obu2+FDoTwlEHsVarcnbzQBE+2IcgnYQaz2trFyjZWRK9VBfsPBplZBLUZrFrovfim dide+9fcz2BKWlkVQ2Td9liR2XkMm14FWuHxzuKsDm2ID5+xHRVi9TJO5yI3yQBVmA12 fpzJVMw8h0Whgwe4cyHrZKUQaiyAC/mux5mOi2m+ph73CdPHTsgsDd2Nur5Kan87511t dwMmIyIyp50gzK1KfE+icRkCm7otfP3Kpj+bZKv+JH4xKXQPJSSlyT+50vagC78YlBU/ D+4c11AH9ovlqE8mMYAYIhha0pcQqFzNFSVNTL7Jts6aN4Rc3VcyRCii8QmLWM4CuUQ6 Py/w== X-Gm-Message-State: AOAM5321YEfRTkGe/4bcrNDzSQ4WtXzzBcnuO+31xAk0xzZsQ7JIS3jb /VZ78FkJ+kAI81dWa0luhEU= X-Google-Smtp-Source: ABdhPJz/KpAnwDuM8kYSwlL6csMHjK7Ms7q8ZS6U/xx+aB5YAwjcF8rJ0behvDIMocs9dbwR8N4j0A== X-Received: by 2002:a17:907:3f8b:b0:6e8:318d:1def with SMTP id hr11-20020a1709073f8b00b006e8318d1defmr1394258ejc.153.1650077940389; Fri, 15 Apr 2022 19:59:00 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.159]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006e872188edbsm2200915ejb.104.2022.04.15.19.58.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 19:59:00 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana Subject: [PATCH RESEND v2 6/9] arm64: dts: qcom: msm8996: Remove MSM8996 Pro speed bins from cluster OPP tables Date: Sat, 16 Apr 2022 06:56:34 +0400 Message-Id: <20220416025637.83484-7-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Now that qcom-cpufreq-nvmem doesn't use SMEM to combine both MSM8996 and MSM8996 Pro speed bins into the same supported-hw bitmask, remove bits 4,5,6 from all opp-supported-hw in cluster OPPs. These bits will be placed in a separate device tree for MSM8996 Pro. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 82 +++++++++++++-------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6fb3ef9df05b..5695671bb934 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -142,82 +142,82 @@ cluster0_opp: opp-table-cluster0 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; }; @@ -230,127 +230,127 @@ cluster1_opp: opp-table-cluster1 { /* Nominal fmax for now */ opp-307200000 { opp-hz = /bits/ 64 <307200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; }; From patchwork Sat Apr 16 02:56:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF3BCC43217 for ; Sat, 16 Apr 2022 02:59:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229702AbiDPDBh (ORCPT ); Fri, 15 Apr 2022 23:01:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbiDPDBg (ORCPT ); Fri, 15 Apr 2022 23:01:36 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D623AF896C; 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Fri, 15 Apr 2022 19:59:04 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.159]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006e872188edbsm2200915ejb.104.2022.04.15.19.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 19:59:03 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana Subject: [PATCH RESEND v2 7/9] dt-bindings: arm: qcom: Add MSM8996 Pro compatible Date: Sat, 16 Apr 2022 06:56:35 +0400 Message-Id: <20220416025637.83484-8-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a qcom,msm8996pro compatible and move xiaomi,scorpio to the same items list as it. Signed-off-by: Yassine Oudjana Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 129cdd246223..dcf2e0102857 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -186,7 +186,12 @@ properties: - sony,kagura-row - sony,keyaki-row - xiaomi,gemini + - const: qcom,msm8996 + + - items: + - enum: - xiaomi,scorpio + - const: qcom,msm8996pro - const: qcom,msm8996 - items: From patchwork Sat Apr 16 02:56:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 653BCC433F5 for ; Sat, 16 Apr 2022 02:59:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229710AbiDPDBk (ORCPT ); Fri, 15 Apr 2022 23:01:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229671AbiDPDBk (ORCPT ); Fri, 15 Apr 2022 23:01:40 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 833BDF9555; Fri, 15 Apr 2022 19:59:09 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id bv19so18176842ejb.6; Fri, 15 Apr 2022 19:59:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+NV5gOjwMPjEqQproX/5dQ/w1lbzwSeSIPPGmGmAZ3I=; b=RYIPfsH2KIfCp4UttHOWlCbyVTpvnGtqEE84nK/CADuaYB1ZDqZTzHR9JqzM4+S2W3 UKIjFYHVC5w+DgYU1O3Dv5Wm4MuBtwBA3yDEnV0CCj1Cv+CwSzpz/xJITdUhFS6IJICE MNg9np+HR4PTq1UXHRsHFU7zgSoeJUPOA8JsF5z7D8seKLMX1pcdXHX7mfaEoX9nKv0k T48IoL3dm2AJOBwx62hnxrC2yOPt0+gIqohxvAvKPvD5PCvJ7FOWv2oYk4fXGDgfDGAJ c0El2HUgZh7DRY5Lhg4BSUjz+FI8omeATbTn7aw9I0mEcr+u4ajAI1H1M/G8JkAk+avH JSFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+NV5gOjwMPjEqQproX/5dQ/w1lbzwSeSIPPGmGmAZ3I=; b=zwXlz/HprFPjHOtCaARuvKws3GWGerpcnDOt6U2JJkgm9cxD/ClbDW51D5oC+5fGuQ sDMxC/yTatgbuImRNVMwcv4pMpRz0jUdJJunD0j9fP4wthtt+AaTd931UAQefDA6mKHY 7PXbWI24GqSdbM4TyF3tN6WVHcWo2e+93VNrvFNZg2Wcfj7yvp/aFydxY7tnS0UEzwjT httkgBhSdqwgcpKWMStoVZfE3j+q7YWS4EayWmHu45DEzyZ5rfKO0BfRvQ3LyBxUyYHd yxXYdcVkx79j3A5+o35qVaRvJdm3ox6+ltg/2OhojMfC1FDCVnvt6vD/iyZDhdFV96Gl BmwQ== X-Gm-Message-State: AOAM532R+XcS1KkEhe3xn5rSVmWE5zYlAKlq2EZiwBF3l1F37cIH2/1m H/SswYR9dcLWn34ZJ90/YXA= X-Google-Smtp-Source: ABdhPJxLLGhJogsJ4zEG4NYzQ7tVDi+L+unDNFU+r2d5G+qQ6zKcY5MPnOc+CXkWyR9doSbBCH8DTA== X-Received: by 2002:a17:906:4944:b0:6e8:a48d:804e with SMTP id f4-20020a170906494400b006e8a48d804emr1366676ejt.164.1650077948116; Fri, 15 Apr 2022 19:59:08 -0700 (PDT) Received: from localhost.localdomain ([138.199.7.159]) by smtp.gmail.com with ESMTPSA id oz20-20020a170906cd1400b006e872188edbsm2200915ejb.104.2022.04.15.19.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 19:59:07 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana Subject: [PATCH RESEND v2 8/9] arm64: dts: qcom: msm8996: Add MSM8996 Pro support Date: Sat, 16 Apr 2022 06:56:36 +0400 Message-Id: <20220416025637.83484-9-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a new DTSI for MSM8996 Pro (MSM8996SG) with msm-id and CPU/GPU OPPs. CBF OPPs and CPR parameters will be added to it as well once support for CBF scaling and CPR is introduced. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 281 +++++++++++++++++++++++ 1 file changed, 281 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8996pro.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi new file mode 100644 index 000000000000..8c8dd5614f4d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Yassine Oudjana + */ + +#include "msm8996.dtsi" + +/* + * MSM8996 Pro (also known as MSM8996SG) is a revision of MSM8996 with + * different CPU, CBF and GPU frequencies as well as CPR parameters. + */ +/delete-node/ &cluster0_opp; +/delete-node/ &cluster1_opp; + +/ { + qcom,msm-id = <305 0x10000>; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-supported-hw = <0x2>; + clock-latency-ns = <200000>; + }; + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; +}; + +&gpu_opp_table { + /* + * All MSM8996 GPU OPPs are available on MSM8996 Pro, + * in addition to one: + */ + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-supported-hw = <0x1>; + }; +}; + +&kryocc { + compatible = "qcom,msm8996pro-apcc"; +}; From patchwork Sat Apr 16 02:56:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 12815658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B7DC433F5 for ; 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Fri, 15 Apr 2022 19:59:11 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Ilia Lin , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" Cc: Konrad Dybcio , Dmitry Baryshkov , Loic Poulain , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, Yassine Oudjana Subject: [PATCH RESEND v2 9/9] arm64: dts: qcom: msm8996-xiaomi-scorpio: Use MSM8996 Pro Date: Sat, 16 Apr 2022 06:56:37 +0400 Message-Id: <20220416025637.83484-10-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220416025637.83484-1-y.oudjana@protonmail.com> References: <20220416025637.83484-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The Xiaomi Mi Note 2 has the MSM8996 Pro SoC. Rename the dts to match, include msm8996pro.dtsi, and add the qcom,msm8996pro compatible. To do that, the msm8996.dtsi include in msm8996-xiaomi-common has to be moved to msm8996-xiaomi-gemini, the only device that needs it included after this change. The msm-id is also removed as it is now defined in msm8996pro.dtsi. Signed-off-by: Yassine Oudjana --- arch/arm64/boot/dts/qcom/Makefile | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 3 --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 1 + ...m8996-xiaomi-scorpio.dts => msm8996pro-xiaomi-scorpio.dts} | 4 ++-- 4 files changed, 4 insertions(+), 6 deletions(-) rename arch/arm64/boot/dts/qcom/{msm8996-xiaomi-scorpio.dts => msm8996pro-xiaomi-scorpio.dts} (99%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f9e6343acd03..72b8fcdd9074 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -37,7 +37,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 7a9fcbe9bb31..1bdd3f09f536 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -3,9 +3,6 @@ * Copyright (c) 2020, Yassine Oudjana */ -/dts-v1/; - -#include "msm8996.dtsi" #include "pm8994.dtsi" #include "pmi8994.dtsi" #include diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 34f82e06ef53..e360187109a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "msm8996.dtsi" #include "msm8996-xiaomi-common.dtsi" #include #include diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts similarity index 99% rename from arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts rename to arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts index 27a45ddbb5bd..2028325e1c0f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "msm8996pro.dtsi" #include "msm8996-xiaomi-common.dtsi" #include "pmi8996.dtsi" #include @@ -12,9 +13,8 @@ / { model = "Xiaomi Mi Note 2"; - compatible = "xiaomi,scorpio", "qcom,msm8996"; + compatible = "xiaomi,scorpio", "qcom,msm8996pro", "qcom,msm8996"; chassis-type = "handset"; - qcom,msm-id = <305 0x10000>; qcom,board-id = <34 0>; chosen {