From patchwork Sat Apr 16 11:05:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A92B9C433EF for ; Sat, 16 Apr 2022 11:05:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4eoKjGsUqn366TaQMxIiXNHBYpCfqZBXLrNBlVZ/vVI=; b=SdINgl+zUfrUdy /0XWUWrb68NQTxzOgF2rGFhAZL6WH2IhRYAFNlVrbuCQQKaOJeGgQ8RXiPZBUMxEynRVDe9ChmYaW /dvVvVFADH7qmjntM6dcsmoYxDsJX7Yuou5E07dalpG8fsRW0elOCCCKHza5BAEo0nIv4aLVWmfu8 5558KuSe5qOZHCMVSEqE+6/iXqGzE8sO8fKVbLO9XEsaKJBimRBx9+b4WtgPlMyfZpCiyAXYijXlc dvC35KUPJWMEcBFwkksnMbdtrmYdFJkPJeBBiHS1xo0XBUBwydGo5IY5GS0A60oZ5AajjnyWG3W3m wsmyS1qGYtSQ+csGvKHA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgF5-00CnLk-IV; Sat, 16 Apr 2022 11:05:27 +0000 Received: from mail-qt1-x830.google.com ([2607:f8b0:4864:20::830]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgEs-00CnH6-Fl; Sat, 16 Apr 2022 11:05:17 +0000 Received: by mail-qt1-x830.google.com with SMTP id bb38so7324706qtb.3; Sat, 16 Apr 2022 04:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UMYeeN0iZUy6EfrHqDAGGWFWHi99PGIp7rnql4YH69k=; b=mO+c+dgqNkgVHglcmeNkqeYKEFrbca9Mg1ereL9nAPWF+rDUhc5bExsShTgtJGU7Fq YnBsFlQMii8hiDBByq1Mbg04Uu+YzbVE16mL0cTHy1TQzjI7YMPODVwtC6Dvplq3jmdM YhSlC9j+CkJOAjRvVzQvy8rE9ed4kuu94gZMUlA/RVHyRp7PnzBTZ5S8IQGcroVUQTgM +hbuGk86KhafBO6pYzl38Zqr07WbTYZ+o3yivDwoqTHoUJi7n45BFRLWAEkSUirlPDTU MXKd2Fq214KHOcDSHUnOQDbrAxQH+9jNaxYtaM1bAuaFWzMsFLfu216YmPC1z0GRwceL 9f4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UMYeeN0iZUy6EfrHqDAGGWFWHi99PGIp7rnql4YH69k=; b=T2wSX7AHooGhcDdkkgtZsGs43tT1rePRScztF1og77P4cfSqDJo4gY6v4Y8gRGdeuo 53GmWOi7Xk1e3w8mUcZv56hcOcV1s1En+cEBeKtvMTzk1cuKR0cDNzyJ4pBaUoosYNlQ 3KKBT3x6Hh53QifAHlrCRY1lXfJ9Tro/358wQ26+iZfyAn7M4MgBgVrbnM6x2zey2ESC UWrqZXKAJ1bw9u3Yl3oGheebJvvE0v4HDJtJfNrHZqLd8OgSxezUikwb7iIVaz8E3Yw+ uO2+9Mv8cSOMOI/wJoreTFxL4ssoqJZUugWvb8OxJwMXKliPbabTcwynkxm5/2ADfb4g hdow== X-Gm-Message-State: AOAM533vINQIKxkQ57ztRAuhvIW3SB41HvCtBvta+CUCzmsfgblyrod2 B1ouAaT/Unz43XvI2O5Xk1A= X-Google-Smtp-Source: ABdhPJyEAu3rtiQo0zzKoe4zKalnE3V0w3SLyN99GNkbCGHM7+Ji+PwVeroMv+GZu4jpHLnxwpdRsw== X-Received: by 2002:ac8:1191:0:b0:2ed:bb6:ab07 with SMTP id d17-20020ac81191000000b002ed0bb6ab07mr1935995qtj.418.1650107112074; Sat, 16 Apr 2022 04:05:12 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id w6-20020a05622a190600b002f1f91ad3e7sm97026qtc.22.2022.04.16.04.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Apr 2022 04:05:11 -0700 (PDT) From: Peter Geis To: Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Simon Xue Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 1/4] dt-bindings: pci: remove fallback from Rockchip DesignWare binding Date: Sat, 16 Apr 2022 07:05:03 -0400 Message-Id: <20220416110507.642398-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416110507.642398-1-pgwipeout@gmail.com> References: <20220416110507.642398-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220416_040514_562101_9C3F1724 X-CRM114-Status: GOOD ( 11.12 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The snps,dw-pcie binds to a standalone driver. It is not fully compatible with the Rockchip implementation and causes a hang if it binds to the device. Remove this binding as a valid fallback. Signed-off-by: Peter Geis Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 142bbe577763..bc0a9d1db750 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -19,20 +19,10 @@ description: |+ allOf: - $ref: /schemas/pci/pci-bus.yaml# -# We need a select here so we don't match all nodes with 'snps,dw-pcie' -select: - properties: - compatible: - contains: - const: rockchip,rk3568-pcie - required: - - compatible - properties: compatible: items: - const: rockchip,rk3568-pcie - - const: snps,dw-pcie reg: items: @@ -110,7 +100,7 @@ examples: #size-cells = <2>; pcie3x2: pcie@fe280000 { - compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0800000 0x0 0x390000>, <0x0 0xfe280000 0x0 0x10000>, <0x3 0x80000000 0x0 0x100000>; From patchwork Sat Apr 16 11:05:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D1A8C433EF for ; Sat, 16 Apr 2022 11:05:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M9MtqCulyYQbBiTqklKlQXPINRqSuJMpQZf/2za1ctM=; b=rvErN/+n453xm5 Gsjcd9GluO4eUqwLdo5iuXvYGLGphuqbfThkQv+91fvqWdHJWUr6TkdiKnJIBiE3Gs9XsxeMY0w3Z oA/qy+dsdLkXI7xT+U3WIXLbX3l3TXFpU6JCiqh8LZearzyVCmeqT2o4zUNlX8MCkyJtj2MQ0W6z9 LcWFhidvwCPhVtL3y4hi0pHfOdynmm+F+97prLvIUzZ69a7xlVjNq1Qa2kH1qUB6pmJVVC6v/Nj1W stnwyNLyKy1RjQ1yzXon2YoY8ApY7w3WJiaGs1zsy2F7Dv4y5jPpemD26pJkBOvpS1g34M2E5KAnK Ww4G5ml+W1TbO9nedMLw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgFQ-00CnXd-F3; Sat, 16 Apr 2022 11:05:48 +0000 Received: from mail-qk1-x731.google.com ([2607:f8b0:4864:20::731]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgEs-00CnH7-Qt; Sat, 16 Apr 2022 11:05:19 +0000 Received: by mail-qk1-x731.google.com with SMTP id d198so4999672qkc.12; Sat, 16 Apr 2022 04:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2wd9sVHC/mmpYlhb5g3G/iw92sjMjBm/QMls3NoS/gY=; b=YlTGFeYjrIrumrZP+5CDlg2AkD0OJl3NYU1RSr68tmG7LUCUH6ZWffvts6Bdzo/7ca 4XKcK8cY0tWyo5H98SRl6riGPjPy3OVOx3yqk0AGasS8mOC1CP248b2Z0avHgeJrBw6L dPJD2pTd+JdghXArj8o0X97w4slG3e12aAZAUO4ykL0cwUCC2NU/V5jIf+oOxPffLHPx wFTvM3Rx7/7jQAAailoeItdAZQizaA4My4rwfi+apYs2+lDWZNrwBycqW6fqesw7bsCq lYmoTkVxU6ZrIABU92zTIw7WebKZMn9lsSfoVXZQ8OoMAjKKXplwFTg/QE0dLO4+47Ww +qow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2wd9sVHC/mmpYlhb5g3G/iw92sjMjBm/QMls3NoS/gY=; b=8CKhwT7lSDUILv0ZHMaDTbiaxG5A5jkA/Hljz2ubSn1vZhhUysWx2GamiCdcY6Mk/u ctIum4zGY1+e+d+2CwcSoW1NKQu0FQH4s0OzzbwTe5yzOeixcAikphWwSkFzrwxlxTva lFsU7Oi/oBDrWbSYyzRrJGy5mlYydl4zKVVDtEljlo2ib5sYZyGitxv8dNTDSVwR6dTg v7bp22ENKf1dlQtMHruw2cwaoZU4kbsq40dalplv5yAzKCLO5y6nfaONMR3X6Mk1mvwS 4yY6zYpXONGK/7X5+V5egssPgqlIcYBWeyoPqDKrbybNEZhgLin/u7eivQWzxLM7vCl5 MFyA== X-Gm-Message-State: AOAM5303KmWvBoxHYF4oyIjTe13Ogj2ZisVe55rHFQDrPtuUSlr27Me3 gXsOSH7RxqaZxkp6cHxPwNk= X-Google-Smtp-Source: ABdhPJzgP/Su9sVo1WAek3VOvHi3aYFIuz+vrZ6O0feP9a0D2IimwOcRKvjATzNU5fvbJKAMD3h1cQ== X-Received: by 2002:ae9:ef55:0:b0:69e:7116:8644 with SMTP id d82-20020ae9ef55000000b0069e71168644mr1093833qkg.293.1650107113047; Sat, 16 Apr 2022 04:05:13 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id w6-20020a05622a190600b002f1f91ad3e7sm97026qtc.22.2022.04.16.04.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Apr 2022 04:05:12 -0700 (PDT) From: Peter Geis To: Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 2/4] PCI: dwc: rockchip: add legacy interrupt support Date: Sat, 16 Apr 2022 07:05:04 -0400 Message-Id: <20220416110507.642398-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416110507.642398-1-pgwipeout@gmail.com> References: <20220416110507.642398-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220416_040514_911326_C7D9AFDB X-CRM114-Status: GOOD ( 19.11 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The legacy interrupts on the rk356x pcie controller are handled by a single muxed interrupt. Add irq domain support to the pcie-dw-rockchip driver to support the virtual domain. Signed-off-by: Peter Geis --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 112 +++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index c9b341e55cbb..863374604fb1 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -10,9 +10,12 @@ #include #include +#include +#include #include #include #include +#include #include #include #include @@ -36,10 +39,13 @@ #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) #define PCIE_L0S_ENTRY 0x11 #define PCIE_CLIENT_GENERAL_CONTROL 0x0 +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c #define PCIE_CLIENT_GENERAL_DEBUG 0x104 -#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 +#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) +#define PCIE_LEGACY_INT_ENABLE GENMASK(3, 0) +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) struct rockchip_pcie { @@ -51,6 +57,8 @@ struct rockchip_pcie { struct reset_control *rst; struct gpio_desc *rst_gpio; struct regulator *vpcie3v3; + struct irq_domain *irq_domain; + raw_spinlock_t irq_lock; }; static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, @@ -65,6 +73,94 @@ static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, writel_relaxed(val, rockchip->apb_base + reg); } +static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); + unsigned long reg, hwirq; + + chained_irq_enter(chip, desc); + + reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); + + for_each_set_bit(hwirq, ®, 8) + generic_handle_domain_irq(rockchip->irq_domain, hwirq); + + chained_irq_exit(chip, desc); +} + +static void rockchip_intx_mask(struct irq_data *data) +{ + struct rockchip_pcie *rockchip = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 val; + + /* disable legacy interrupts */ + raw_spin_lock_irqsave(&rockchip->irq_lock, flags); + val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); + val |= PCIE_LEGACY_INT_ENABLE; + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); + raw_spin_unlock_irqrestore(&rockchip->irq_lock, flags); +}; + +static void rockchip_intx_unmask(struct irq_data *data) +{ + struct rockchip_pcie *rockchip = irq_data_get_irq_chip_data(data); + unsigned long flags; + u32 val; + + /* enable legacy interrupts */ + raw_spin_lock_irqsave(&rockchip->irq_lock, flags); + val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); + val &= ~PCIE_LEGACY_INT_ENABLE; + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); + raw_spin_unlock_irqrestore(&rockchip->irq_lock, flags); +}; + +static struct irq_chip rockchip_intx_irq_chip = { + .name = "INTx", + .irq_mask = rockchip_intx_mask, + .irq_unmask = rockchip_intx_unmask, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, +}; + +static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops intx_domain_ops = { + .map = rockchip_pcie_intx_map, +}; + +static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) +{ + struct device *dev = rockchip->pci.dev; + struct device_node *intc; + + raw_spin_lock_init(&rockchip->irq_lock); + + intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); + if (!intc) { + dev_err(dev, "missing child interrupt-controller node\n"); + return -EINVAL; + } + + rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, + &intx_domain_ops, rockchip); + of_node_put(intc); + if (!rockchip->irq_domain) { + dev_err(dev, "failed to get a INTx IRQ domain\n"); + return -EINVAL; + } + + return 0; +} + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, @@ -111,7 +207,19 @@ static int rockchip_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + struct device *dev = rockchip->pci.dev; u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + int irq, ret; + + irq = of_irq_get_byname(dev->of_node, "legacy"); + if (irq < 0) + return irq; + + ret = rockchip_pcie_init_irq_domain(rockchip); + if (ret < 0) + dev_err(dev, "failed to init irq domain\n"); + + irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, rockchip); /* LTSSM enable control mode */ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); From patchwork Sat Apr 16 11:05:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77AFCC433F5 for ; Sat, 16 Apr 2022 11:05:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sR9xcKwlzMMdkbdhXBf/qdl9CujfBagJsa7up+zBYH0=; b=D2DzpiGxkcSfCM 6e8Vhnzk39lLJR2wTwgqCqkZEcR9mvqFhZLXR4Ygyji5PQT4LMdASk21c/WMa28wyvRHDZ8RSoKxg skZ2eGL6WBDqocIY6msz9Dxy2G/bPZ55mh8Encl6GHw4ZryaWZhrAaV2moxarULGdC2u06yPS3P4c 89lm4pQ/C4ccxz9aRhuaYna4BHQR2q2NnRwI1t5P6JYa6shskQZsLWa5vk+Dtvf8wYiUwwiXOdeJ9 fbZZp+EiUr7iARDt+BaNvON8wqd5qTK0teZAjUXmamUIkiWTHfRwrsdPIYgWz6wdCatynuALDv0uY Uj7oOlanWqmOCzRHONzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgFF-00CnQL-90; Sat, 16 Apr 2022 11:05:37 +0000 Received: from mail-qt1-x833.google.com ([2607:f8b0:4864:20::833]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgEt-00CnHQ-LE; Sat, 16 Apr 2022 11:05:18 +0000 Received: by mail-qt1-x833.google.com with SMTP id s6so7322203qta.1; Sat, 16 Apr 2022 04:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wHb/kWKkyUoMSq3gKmql5I0wP4N+nhBclwmCSXeGOCA=; b=DeSr22RKUsgQpJKim6SJmZdEax2iP8VQJMrxoFEpH17Sfn3Gc6Y3mGfrqn2pgEhPMd tCdM968xmSZ5NvLk5optsYY9Ha6I1ySvwiQNfUTxWU97yf8lXGqREsx7K42vagDsYS3m 5nsqAuHdS16X6qLysAmxwvf591wagOYDS0US8VWnea2cKnNzHmvlOOB2BV7nTZPasX63 clP9YgMpOh0Fb7doH7qgprEdPSthlVYRilkLZtvD3YdFeTBmPHs8vUN1c6keVvm/aG7y bo7fgnWU3GpSevUpeXGW3t/siZodwHLNnTLzsObW2kX7Q6ZHznUmCvULhmNlaolfUTFL kusg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wHb/kWKkyUoMSq3gKmql5I0wP4N+nhBclwmCSXeGOCA=; b=cFxBC6Ki5bvsfqbD5pKrNzoE4TrbHgaU+vAQc0ZV8KwxqdZy/ZFRViG7NTj0cAiqmC bjHTFg/eYpLCkD9bwURzrwbvrESAYXQ8GhfZ3vlll7LbL9ccJpbieUuQRrZ0ARdeLipa 7QSJ4V766FEsQA8BPuUGdGWZWEXZtKFOp5415LmbrRH/Y9WXpBBuSMgUxxw7dzFex9wN JLC6g1gsDR9g0Eer/fXnzJ0snqK+fSUGQhHCrUNA827T6QXIH0U1spYqDKUm5jtGlQNh /VAAYTVBiEWwdsh8ACA2cQncq+Yqx3iQxmIMGy5I7bGyKFFMbLeIk7II0IpBEzu+vH2U dEUg== X-Gm-Message-State: AOAM531oV7t+0K1+di43Misv4BqV60rtpfQMIG/Tz/v+GrfRD2NJm3cp hzid2jwXDPB3pBewjeqQ2nE= X-Google-Smtp-Source: ABdhPJxG6E7fIu49tzkJ5bJeXmAzZsUQjvjD8ZS4FiBSmkWy8B5OREubKBHRVnYg7JsCT6oFLCDdsA== X-Received: by 2002:ac8:7f4b:0:b0:2f1:effa:6175 with SMTP id g11-20020ac87f4b000000b002f1effa6175mr1864999qtk.555.1650107113973; Sat, 16 Apr 2022 04:05:13 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id w6-20020a05622a190600b002f1f91ad3e7sm97026qtc.22.2022.04.16.04.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Apr 2022 04:05:13 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 3/4] arm64: dts: rockchip: add rk3568 pcie2x1 controller Date: Sat, 16 Apr 2022 07:05:05 -0400 Message-Id: <20220416110507.642398-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416110507.642398-1-pgwipeout@gmail.com> References: <20220416110507.642398-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220416_040515_730850_A3E9411E X-CRM114-Status: GOOD ( 10.15 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The pcie2x1 controller is common between the rk3568 and rk3566. It is a single lane pcie2 compliant controller. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 52 ++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index ca20d7b91fe5..bb08633332c7 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -722,6 +722,58 @@ qos_vop_m1: qos@fe1a8100 { reg = <0x0 0xfe1a8100 0x0 0x20>; }; + pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msi", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; + msi-map = <0x0 &gic 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, + <0x3 0x00000000 0x0 0x01000000>; + ranges = <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000 + 0x02000000 0x0 0x02000000 0x3 0x01100000 0x0 0x3ef00000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + status = "disabled"; + + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = ; + }; + + }; + sdmmc0: mmc@fe2b0000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2b0000 0x0 0x4000>; From patchwork Sat Apr 16 11:05:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 12815805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B46BC433EF for ; Sat, 16 Apr 2022 11:06:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GvQJ2zQLCEYUqGw1Y6Txp5HQldQEL/+FfVLUdvCYBXQ=; b=eYmUKNbCgFBzV3 Ehuo1NOkzwZF2oDawLUIkGan8oqU2mBTRf9vn7tNWcJ0FVQsZuMNPJNoaUL28pU49d57G7a74+OR2 DdvO5jmzBkeiuRFc5h5fMoZ/3SQkZgY97RCnL3JS6qZHxvl7UIL08/yBaNy1/qogYIfatTJtofTiD MXoXPZFbIladr8Wbb8pYQF8rMoE6NxkCmEuWANI5BfXiAavjtRaQsdNNZDz+vAVS6uATXAzANMQLo VGbCEaymA1u8sLqf464dFgN4F3Zs9P9TWOis9E6SJgktM54bWdu1faEwW7NO59v0DVm6N3FbdZRLA YXT+VgeVmOhOsSKu4fHA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgFe-00Cng4-7Y; Sat, 16 Apr 2022 11:06:02 +0000 Received: from mail-qk1-x736.google.com ([2607:f8b0:4864:20::736]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nfgEu-00CnI4-7C; Sat, 16 Apr 2022 11:05:20 +0000 Received: by mail-qk1-x736.google.com with SMTP id b68so3394402qkc.4; Sat, 16 Apr 2022 04:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IqOtlYyePRN/r4aPym/C6r8euVVGX9fSqK0zMFP5Scg=; b=Ay1l2u7NSquF+9PFgxtbeBqNLhrl/1lHtqjekfmK+9qQ/SzNzdamOekZ0caVKln0z9 GEWVMDqegY3wwkydYjmptujbX7Xomb9wkwHuDaH+i9bwlKhnr6VAKR0dFP5GIlbhjqbt JWM0zCBy8cF/YHITuVC7cU2pH5pC3Kojg7wLJf3scsmrGUimgssZ5bE0CeR02TqF4sVk pyH/jQoA1B0pG/DLmymtXOuPJaSK1MGmV8rQsukr5eFkGMcJ0xJmbqWHuOrzFWw3Ld99 yPRbBFr6DkgV5xZBbab+kqen3JiTg0qyRNl8Gcc9YoQ8PJfjuCkdihuwQlFQyijn/NHs K6dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IqOtlYyePRN/r4aPym/C6r8euVVGX9fSqK0zMFP5Scg=; b=p5UbUE4W8sJU3KKLTfgiqQAobsG2X5CavDQoBouqLc+RqzABcQqm/sUDNO9viwf2qb QVYrf20w9mU30K3OiOihDFvbeYMvPCd01JCHfV4/xmb4yr6Bd3ZlPQHJNFlQ0pgKwsbR /RrN13SwS+lVpx/756rQTwkuVBk0H3e+hVAFyCUlG6di0RHKAX6co/AYxP9bL2LYJTw4 MZ4Rg1zIYzEhR9eSqLjwXor3vqHHuZksgmoa7lWSGqasmF43oh6AHrJb5xKjZOX+1QwB /1ci301rJXn1IUhh/QWg9pTEBTXj6kMkTd/IFfkhx5QCZuMQeGj3DXHyks+htcbFcjuh hFyQ== X-Gm-Message-State: AOAM531UtZ3n7pisH8Gw1vCjRM8pcUNZh/EBOq/iJFQK8rdqIh93txKY d7k1r7ajBsS7MIjVfZJMHKE= X-Google-Smtp-Source: ABdhPJxmwpn+eW8bdaz975hRwX2JS+73deqtcOTIOVPwSnY4StdJw+G5r+6cVfuDeQ6dNs7KIKgE9Q== X-Received: by 2002:a37:ba45:0:b0:69b:e728:34b7 with SMTP id k66-20020a37ba45000000b0069be72834b7mr1656171qkf.606.1650107114886; Sat, 16 Apr 2022 04:05:14 -0700 (PDT) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id w6-20020a05622a190600b002f1f91ad3e7sm97026qtc.22.2022.04.16.04.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Apr 2022 04:05:14 -0700 (PDT) From: Peter Geis To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, Peter Geis , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 4/4] arm64: dts: rockchip: enable pcie controller on quartz64-a Date: Sat, 16 Apr 2022 07:05:06 -0400 Message-Id: <20220416110507.642398-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416110507.642398-1-pgwipeout@gmail.com> References: <20220416110507.642398-1-pgwipeout@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220416_040516_321303_CEC9E700 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add the nodes to enable the pcie controller on the quartz64 model a board. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 141a433429b5..85926d46337d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -125,6 +125,18 @@ vbus: vbus { vin-supply = <&vcc12v_dcin>; }; + vcc3v3_pcie_p: vcc3v3_pcie_p { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie_p"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + vcc5v0_usb: vcc5v0_usb { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; @@ -201,6 +213,10 @@ &combphy1 { status = "okay"; }; +&combphy2 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -509,6 +525,14 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + vpcie3v3-supply = <&vcc3v3_pcie_p>; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -534,6 +558,16 @@ diy_led_enable_h: diy-led-enable-h { }; }; + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;