From patchwork Mon Apr 18 13:21:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18D30C352A1 for ; Mon, 18 Apr 2022 14:26:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343717AbiDRO3N (ORCPT ); Mon, 18 Apr 2022 10:29:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344424AbiDRO1Z (ORCPT ); Mon, 18 Apr 2022 10:27:25 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 737EA3D499; Mon, 18 Apr 2022 06:22:27 -0700 (PDT) X-UUID: f75a66ff43b94f8b819e1b37ecc3b7f4-20220418 X-UUID: f75a66ff43b94f8b819e1b37ecc3b7f4-20220418 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1012260767; Mon, 18 Apr 2022 21:22:23 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 18 Apr 2022 21:22:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Apr 2022 21:22:22 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 1/7] clk: mediatek: reset: Correct the logic of setting register Date: Mon, 18 Apr 2022 21:21:48 +0800 Message-ID: <20220418132154.7401-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/reset.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index bcec4b89f449..834d26e9bdfd 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -25,7 +25,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4); - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, @@ -34,7 +34,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_assert(struct reset_controller_dev *rcdev, From patchwork Mon Apr 18 13:21:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 847BCC43217 for ; Mon, 18 Apr 2022 14:27:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245568AbiDRO3y (ORCPT ); Mon, 18 Apr 2022 10:29:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344542AbiDRO1i (ORCPT ); Mon, 18 Apr 2022 10:27:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D09B532C7; Mon, 18 Apr 2022 06:22:33 -0700 (PDT) X-UUID: 4e4fae0afe094a9799ab825ebc8af60e-20220418 X-UUID: 4e4fae0afe094a9799ab825ebc8af60e-20220418 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 240949655; Mon, 18 Apr 2022 21:22:24 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Apr 2022 21:22:22 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 2/7] clk: mediatek: reset: Rename reset function Date: Mon, 18 Apr 2022 21:21:49 +0800 Message-ID: <20220418132154.7401-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There are two version for clock reset register control of MediaTek SoCs. Since MT8183, the version 2 is adopted. To make the driver more readable, - Rename them to v2 for MT8183 and v1 for previous SoCs. - Adjust the fuinction order in reset.c. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +- drivers/clk/mediatek/clk-mt2712.c | 4 +- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +- drivers/clk/mediatek/clk-mt7622.c | 4 +- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +- drivers/clk/mediatek/clk-mt8135.c | 4 +- drivers/clk/mediatek/clk-mt8173.c | 4 +- drivers/clk/mediatek/clk-mt8183.c | 2 +- drivers/clk/mediatek/clk-mtk.h | 8 +-- drivers/clk/mediatek/reset.c | 76 ++++++++++++++------------- 15 files changed, 64 insertions(+), 60 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 100ff6ca609e..f3e56a988177 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 1328c112a38f..5a41d4607e77 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0xc); + mtk_register_reset_controller_v1(node, 1, 0xc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 61444881c539..426a54cb077b 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 1eb3e4563c3f..0e103d6735bb 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_v1(node, 2, 0x30); return 0; } @@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller_v1(node, 2, 0x0); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index ff72b9ab945b..e80fc89a5a07 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_v1(node, 2, 0x30); return r; } @@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_v1(node, 2, 0); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index c9947dc7ba5a..13f346643e26 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 628be0c9f888..32855bb489a2 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return r; } @@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 0e1fb30a1e98..953e81049957 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 1, 0x30); + mtk_register_reset_controller_v1(node, 1, 0x30); return 0; } @@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller_v1(node, 2, 0x0); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 88279d0ea1a7..e47b66c67079 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 5c5b37207afb..72f261f12e92 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return r; } @@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_v1(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 09ad272d51f1..d649e817b320 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_v1(node, 2, 0x30); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_v1(node, 2, 0); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 46b7655feeaa..11becf2f7a9f 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_v1(node, 2, 0x30); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_v1(node, 2, 0); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 68496554dd3d..ac76328c423d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1239,7 +1239,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); + mtk_register_reset_controller_v2(node, 4, INFRA_RST0_SET_OFFSET); return r; } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bf6565aa7319..601db24a342b 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -190,11 +190,11 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs); +void mtk_register_reset_controller_v1(struct device_node *np, + unsigned int num_regs, int regofs); -void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs); +void mtk_register_reset_controller_v2(struct device_node *np, + unsigned int num_regs, int regofs); struct mtk_clk_desc { const struct mtk_gate *clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 834d26e9bdfd..b1012b0c44d0 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -19,75 +19,79 @@ struct mtk_reset { struct reset_controller_dev rcdev; }; -static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_assert_v1(struct reset_controller_dev *rcdev, + unsigned long id) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - unsigned int reg = data->regofs + ((id / 32) << 4); - return regmap_write(data->regmap, reg, BIT(id % 32)); + return regmap_update_bits(data->regmap, + data->regofs + ((id / 32) << 2), + BIT(id % 32), ~0); } -static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_deassert_v1(struct reset_controller_dev *rcdev, + unsigned long id) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; - return regmap_write(data->regmap, reg, BIT(id % 32)); + return regmap_update_bits(data->regmap, + data->regofs + ((id / 32) << 2), + BIT(id % 32), 0); } -static int mtk_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_assert_v2(struct reset_controller_dev *rcdev, + unsigned long id) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), ~0); + return regmap_write(data->regmap, + data->regofs + ((id / 32) << 4), + BIT(id % 32)); } -static int mtk_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_deassert_v2(struct reset_controller_dev *rcdev, + unsigned long id) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), 0); + return regmap_write(data->regmap, + data->regofs + ((id / 32) << 4) + 0x4, + BIT(id % 32)); } -static int mtk_reset(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_v1(struct reset_controller_dev *rcdev, + unsigned long id) { int ret; - ret = mtk_reset_assert(rcdev, id); + ret = mtk_reset_assert_v1(rcdev, id); if (ret) return ret; - return mtk_reset_deassert(rcdev, id); + return mtk_reset_deassert_v1(rcdev, id); } -static int mtk_reset_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_v2(struct reset_controller_dev *rcdev, + unsigned long id) { int ret; - ret = mtk_reset_assert_set_clr(rcdev, id); + ret = mtk_reset_assert_v2(rcdev, id); if (ret) return ret; - return mtk_reset_deassert_set_clr(rcdev, id); + return mtk_reset_deassert_v2(rcdev, id); } -static const struct reset_control_ops mtk_reset_ops = { - .assert = mtk_reset_assert, - .deassert = mtk_reset_deassert, - .reset = mtk_reset, +static const struct reset_control_ops mtk_reset_ops_v1 = { + .assert = mtk_reset_assert_v1, + .deassert = mtk_reset_deassert_v1, + .reset = mtk_reset_v1, }; -static const struct reset_control_ops mtk_reset_ops_set_clr = { - .assert = mtk_reset_assert_set_clr, - .deassert = mtk_reset_deassert_set_clr, - .reset = mtk_reset_set_clr, +static const struct reset_control_ops mtk_reset_ops_v2 = { + .assert = mtk_reset_assert_v2, + .deassert = mtk_reset_deassert_v2, + .reset = mtk_reset_v2, }; static void mtk_register_reset_controller_common(struct device_node *np, @@ -123,18 +127,18 @@ static void mtk_register_reset_controller_common(struct device_node *np, } } -void mtk_register_reset_controller(struct device_node *np, +void mtk_register_reset_controller_v1(struct device_node *np, unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops); + &mtk_reset_ops_v1); } -void mtk_register_reset_controller_set_clr(struct device_node *np, +void mtk_register_reset_controller_v2(struct device_node *np, unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_set_clr); + &mtk_reset_ops_v2); } MODULE_LICENSE("GPL"); From patchwork Mon Apr 18 13:21:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8775C38A02 for ; Mon, 18 Apr 2022 14:26:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244620AbiDRO3H (ORCPT ); Mon, 18 Apr 2022 10:29:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344445AbiDRO11 (ORCPT ); Mon, 18 Apr 2022 10:27:27 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2D8A52B19; Mon, 18 Apr 2022 06:22:28 -0700 (PDT) X-UUID: 50c7e66351af474da1f771aa3d23058b-20220418 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:46f4d9a7-debe-4fc7-821f-b6ff8e4a6401,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:539c41ef-06b0-4305-bfbf-554bfc9d151a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 50c7e66351af474da1f771aa3d23058b-20220418 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1371199606; Mon, 18 Apr 2022 21:22:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 18 Apr 2022 21:22:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Apr 2022 21:22:22 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 3/7] clk: mediatek: reset: Merge and revise reset register function Date: Mon, 18 Apr 2022 21:21:50 +0800 Message-ID: <20220418132154.7401-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Merge the reset register function of v1 and v2 into one function. - Input the version number to determine which version we will use. - Add return value of reset register function for error handling. - Rename reset register function to "mtk_clk_register_rst_ctrl" Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt2701-eth.c | 8 +++--- drivers/clk/mediatek/clk-mt2701-g3d.c | 8 +++--- drivers/clk/mediatek/clk-mt2701-hif.c | 4 +-- drivers/clk/mediatek/clk-mt2701.c | 8 ++---- drivers/clk/mediatek/clk-mt2712.c | 16 +++++------ drivers/clk/mediatek/clk-mt7622-eth.c | 8 +++--- drivers/clk/mediatek/clk-mt7622-hif.c | 16 +++++------ drivers/clk/mediatek/clk-mt7622.c | 8 ++---- drivers/clk/mediatek/clk-mt7629-eth.c | 8 +++--- drivers/clk/mediatek/clk-mt7629-hif.c | 16 +++++------ drivers/clk/mediatek/clk-mt8135.c | 12 +++++--- drivers/clk/mediatek/clk-mt8173.c | 12 +++++--- drivers/clk/mediatek/clk-mt8183.c | 5 ++-- drivers/clk/mediatek/clk-mtk.h | 13 +++++---- drivers/clk/mediatek/reset.c | 41 +++++++++++++-------------- 15 files changed, 90 insertions(+), 93 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index f3e56a988177..71257714e6a6 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -53,14 +53,14 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static struct platform_driver clk_mt2701_eth_drv = { diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 5a41d4607e77..f878ffba48a9 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -47,14 +47,14 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0xc); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0xc, MTK_RST_V1); } static const struct of_device_id of_match_clk_mt2701_g3d[] = { diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 426a54cb077b..ee53b227e99a 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -57,9 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return 0; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static struct platform_driver clk_mt2701_hif_drv = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 0e103d6735bb..c1100a20c7ed 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -785,9 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller_v1(node, 2, 0x30); - - return 0; + return mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); } static const struct mtk_gate_regs peri0_cg_regs = { @@ -908,9 +906,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller_v1(node, 2, 0x0); - - return 0; + return mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_V1); } #define MT8590_PLL_FMAX (2000 * MHZ) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index e80fc89a5a07..a8cfa85f06a1 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1357,13 +1357,13 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r != 0) + if (r != 0) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return r; + } - mtk_register_reset_controller_v1(node, 2, 0x30); - - return r; + return mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); } static int clk_mt2712_peri_probe(struct platform_device *pdev) @@ -1379,13 +1379,13 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r != 0) + if (r != 0) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return r; + } - mtk_register_reset_controller_v1(node, 2, 0); - - return r; + return mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_V1); } static int clk_mt2712_mcu_probe(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 13f346643e26..33359250fab3 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -77,14 +77,14 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 32855bb489a2..6be894299ae3 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -88,14 +88,14 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static int clk_mt7622_pciesys_init(struct platform_device *pdev) @@ -110,14 +110,14 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static const struct of_device_id of_match_clk_mt7622_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 953e81049957..e8387df38798 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -663,9 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller_v1(node, 1, 0x30); - - return 0; + return mtk_clk_register_rst_ctrl(node, 1, 0x30, MTK_RST_V1); } static int mtk_apmixedsys_init(struct platform_device *pdev) @@ -714,9 +712,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_register_reset_controller_v1(node, 2, 0x0); - - return 0; + return mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_V1); } static const struct of_device_id of_match_clk_mt7622[] = { diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index e47b66c67079..bf1791efe05d 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -87,14 +87,14 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static int clk_mt7629_sgmiisys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 72f261f12e92..23d22c69d47b 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -83,14 +83,14 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static int clk_mt7629_pciesys_init(struct platform_device *pdev) @@ -105,14 +105,14 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + return r; + } - mtk_register_reset_controller_v1(node, 1, 0x34); - - return r; + return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); } static const struct of_device_id of_match_clk_mt7629_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index d649e817b320..68ce0866c5b7 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -555,11 +555,13 @@ static void __init mtk_infrasys_init(struct device_node *node) clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return; + } - mtk_register_reset_controller_v1(node, 2, 0x30); + r = mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -583,11 +585,13 @@ static void __init mtk_pericfg_init(struct device_node *node) &mt8135_clk_lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return; + } - mtk_register_reset_controller_v1(node, 2, 0); + r = mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_V1); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 11becf2f7a9f..fd56dbe8ff95 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -878,11 +878,13 @@ static void __init mtk_infrasys_init(struct device_node *node) clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return; + } - mtk_register_reset_controller_v1(node, 2, 0x30); + r = mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -906,11 +908,13 @@ static void __init mtk_pericfg_init(struct device_node *node) &mt8173_clk_lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); - if (r) + if (r) { pr_err("%s(): could not register clock provider: %d\n", __func__, r); + return; + } - mtk_register_reset_controller_v1(node, 2, 0); + r = mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_V1); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index ac76328c423d..e796af76f960 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1239,9 +1239,8 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller_v2(node, 4, INFRA_RST0_SET_OFFSET); - - return r; + return mtk_clk_register_rst_ctrl(node, 4, + INFRA_RST0_SET_OFFSET, MTK_RST_V2); } static int clk_mt8183_peri_probe(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 601db24a342b..dafdf30fe94e 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -178,6 +178,12 @@ struct mtk_clk_divider { .div_width = _width, \ } +enum mtk_reset_version { + MTK_RST_V1 = 0, + MTK_RST_V2, + MTK_RST_MAX, +}; + int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); @@ -190,11 +196,8 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -void mtk_register_reset_controller_v1(struct device_node *np, - unsigned int num_regs, int regofs); - -void mtk_register_reset_controller_v2(struct device_node *np, - unsigned int num_regs, int regofs); +int mtk_clk_register_rst_ctrl(struct device_node *np, + u32 reg_num, u16 reg_ofs, u8 version); struct mtk_clk_desc { const struct mtk_gate *clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index b1012b0c44d0..2a55e8bf6b28 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -94,51 +94,48 @@ static const struct reset_control_ops mtk_reset_ops_v2 = { .reset = mtk_reset_v2, }; -static void mtk_register_reset_controller_common(struct device_node *np, - unsigned int num_regs, int regofs, - const struct reset_control_ops *reset_ops) +static const struct reset_control_ops *rst_op[MTK_RST_MAX] = { + [MTK_RST_V1] = &mtk_reset_ops_v1, + [MTK_RST_V2] = &mtk_reset_ops_v2, +}; + +int mtk_clk_register_rst_ctrl(struct device_node *np, + u32 reg_num, u16 reg_ofs, u8 version) { struct mtk_reset *data; int ret; struct regmap *regmap; + if (version >= MTK_RST_MAX) { + pr_err("Error version number: %d\n", version); + return -EINVAL; + } + regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); - return; + return -EINVAL; } data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return; + return -ENOMEM; data->regmap = regmap; - data->regofs = regofs; + data->regofs = reg_ofs; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = num_regs * 32; - data->rcdev.ops = reset_ops; + data->rcdev.nr_resets = reg_num * 32; + data->rcdev.ops = rst_op[version]; data->rcdev.of_node = np; ret = reset_controller_register(&data->rcdev); if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); - return; + return -EINVAL; } -} -void mtk_register_reset_controller_v1(struct device_node *np, - unsigned int num_regs, int regofs) -{ - mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_v1); -} - -void mtk_register_reset_controller_v2(struct device_node *np, - unsigned int num_regs, int regofs) -{ - mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_v2); + return 0; } MODULE_LICENSE("GPL"); From patchwork Mon Apr 18 13:21:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A056C38A2C for ; Mon, 18 Apr 2022 14:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245684AbiDRO3S (ORCPT ); Mon, 18 Apr 2022 10:29:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245685AbiDRO1b (ORCPT ); Mon, 18 Apr 2022 10:27:31 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF28252E77; Mon, 18 Apr 2022 06:22:31 -0700 (PDT) X-UUID: a973e584414c4509b95678c1e3048e21-20220418 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:41f795b1-590a-4880-92c7-91b605d39997,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:41f795b1-590a-4880-92c7-91b605d39997,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:54c817f0-da02-41b4-b6df-58f4ccd36682,C OID:28c04104b64a,Recheck:0,SF:13|15|28|17|19|48,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: a973e584414c4509b95678c1e3048e21-20220418 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 433432596; Mon, 18 Apr 2022 21:22:25 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Apr 2022 21:22:23 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 4/7] clk: mediatek: reset: Add reset.h Date: Mon, 18 Apr 2022 21:21:51 +0800 Message-ID: <20220418132154.7401-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a new file "reset.h" to place some definitions for clock reset. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mtk.h | 10 +--------- drivers/clk/mediatek/reset.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 9 deletions(-) create mode 100644 drivers/clk/mediatek/reset.h diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index dafdf30fe94e..dfb0549ceb6c 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -12,6 +12,7 @@ #include #include #include +#include #define MAX_MUX_GATE_BIT 31 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) @@ -178,12 +179,6 @@ struct mtk_clk_divider { .div_width = _width, \ } -enum mtk_reset_version { - MTK_RST_V1 = 0, - MTK_RST_V2, - MTK_RST_MAX, -}; - int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); @@ -196,9 +191,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -int mtk_clk_register_rst_ctrl(struct device_node *np, - u32 reg_num, u16 reg_ofs, u8 version); - struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h new file mode 100644 index 000000000000..0af77531b918 --- /dev/null +++ b/drivers/clk/mediatek/reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __DRV_CLK_MTK_RESET_H +#define __DRV_CLK_MTK_RESET_H + +#include + +enum mtk_reset_version { + MTK_RST_V1 = 0, + MTK_RST_V2, + MTK_RST_MAX, +}; + +int mtk_clk_register_rst_ctrl(struct device_node *np, + u32 reg_num, u16 reg_ofs, u8 version); + +#endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Mon Apr 18 13:21:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 766CFC38A2E for ; Mon, 18 Apr 2022 14:26:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344189AbiDRO3V (ORCPT ); Mon, 18 Apr 2022 10:29:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344473AbiDRO1c (ORCPT ); Mon, 18 Apr 2022 10:27:32 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F40152E76; Mon, 18 Apr 2022 06:22:31 -0700 (PDT) X-UUID: 97e3ac0d6ecc4e8db23002ebc03f733d-20220418 X-UUID: 97e3ac0d6ecc4e8db23002ebc03f733d-20220418 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 394762372; Mon, 18 Apr 2022 21:22:26 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:24 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 Apr 2022 21:22:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Apr 2022 21:22:23 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 5/7] clk: mediatek: reset: Revise structure to control reset register Date: Mon, 18 Apr 2022 21:21:52 +0800 Message-ID: <20220418132154.7401-6-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Replace the structure "struct mtk_reset" to reset.h, and rename it as "mtk_clk_rst_data". We use it to input the resset register data and store reset controller device. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt2701-eth.c | 9 +++- drivers/clk/mediatek/clk-mt2701-g3d.c | 9 +++- drivers/clk/mediatek/clk-mt2701-hif.c | 9 +++- drivers/clk/mediatek/clk-mt2701.c | 19 +++++++- drivers/clk/mediatek/clk-mt2712.c | 19 +++++++- drivers/clk/mediatek/clk-mt7622-eth.c | 9 +++- drivers/clk/mediatek/clk-mt7622-hif.c | 19 +++++++- drivers/clk/mediatek/clk-mt7622.c | 19 +++++++- drivers/clk/mediatek/clk-mt7629-eth.c | 9 +++- drivers/clk/mediatek/clk-mt7629-hif.c | 19 +++++++- drivers/clk/mediatek/clk-mt8135.c | 19 +++++++- drivers/clk/mediatek/clk-mt8173.c | 19 +++++++- drivers/clk/mediatek/clk-mt8183.c | 10 ++++- drivers/clk/mediatek/reset.c | 62 +++++++++++++-------------- drivers/clk/mediatek/reset.h | 12 +++++- 15 files changed, 209 insertions(+), 53 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 71257714e6a6..16fc4a50d513 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -36,6 +36,13 @@ static const struct mtk_gate eth_clks[] = { GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), }; +static struct mtk_clk_rst_data clk_rst_data = { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static const struct of_device_id of_match_clk_mt2701_eth[] = { { .compatible = "mediatek,mt2701-ethsys", }, {} @@ -60,7 +67,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data); } static struct platform_driver clk_mt2701_eth_drv = { diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index f878ffba48a9..bdaa210813f4 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -35,6 +35,13 @@ static const struct mtk_gate g3d_clks[] = { GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; +static struct mtk_clk_rst_data clk_rst_data = { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0xc, +}; + static int clk_mt2701_g3dsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -54,7 +61,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0xc, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data); } static const struct of_device_id of_match_clk_mt2701_g3d[] = { diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index ee53b227e99a..b79cf799d8f6 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -33,6 +33,13 @@ static const struct mtk_gate hif_clks[] = { GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26), }; +static struct mtk_clk_rst_data clk_rst_data = { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static const struct of_device_id of_match_clk_mt2701_hif[] = { { .compatible = "mediatek,mt2701-hifsys", }, {} @@ -57,7 +64,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data); } static struct platform_driver clk_mt2701_hif_drv = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index c1100a20c7ed..a8ac3d11ced6 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -735,6 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; +static struct mtk_clk_rst_data clk_rst_data[] = { + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x30, + }, + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x0, + }, +}; + static struct clk_onecell_data *infra_clk_data; static void __init mtk_infrasys_init_early(struct device_node *node) @@ -785,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - return mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[0]); } static const struct mtk_gate_regs peri0_cg_regs = { @@ -906,7 +921,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - return mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[1]); } #define MT8590_PLL_FMAX (2000 * MHZ) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index a8cfa85f06a1..cc92a54d84ce 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1258,6 +1258,21 @@ static const struct mtk_pll_data plls[] = { 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; +static struct mtk_clk_rst_data clk_rst_data[] = { + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x30, + }, + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x0, + }, +}; + static int clk_mt2712_apmixed_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -1363,7 +1378,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[0]); } static int clk_mt2712_peri_probe(struct platform_device *pdev) @@ -1385,7 +1400,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[1]); } static int clk_mt2712_mcu_probe(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 33359250fab3..2d5e00a3ae5b 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -65,6 +65,13 @@ static const struct mtk_gate sgmii_clks[] = { "ssusb_cdr_fb", 5), }; +static struct mtk_clk_rst_data clk_rst_data = { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7622_ethsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -84,7 +91,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data); } static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 6be894299ae3..a10ecc5b88a1 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -76,6 +76,21 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), }; +static struct mtk_clk_rst_data clk_rst_data[] = { + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, + }, + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, + }, +}; + static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -95,7 +110,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[0]); } static int clk_mt7622_pciesys_init(struct platform_device *pdev) @@ -117,7 +132,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[1]); } static const struct of_device_id of_match_clk_mt7622_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index e8387df38798..cd5181a43132 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -610,6 +610,21 @@ static struct mtk_composite peri_muxes[] = { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; +static struct mtk_clk_rst_data clk_rst_data[] = { + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x30, + }, + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x0, + }, +}; + static int mtk_topckgen_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -663,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - return mtk_clk_register_rst_ctrl(node, 1, 0x30, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[0]); } static int mtk_apmixedsys_init(struct platform_device *pdev) @@ -712,7 +727,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - return mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[1]); } static const struct of_device_id of_match_clk_mt7622[] = { diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index bf1791efe05d..c0ff826a9769 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -76,6 +76,13 @@ static const struct mtk_gate sgmii_clks[2][4] = { } }; +static struct mtk_clk_rst_data clk_rst_data = { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7629_ethsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -94,7 +101,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data); } static int clk_mt7629_sgmiisys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 23d22c69d47b..3b81b7e546a4 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -71,6 +71,21 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), }; +static struct mtk_clk_rst_data clk_rst_data[] = { + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, + }, + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 1, + .reg_ofs = 0x34, + }, +}; + static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -90,7 +105,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[0]); } static int clk_mt7629_pciesys_init(struct platform_device *pdev) @@ -112,7 +127,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_V1); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data[1]); } static const struct of_device_id of_match_clk_mt7629_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 68ce0866c5b7..272a201c13ca 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -514,6 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = { MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; +static struct mtk_clk_rst_data clk_rst_data[] = { + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x30, + }, + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x0, + } +}; + static void __init mtk_topckgen_init(struct device_node *node) { struct clk_onecell_data *clk_data; @@ -561,7 +576,7 @@ static void __init mtk_infrasys_init(struct device_node *node) return; } - r = mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); + r = mtk_clk_register_rst_ctrl(node, &clk_rst_data[0]); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -591,7 +606,7 @@ static void __init mtk_pericfg_init(struct device_node *node) return; } - r = mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_V1); + r = mtk_clk_register_rst_ctrl(node, &clk_rst_data[1]); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index fd56dbe8ff95..56f324948a8c 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -819,6 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = { GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; +static struct mtk_clk_rst_data clk_rst_data[] = { + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x30, + }, + { + .supported = true, + .version = MTK_RST_V1, + .reg_num = 2, + .reg_ofs = 0x0, + } +}; + static struct clk_onecell_data *mt8173_top_clk_data __initdata; static struct clk_onecell_data *mt8173_pll_clk_data __initdata; @@ -884,7 +899,7 @@ static void __init mtk_infrasys_init(struct device_node *node) return; } - r = mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_V1); + r = mtk_clk_register_rst_ctrl(node, &clk_rst_data[0]); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -914,7 +929,7 @@ static void __init mtk_pericfg_init(struct device_node *node) return; } - r = mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_V1); + r = mtk_clk_register_rst_ctrl(node, &clk_rst_data[1]); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index e796af76f960..adf78d882c72 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1153,6 +1153,13 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), }; +static struct mtk_clk_rst_data clk_rst_data = { + .supported = true, + .version = MTK_RST_V2, + .reg_num = 4, + .reg_ofs = INFRA_RST0_SET_OFFSET, +}; + static int clk_mt8183_apmixed_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -1239,8 +1246,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - return mtk_clk_register_rst_ctrl(node, 4, - INFRA_RST0_SET_OFFSET, MTK_RST_V2); + return mtk_clk_register_rst_ctrl(node, &clk_rst_data); } static int clk_mt8183_peri_probe(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 2a55e8bf6b28..709ae54efc18 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -13,49 +13,51 @@ #include "clk-mtk.h" -struct mtk_reset { - struct regmap *regmap; - int regofs; - struct reset_controller_dev rcdev; -}; - static int mtk_reset_assert_v1(struct reset_controller_dev *rcdev, unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + struct mtk_clk_rst_data *data = container_of(rcdev, + struct mtk_clk_rst_data, + rcdev); return regmap_update_bits(data->regmap, - data->regofs + ((id / 32) << 2), + data->reg_ofs + ((id / 32) << 2), BIT(id % 32), ~0); } static int mtk_reset_deassert_v1(struct reset_controller_dev *rcdev, unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + struct mtk_clk_rst_data *data = container_of(rcdev, + struct mtk_clk_rst_data, + rcdev); return regmap_update_bits(data->regmap, - data->regofs + ((id / 32) << 2), + data->reg_ofs + ((id / 32) << 2), BIT(id % 32), 0); } static int mtk_reset_assert_v2(struct reset_controller_dev *rcdev, unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + struct mtk_clk_rst_data *data = container_of(rcdev, + struct mtk_clk_rst_data, + rcdev); return regmap_write(data->regmap, - data->regofs + ((id / 32) << 4), + data->reg_ofs + ((id / 32) << 4), BIT(id % 32)); } static int mtk_reset_deassert_v2(struct reset_controller_dev *rcdev, unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + struct mtk_clk_rst_data *data = container_of(rcdev, + struct mtk_clk_rst_data, + rcdev); return regmap_write(data->regmap, - data->regofs + ((id / 32) << 4) + 0x4, + data->reg_ofs + ((id / 32) << 4) + 0x4, BIT(id % 32)); } @@ -100,14 +102,18 @@ static const struct reset_control_ops *rst_op[MTK_RST_MAX] = { }; int mtk_clk_register_rst_ctrl(struct device_node *np, - u32 reg_num, u16 reg_ofs, u8 version) + struct mtk_clk_rst_data *clk_rst) { - struct mtk_reset *data; - int ret; struct regmap *regmap; + int ret; - if (version >= MTK_RST_MAX) { - pr_err("Error version number: %d\n", version); + if (!clk_rst) { + pr_err("mtk clock reset data is NULL\n"); + return -EINVAL; + } + + if (clk_rst->version >= MTK_RST_MAX) { + pr_err("Error version number: %d\n", clk_rst->version); return -EINVAL; } @@ -117,21 +123,15 @@ int mtk_clk_register_rst_ctrl(struct device_node *np, return -EINVAL; } - data = kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - data->regmap = regmap; - data->regofs = reg_ofs; - data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = reg_num * 32; - data->rcdev.ops = rst_op[version]; - data->rcdev.of_node = np; + clk_rst->regmap = regmap; + clk_rst->rcdev.owner = THIS_MODULE; + clk_rst->rcdev.nr_resets = clk_rst->reg_num * 32; + clk_rst->rcdev.ops = rst_op[clk_rst->version]; + clk_rst->rcdev.of_node = np; - ret = reset_controller_register(&data->rcdev); + ret = reset_controller_register(&clk_rst->rcdev); if (ret) { pr_err("could not register reset controller: %d\n", ret); - kfree(data); return -EINVAL; } diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 0af77531b918..851a29c92440 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -6,6 +6,7 @@ #ifndef __DRV_CLK_MTK_RESET_H #define __DRV_CLK_MTK_RESET_H +#include #include enum mtk_reset_version { @@ -14,7 +15,16 @@ enum mtk_reset_version { MTK_RST_MAX, }; +struct mtk_clk_rst_data { + struct reset_controller_dev rcdev; + struct regmap *regmap; + bool supported; + u8 version; + u32 reg_num; + u16 reg_ofs; +}; + int mtk_clk_register_rst_ctrl(struct device_node *np, - u32 reg_num, u16 reg_ofs, u8 version); + struct mtk_clk_rst_data *clk_rst); #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Mon Apr 18 13:21:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A86CC38A2B for ; Mon, 18 Apr 2022 14:26:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343749AbiDRO3O (ORCPT ); Mon, 18 Apr 2022 10:29:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344457AbiDRO12 (ORCPT ); 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Mon, 18 Apr 2022 21:22:24 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 6/7] clk: mediatek: reset: Add support for unregister reset controller Date: Mon, 18 Apr 2022 21:21:53 +0800 Message-ID: <20220418132154.7401-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a function to unregister reset controller. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/reset.c | 10 ++++++++++ drivers/clk/mediatek/reset.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 709ae54efc18..19f7ac0f8145 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -138,4 +138,14 @@ int mtk_clk_register_rst_ctrl(struct device_node *np, return 0; } +int mtk_clk_unregister_rst_ctrl(struct mtk_clk_rst_data *clk_rst) +{ + if (!clk_rst) + return -EINVAL; + + reset_controller_unregister(&clk_rst->rcdev); + + return 0; +} + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 851a29c92440..86a785630bb6 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -27,4 +27,6 @@ struct mtk_clk_rst_data { int mtk_clk_register_rst_ctrl(struct device_node *np, struct mtk_clk_rst_data *clk_rst); +int mtk_clk_unregister_rst_ctrl(struct mtk_clk_rst_data *clk_rst); + #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Mon Apr 18 13:21:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12816661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B293C47086 for ; Mon, 18 Apr 2022 14:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344166AbiDRO3T (ORCPT ); Mon, 18 Apr 2022 10:29:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245689AbiDRO1b (ORCPT ); Mon, 18 Apr 2022 10:27:31 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3F3052E71; Mon, 18 Apr 2022 06:22:30 -0700 (PDT) X-UUID: 59057909ce474155a8537829dd3a3f4c-20220418 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:87980c2e-94ff-46bd-9dff-f25f7df1f570,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:919c41ef-06b0-4305-bfbf-554bfc9d151a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 59057909ce474155a8537829dd3a3f4c-20220418 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1229306514; Mon, 18 Apr 2022 21:22:26 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 18 Apr 2022 21:22:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 Apr 2022 21:22:24 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH 7/7] clk: mediatek: reset: Add reset support for simple probe/remove Date: Mon, 18 Apr 2022 21:21:54 +0800 Message-ID: <20220418132154.7401-8-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220418132154.7401-1-rex-bc.chen@mediatek.com> References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org - Add a pointer of "mtk_clk_rst_data" to "mtk_clk_desc". - Add register reset function in mtk_clk_simple_probe(). - Add unregister reset function in mtk_clk_simple_remove(). Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mtk.c | 6 ++++++ drivers/clk/mediatek/clk-mtk.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4063261cf56..4ecdf0be26d5 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -453,6 +453,9 @@ int mtk_clk_simple_probe(struct platform_device *pdev) platform_set_drvdata(pdev, clk_data); + if (mcd->rst && mcd->rst->supported) + r = mtk_clk_register_rst_ctrl(node, mcd->rst); + return r; unregister_clks: @@ -468,6 +471,9 @@ int mtk_clk_simple_remove(struct platform_device *pdev) struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); struct device_node *node = pdev->dev.of_node; + if (mcd->rst && mcd->rst->supported) + mtk_clk_unregister_rst_ctrl(mcd->rst); + of_clk_del_provider(node); mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); mtk_free_clk_data(clk_data); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index dfb0549ceb6c..453d12cb57ac 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -194,6 +194,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name, struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; + struct mtk_clk_rst_data *rst; }; int mtk_clk_simple_probe(struct platform_device *pdev);