From patchwork Tue Apr 19 06:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E27BC433FE for ; Tue, 19 Apr 2022 06:58:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=kS6h2BlJpj+QD1S+npebZktj6eX0XgiADAuY7njHfs4=; b=WYMqQGJMczhE0w3mMdJYEdRbnv JjbUFc1bM6wl5RJH/gl5WIBFr9vey9gSwwG5SKFo2Txf9OItNP9p1Re4DLRasJMYhU4Rva0KenXoH 3QMZvT9M+P28xmPrmUfK4vNnAH3xj5ctTteS0KduZNnZKFAMERrLJA9ElSDpqOAElUIGQQljBd8jV 5IR3fKNIKv6xw0pMnyEy59rO9RikcJdqWUr9v1vQTi8D8DqiAN5SVYDEV4rA1DVPNNPXe5b6baNR+ 42gyo4SjqlzvGCSW4qDseAvz0c+itY58H4JXttTYhRvB0xz2IEsEPs/Y7OenUQeJQH8rUWZ7dXb9d 7wRaQPbg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnX-001nNd-IO; Tue, 19 Apr 2022 06:57:15 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnT-001nKH-Fh for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:13 +0000 Received: by mail-pj1-x104a.google.com with SMTP id v9-20020a17090a7c0900b001cb45f88cdcso10160141pjf.0 for ; Mon, 18 Apr 2022 23:57:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=LynBrBVbmgX2+WvKy3gn9dzDYlX9Xj/PYcz4rcGsVrE=; b=pb47lvhf8Z//JVtjhi2MTUEc5TyUZmQkHhhcQiIH1B+gOsCUIuYhHDxjaeh/NBGruD IFmEFY99G7yvkW9vtGaRltiz96b+66iq4Rh7sr0f96aTkCVLuJkcOBCS1PEEciP7ykHd hlc5fldT3vIKA/dNwCChdCoF2CS7MWMzq1LM52cdaoTTb5Y3IHRjI3hiKBSNeKpTBv5m H+TZe3zZK2DqK+dch7uYj+Fxh0hnB/KMIcxzXboPM+2VoxuTshugY0WZKEO4aC+SK9tY xCmxr0oUqVp9JU/RAwQTGYsuLLsXAM3OaFoHv019JtwirkqTeevXBu8XaOfxbb3rJLMb 3v6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=LynBrBVbmgX2+WvKy3gn9dzDYlX9Xj/PYcz4rcGsVrE=; b=lWcMna4/Q6hWvt2TRA5kBpb295ce1TEgE132cjcGOnuegJWuniBvaZNbCIH4M2CQGW u9mJyKp4xoyHAdWcSQBTytSXaHNS1dGrzbIXsLMQtxM8LySb/YzGhiYU1IoHajH1SPp/ PBq86K1+17Nz7BavfI4KWTWsi8TQ0fozC/DJnBK4eF9ALpzNKB0ZLcvpQzqV2F4DMBfL lYB6VLkCEORTz9NTLArW+I2AfBYhGhEX5JFaeShLwFLKtzsvMKNBN7nv54zSzVpX9zRO PRlAePzmAMsY8u4VDWVY9yzOUbuSK1fv3/DKcwQaDRmYjp4ry6MdFwCBYhuoCM5LwAN2 D0Yg== X-Gm-Message-State: AOAM530RLQHS3bFcjgGNIPSRIB4z8nFCoMzj84MsIiRyaOR3zOWi41i0 oe1DoU+H9Ej1R19Td8uI4Oxlmfy7B1o= X-Google-Smtp-Source: ABdhPJxvVqjBxl7SRv/CdH2AWZNC4bLBk9YbOJJ9z+CxzjQ12jRtsxSU318j3YETRdXG3BXKMjWxCiZkbks= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90a:9105:b0:1d2:9e98:7e1e with SMTP id k5-20020a17090a910500b001d29e987e1emr277559pjo.0.1650351426949; Mon, 18 Apr 2022 23:57:06 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:07 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-2-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 01/38] KVM: arm64: Introduce a validation function for an ID register From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235711_554389_E3312529 X-CRM114-Status: GOOD ( 19.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce arm64_check_features(), which does a basic validity checking of an ID register value against the register's limit value, which is generally the host's sanitized value. This function will be used by the following patches to check if an ID register value that userspace tries to set for a guest can be supported on the host. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/cpufeature.h | 1 + arch/arm64/kernel/cpufeature.c | 52 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index c62e7e5e2f0c..7a009d4e18a6 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -634,6 +634,7 @@ void check_local_cpu_capabilities(void); u64 read_sanitised_ftr_reg(u32 id); u64 __read_sysreg_by_encoding(u32 sys_id); +int arm64_check_features(const struct arm64_ftr_bits *ftrp, u64 val, u64 limit); static inline bool cpu_supports_mixed_endian_el0(void) { diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d72c4b4d389c..dbbc69745f22 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3239,3 +3239,55 @@ ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, return sprintf(buf, "Vulnerable\n"); } } + +/** + * arm64_check_features() - Check if a feature register value constitutes + * a subset of features indicated by @limit. + * + * @ftrp: Pointer to an array of arm64_ftr_bits. It must be terminated by + * an item whose width field is zero. + * @val: The feature register value to check + * @limit: The limit value of the feature register + * + * This function will check if each feature field of @val is the "safe" value + * against @limit based on @ftrp[], each of which specifies the target field + * (shift, width), whether or not the field is for a signed value (sign), + * how the field is determined to be "safe" (type), and the safe value + * (safe_val) when type == FTR_EXACT (safe_val won't be used by this + * function when type != FTR_EXACT). Any other fields in arm64_ftr_bits + * won't be used by this function. If a field value in @val is the same + * as the one in @limit, it is always considered the safe value regardless + * of the type. For register fields that are not in @ftrp[], only the value + * in @limit is considered the safe value. + * + * Return: 0 if all the fields are safe. Otherwise, return negative errno. + */ +int arm64_check_features(const struct arm64_ftr_bits *ftrp, u64 val, u64 limit) +{ + u64 mask = 0; + + for (; ftrp->width; ftrp++) { + s64 f_val, f_lim, safe_val; + + f_val = arm64_ftr_value(ftrp, val); + f_lim = arm64_ftr_value(ftrp, limit); + mask |= arm64_ftr_mask(ftrp); + + if (f_val == f_lim) + safe_val = f_val; + else + safe_val = arm64_ftr_safe_value(ftrp, f_val, f_lim); + + if (safe_val != f_val) + return -E2BIG; + } + + /* + * For fields that are not indicated in ftrp, values in limit are the + * safe values. + */ + if ((val & ~mask) != (limit & ~mask)) + return -E2BIG; + + return 0; +} From patchwork Tue Apr 19 06:55:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92FC7C433F5 for ; Tue, 19 Apr 2022 06:58:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ykF2pszCpNbpPGQ3h4pRuvOwNBl6q3Qw0Z1/jqQCAG0=; b=rsxUT5sYJF1GiEOrzVwx2sNj5/ McRHQcTaAbz98nCwjua5tL8kbKQWSIx/IYrj95IBxGZ9tId9GILhRmJJ1vTmUHYaBx2OvHKjnKmhC Hd7QIw/8KIz8SBSiUVhOU505jdLZOjGh5xiMvhI0PwAyjdUzqneMJa7+86RfliK6h/s6w/aen/sx2 Tw9Zq0hPl7LPYsBZIMlcNI5RuVo4QnA5TKe83ZHC3VOWraG0gDRp2NjY4yRUQFKtKz8Rl8AaCZSwX 1Vxehj+U0sYeYWgyUUsik+SwjLtgfcyLutM2UBmWYd7jx4jU2qMWojptsvJ6bmSoyPo3sj8gwGSVb b3mO55vg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnj-001nTz-Qt; Tue, 19 Apr 2022 06:57:28 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnU-001nKT-L0 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:14 +0000 Received: by mail-pj1-x1049.google.com with SMTP id d15-20020a17090a3b0f00b001cd5528627eso927842pjc.1 for ; Mon, 18 Apr 2022 23:57:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=wwGm9HLNSmhYfgL+YutMxTHGZ3Nf+ncKTp/wt1uJeaM=; b=XZHkzRY5NcvY30i9Q68ueVyPZmpJrlgUXM6h2+Ht++CNJhuk9Ab/S5OX4prgP9L0li cLCdb4V+SosvjKsZ6zrGUmpNHG44sSBViRtKLIAtooDqePFK+BHwMTLERxF4xXmGqZJS kd0FA792uE+WB6Ae6g8la4N52N/vvh/GLoKLbCYkjymgCHFVJuM+lJQUCBISgG+vnqQ7 rXX1eO+2zd+2m4tM/P/GrBXZIL0apQkxpz12n35DCTaG5w9/M2MNdx3NjQV5Ch0KdHOt oNM1EjISJ13+fZxQq2W9FTESsyIjid3v+3tFbIRgHvqR1jxfPH1qLJ4Amcp/ws75Fvf1 W5gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=wwGm9HLNSmhYfgL+YutMxTHGZ3Nf+ncKTp/wt1uJeaM=; b=TpT3mZ1SWcnkl3oxUxXcihTjEnGrIze1+UZ3K2Q5MmA4OkRgV4BY4yEIqc+sYlw6cS N8tbvwUeWWkOlYgqI3wVrO4QfGtWYQmiVgqXHpGcq4U92xHP99I3IOF155JCMuYT9oCt EbShNJDm1QvY1pUG3qKV4mBiyuAuCGPJA7tOV5vbkpB3i9BpTvky2C4H5ty1bvFONTsP d9lAg3JbB95z4odUmi+IcaFdG5vhRFBjjdrpdoRuxjASDB5mHXN5iUFkloNuGuwAbZbD wWztynauDd6iPw5R+3ZAYseRTnzY8p5D4uBcqjNuEU/Tr9wk8U6+xdA8iDrQL10yG7pd 3u1Q== X-Gm-Message-State: AOAM532sO9v5Ecf5TT+6nNiCDT9cZ1TDN7X7hop/mBGRga5VrapIHDmM 2ttzcsJsoLE0bab0NIOVVkvYD9Rvq2U= X-Google-Smtp-Source: ABdhPJxn5yJvOYBVq+YRQNQ/f8W+joFEc2Uin92mJVYL2mkjO+sikRGNfunowGA6J8dBpaXEP7qKj3+ikfM= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:2d7:b0:508:383e:249e with SMTP id b23-20020a056a0002d700b00508383e249emr16114091pft.71.1650351428925; Mon, 18 Apr 2022 23:57:08 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:08 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-3-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 02/38] KVM: arm64: Save ID registers' sanitized value per guest From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235712_713684_A795FDA7 X-CRM114-Status: GOOD ( 22.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce id_regs[] in kvm_arch as a storage of guest's ID registers, and save ID registers' sanitized value in the array at KVM_CREATE_VM. Use the saved ones when ID registers are read by the guest or userspace (via KVM_GET_ONE_REG). Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 11 +++++ arch/arm64/kvm/arm.c | 1 + arch/arm64/kvm/sys_regs.c | 81 +++++++++++++++++++++++++------ 3 files changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 94a27a7520f4..fc836df84748 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -150,6 +150,15 @@ struct kvm_arch { u8 pfr0_csv2; u8 pfr0_csv3; + + /* + * Save ID registers for the guest in id_regs[]. + * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it + * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. + */ +#define KVM_ARM_ID_REG_MAX_NUM 56 +#define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id)) + u64 id_regs[KVM_ARM_ID_REG_MAX_NUM]; }; struct kvm_vcpu_fault_info { @@ -775,6 +784,8 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, struct kvm_arm_copy_mte_tags *copy_tags); +void set_default_id_regs(struct kvm *kvm); + /* Guest/host FPSIMD coordination helpers */ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 523bc934fe2f..04312f7ee0da 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -156,6 +156,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) kvm->arch.max_vcpus = kvm_arm_default_max_vcpus(); set_default_spectre(kvm); + set_default_id_regs(kvm); return ret; out_free_stage2_pgd: diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7b45c040cc27..5b813a0b7b1c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -33,6 +33,8 @@ #include "trace.h" +static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id); + /* * All of this file is extremely similar to the ARM coproc.c, but the * types are different. My gut feeling is that it should be pretty @@ -277,7 +279,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + u64 val = read_id_reg_with_encoding(vcpu, SYS_ID_AA64MMFR1_EL1); u32 sr = reg_to_encoding(r); if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { @@ -1102,17 +1104,20 @@ static bool access_arch_timer(struct kvm_vcpu *vcpu, return true; } -/* Read a sanitised cpufeature ID register by sys_reg_desc */ -static u64 read_id_reg(const struct kvm_vcpu *vcpu, - struct sys_reg_desc const *r, bool raz) +/* + * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is + * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8. + */ +static bool is_id_reg(u32 id) { - u32 id = reg_to_encoding(r); - u64 val; - - if (raz) - return 0; + return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && + sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && + sys_reg_CRm(id) < 8); +} - val = read_sanitised_ftr_reg(id); +static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) +{ + u64 val = vcpu->kvm->arch.id_regs[IDREG_IDX(id)]; switch (id) { case SYS_ID_AA64PFR0_EL1: @@ -1167,6 +1172,14 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, return val; } +static u64 read_id_reg(const struct kvm_vcpu *vcpu, + struct sys_reg_desc const *r, bool raz) +{ + u32 id = reg_to_encoding(r); + + return raz ? 0 : read_id_reg_with_encoding(vcpu, id); +} + static unsigned int id_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -1267,9 +1280,8 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, /* * cpufeature ID register user accessors * - * For now, these registers are immutable for userspace, so no values - * are stored, and for set_id_reg() we don't allow the effective value - * to be changed. + * For now, these registers are immutable for userspace, so for set_id_reg() + * we don't allow the effective value to be changed. */ static int __get_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, void __user *uaddr, @@ -1882,8 +1894,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, if (p->is_write) { return ignore_write(vcpu, p); } else { - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + u64 dfr = read_id_reg_with_encoding(vcpu, SYS_ID_AA64DFR0_EL1); + u64 pfr = read_id_reg_with_encoding(vcpu, SYS_ID_AA64PFR0_EL1); u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | @@ -2895,3 +2907,42 @@ void kvm_sys_reg_table_init(void) /* Clear all higher bits. */ cache_levels &= (1 << (i*3))-1; } + +/* + * Set the guest's ID registers that are defined in sys_reg_descs[] + * with ID_SANITISED() to the host's sanitized value. + */ +void set_default_id_regs(struct kvm *kvm) +{ + int i; + u32 id; + const struct sys_reg_desc *rd; + u64 val; + struct sys_reg_params params = { + Op0(sys_reg_Op0(SYS_ID_PFR0_EL1)), + Op1(sys_reg_Op1(SYS_ID_PFR0_EL1)), + CRn(sys_reg_CRn(SYS_ID_PFR0_EL1)), + CRm(sys_reg_CRm(SYS_ID_PFR0_EL1)), + Op2(sys_reg_Op2(SYS_ID_PFR0_EL1)), + }; + + /* + * Find the first entry of the ID register (ID_PFR0_EL1) from + * sys_reg_descs table, and walk through only the ID register + * entries in the table. + */ + rd = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); + for (i = 0; i < KVM_ARM_ID_REG_MAX_NUM; i++, rd++) { + id = reg_to_encoding(rd); + if (WARN_ON_ONCE(!is_id_reg(id))) + /* Shouldn't happen */ + continue; + + if (rd->access != access_id_reg) + /* Hidden or reserved ID register */ + continue; + + val = read_sanitised_ftr_reg(id); + kvm->arch.id_regs[IDREG_IDX(id)] = val; + } +} From patchwork Tue Apr 19 06:55:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817494 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A653C433EF for ; Tue, 19 Apr 2022 06:59:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Vz9mYjl9jYNQ9GCr50AYIfmP5xvkcfj+R2tgEJWRteM=; b=gz5+myHkd4MyksTDsq4WVfrwKv RRFjuR5aEDS10qBe+aaoX8jKW2tyfvQ7cflEmfxyK+MeaKD4n805CI7cl43Emp4QtTIuJpptXxdfF 5yA7gQjiDditJko9Q3P18Y6pkVbLSsRuSfzNFJi+thiA2buHuscDkBvej+OGmryA/dOwO7/tww0Hh F0tVsq+F0xRJXDZeo8dg7VvXPlm3z9SPDHhVZkblbJr8zUWCQQx6VxHq32MsvQ3DOQHMsJdQ+jhWJ SUhjFgjdTeX1bcvp3qE4Yi+MAmQH2WSSwcwrT4FEfUXccWr6bYzHYScpDPZZSfVpJ/ihNUOAUOpMt O1EKYSiQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoX-001ntI-6Y; Tue, 19 Apr 2022 06:58:17 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnV-001nL1-50 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:15 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id x7-20020a056902050700b00641671dc5d0so14079239ybs.18 for ; Mon, 18 Apr 2022 23:57:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=KS/wIIJ7uM3yRJfC0p0anyF55IOjLEEQRah7lyLn2og=; b=pi46jYG8e8DWlS5vsuaGpm4q+O+GL53YTvZkLbMuftAu5GXIzWzk5CVuyrf1XF9eJ9 ++2oSNEKKUu9cz60xNWUWV1HBhSKnwJjlYTlU7LrIL3x+kc87hoAebkMbDE66dJuTR7x 6HY86ZbiimWgPPvk3OswZbPJ3NAOtAwwwEVcPrQLZh8zbaXbDazgLfioljLnaqped+Q8 Zluv9RdeOa5Fv4xCjh48HgtW1Ndm4l4bsjj+5nZETZ/DK2TCsVN/QTxxbBL1nvqFPuto QLaSbncWLLAfj29CKMU55tfytj9BI7o6khBtZZx0Y3H8yMP1PU78EJRihlblluNkRDCT puXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=KS/wIIJ7uM3yRJfC0p0anyF55IOjLEEQRah7lyLn2og=; b=vbYEBjU869fB/tktWbDbyb0IAirEb82wlJ5MKKbHwSn2AVsGrA0aKDubh6UhfSb7IZ TrZKpZltbhDUGNeRpMrvO7IZT64GspXIhP7USsJgPL8I1pAQCyaHOx+nWo1pBdQvkLP4 hQAjjXDS4KHuxptBYvGS1upNwft88jeuxt2bIprhHeSNgooyIqwXneQUch1kuescwnUi 5sg3wEHi5eGzATXlx69O7GMad+FtXoUkET8KDs2oNkXPTTd0BRwsmko+CA1hrzqc0hK2 hPJkMcFyHDkx9S4YT4HifJ4i0IpE+7J+qpFS4mcca2dT4+KydT29aAGaxbkLZGm29C+h rjKw== X-Gm-Message-State: AOAM533o1Q4M8jW7ZPFKhSDGWZsurBqJ8YHxCXEFxbnT7aBWT6dsvNep 1EJTrvUxUuOHJr+GRoW3aU8Jn9OGK/8= X-Google-Smtp-Source: ABdhPJwlHiTAOkInHI+UkF/bI/+q1ncsfqZcs+GYTID72n/O+fP2xR9PIGz73byjxBPqM4WrghkUY7tVmcU= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a25:52c3:0:b0:645:35f9:b55 with SMTP id g186-20020a2552c3000000b0064535f90b55mr2681156ybb.307.1650351430454; Mon, 18 Apr 2022 23:57:10 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:09 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-4-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 03/38] KVM: arm64: Introduce struct id_reg_desc From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235713_252079_2ADB7A96 X-CRM114-Status: GOOD ( 40.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch lays the groundwork to make ID registers writable. Introduce struct id_reg_desc for an ID register to manage the register specific control of its value for the guest, and provide set of functions commonly used for ID registers to make them writable. Use the id_reg_desc to do register specific initialization, validation of the ID register, etc. The id_reg_desc has reg_desc field (struct sys_reg_desc), which will be used instead of sys_reg_desc in sys_reg_descs[] for ID registers in the following patches (and then the entries in sys_reg_descs[] will be removed). At present, changing an ID register from userspace is allowed only if the ID register has the id_reg_desc, but that will be changed by the following patches. No ID register has the id_reg_desc yet, and the following patches will add them for all the ID registers currently in sys_reg_descs[]. kvm_set_id_reg_feature(), which is introduced in this patch, is going to be used by the following patch outside from sys_regs.c when an ID register field needs to be updated. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/sysreg.h | 3 +- arch/arm64/kvm/sys_regs.c | 313 ++++++++++++++++++++++++++++-- 3 files changed, 300 insertions(+), 17 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index fc836df84748..a43fddd58e68 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -785,6 +785,7 @@ long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, struct kvm_arm_copy_mte_tags *copy_tags); void set_default_id_regs(struct kvm *kvm); +int kvm_set_id_reg_feature(struct kvm *kvm, u32 id, u8 field_shift, u8 fval); /* Guest/host FPSIMD coordination helpers */ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index fbf5f8bb9055..3d860108661b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1234,9 +1234,10 @@ #define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT) #define ARM64_FEATURE_FIELD_BITS 4 +#define ARM64_FEATURE_FIELD_MASK GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0) /* Create a mask for the feature bits of the specified feature. */ -#define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT)) +#define ARM64_FEATURE_MASK(x) (ARM64_FEATURE_FIELD_MASK << x##_SHIFT) #ifdef __ASSEMBLY__ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5b813a0b7b1c..30adc19e4619 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -34,6 +34,7 @@ #include "trace.h" static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id); +static inline struct id_reg_desc *get_id_reg_desc(u32 id); /* * All of this file is extremely similar to the ARM coproc.c, but the @@ -269,6 +270,112 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, return read_zero(vcpu, p); } +/* + * Number of entries in id_reg_desc's ftr_bits[] (Number of 4 bits fields + * in 64 bit register + 1 entry for a terminator entry). + */ +#define FTR_FIELDS_NUM 17 + +struct id_reg_desc { + const struct sys_reg_desc reg_desc; + + /* + * Limit value of the register for a vcpu. The value is the sanitized + * system value with bits set/cleared for unsupported features for the + * guest. + */ + u64 vcpu_limit_val; + + /* Fields that are not validated by arm64_check_features. */ + u64 ignore_mask; + + /* An optional initialization function of the id_reg_desc */ + void (*init)(struct id_reg_desc *id_reg); + + /* + * This is an optional ID register specific validation function. When + * userspace tries to set the ID register, arm64_check_features() + * will check if the requested value indicates any features that cannot + * be supported by KVM on the host. But, some ID register fields need + * a special checking, and this function can be used for such fields. + * e.g. When SVE is configured for a vCPU by KVM_ARM_VCPU_INIT, + * ID_AA64PFR0_EL1.SVE shouldn't be set to 0 for the vCPU. + * The validation function for ID_AA64PFR0_EL1 could be used to check + * the field is consistent with SVE configuration. + */ + int (*validate)(struct kvm_vcpu *vcpu, const struct id_reg_desc *id_reg, + u64 val); + + /* + * Return a bitmask of the vCPU's ID register fields that are not + * synced with saved (per VM) ID register value, which usually + * indicates opt-in CPU features that are not configured for the vCPU. + * ID registers are saved per VM, but some opt-in CPU features can + * be configured per vCPU. The saved (per VM) values for such + * features are for vCPUs with the features (and zero for + * vCPUs without the features). + * Return value of this function is used to handle such fields + * for per vCPU ID register read/write request with saved per VM + * ID register. See the __write_id_reg's comment for more detail. + */ + u64 (*vcpu_mask)(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg); + + /* + * Used to validate the ID register values with arm64_check_features(). + * The last item in the array must be terminated by an item whose + * width field is zero as that is expected by arm64_check_features(). + */ + struct arm64_ftr_bits ftr_bits[FTR_FIELDS_NUM]; +}; + +static void id_reg_desc_init(struct id_reg_desc *id_reg) +{ + u32 id = reg_to_encoding(&id_reg->reg_desc); + u64 val = read_sanitised_ftr_reg(id); + + id_reg->vcpu_limit_val = val; + if (id_reg->init) + id_reg->init(id_reg); + + /* + * id_reg->init() might update id_reg->vcpu_limit_val. + * Make sure that id_reg->vcpu_limit_val, which will be the default + * register value for guests, is a safe value to use for guests + * on the host. + */ + WARN_ON_ONCE(arm64_check_features(id_reg->ftr_bits, + id_reg->vcpu_limit_val, val)); +} + +static int validate_id_reg(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + u64 limit, tmp_val; + int err; + + limit = id_reg->vcpu_limit_val; + + /* + * Replace the fields that are indicated in ignore_mask with + * the value in the limit to not have arm64_check_features() + * check the field in @val. + */ + tmp_val = val & ~id_reg->ignore_mask; + tmp_val |= (limit & id_reg->ignore_mask); + + /* Check if the value indicates any feature that is not in the limit. */ + err = arm64_check_features(id_reg->ftr_bits, tmp_val, limit); + if (err) + return err; + + if (id_reg && id_reg->validate) + /* Run the ID register specific validity check. */ + err = id_reg->validate(vcpu, id_reg, val); + + return err; +} + /* * ARMv8.1 mandates at least a trivial LORegion implementation, where all the * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 @@ -1115,10 +1222,107 @@ static bool is_id_reg(u32 id) sys_reg_CRm(id) < 8); } +static u64 read_kvm_id_reg(struct kvm *kvm, u32 id) +{ + return kvm->arch.id_regs[IDREG_IDX(id)]; +} + +static int __modify_kvm_id_reg(struct kvm *kvm, u32 id, u64 val, + u64 preserve_mask) +{ + u64 old, new; + + lockdep_assert_held(&kvm->lock); + + old = kvm->arch.id_regs[IDREG_IDX(id)]; + + /* Preserve the value at the bit position set in preserve_mask */ + new = old & preserve_mask; + new |= (val & ~preserve_mask); + + /* Don't allow to modify ID register value after KVM_RUN on any vCPUs */ + if (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &kvm->arch.flags) && + new != old) + return -EBUSY; + + WRITE_ONCE(kvm->arch.id_regs[IDREG_IDX(id)], new); + + return 0; +} + +static int modify_kvm_id_reg(struct kvm *kvm, u32 id, u64 val, + u64 preserve_mask) +{ + int ret; + + mutex_lock(&kvm->lock); + ret = __modify_kvm_id_reg(kvm, id, val, preserve_mask); + mutex_unlock(&kvm->lock); + + return ret; +} + +static int write_kvm_id_reg(struct kvm *kvm, u32 id, u64 val) +{ + return modify_kvm_id_reg(kvm, id, val, 0); +} + +/* + * KVM basically forces all vCPUs of the guest to have a uniform value for + * each ID register (it means KVM_SET_ONE_REG for a vCPU affects all + * the vCPUs of the guest), and the id_regs[] of kvm_arch holds values + * of ID registers for the guest. However, there is an exception for + * ID register fields corresponding to CPU features that can be + * configured per vCPU by KVM_ARM_VCPU_INIT, or etc (e.g. PMUv3, SVE, etc). + * For such fields, all vCPUs that have the feature will have a non-zero + * uniform value, which can be updated by userspace, but the vCPUs that + * don't have the feature will have zero for the fields. + * Values that @id_regs holds are for vCPUs that have such features. So, + * to get the ID register value for a vCPU that doesn't have those features, + * the corresponding fields in id_regs[] needs to be cleared. + * A bitmask of the fields are provided by id_reg_desc's vcpu_mask(), and + * __write_id_reg() and __read_id_reg() take care of those fields using + * the bitmask. + */ +static int __write_id_reg(struct kvm_vcpu *vcpu, + struct id_reg_desc *id_reg, u64 val) +{ + u64 mask = 0; + u32 id = reg_to_encoding(&id_reg->reg_desc); + + if (id_reg->vcpu_mask) + mask = id_reg->vcpu_mask(vcpu, id_reg); + + /* + * Update the ID register for the guest with @val, except for fields + * that are set in the mask, which indicates fields for opt-in + * features that are not configured for the vCPU. + */ + return modify_kvm_id_reg(vcpu->kvm, id, val, mask); +} + +static u64 __read_id_reg(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg) +{ + u32 id = reg_to_encoding(&id_reg->reg_desc); + u64 val = read_kvm_id_reg(vcpu->kvm, id); + + if (id_reg && id_reg->vcpu_mask) + /* Clear fields for opt-in features that are not configured. */ + val &= ~(id_reg->vcpu_mask(vcpu, id_reg)); + + return val; +} + static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) { - u64 val = vcpu->kvm->arch.id_regs[IDREG_IDX(id)]; + u64 val; + const struct id_reg_desc *id_reg = get_id_reg_desc(id); + + if (id_reg) + return __read_id_reg(vcpu, id_reg); + val = read_kvm_id_reg(vcpu->kvm, id); switch (id) { case SYS_ID_AA64PFR0_EL1: if (!vcpu_has_sve(vcpu)) @@ -1175,9 +1379,7 @@ static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r, bool raz) { - u32 id = reg_to_encoding(r); - - return raz ? 0 : read_id_reg_with_encoding(vcpu, id); + return raz ? 0 : read_id_reg_with_encoding(vcpu, reg_to_encoding(r)); } static unsigned int id_visibility(const struct kvm_vcpu *vcpu, @@ -1277,12 +1479,7 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return 0; } -/* - * cpufeature ID register user accessors - * - * For now, these registers are immutable for userspace, so for set_id_reg() - * we don't allow the effective value to be changed. - */ +/* cpufeature ID register user accessors */ static int __get_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, void __user *uaddr, bool raz) @@ -1293,11 +1490,32 @@ static int __get_id_reg(const struct kvm_vcpu *vcpu, return reg_to_user(uaddr, &val, id); } -static int __set_id_reg(const struct kvm_vcpu *vcpu, +/* + * Check if the given id indicates AArch32 ID register encoding. + */ +static bool is_aarch32_id_reg(u32 id) +{ + u32 crm, op2; + + if (!is_id_reg(id)) + return false; + + crm = sys_reg_CRm(id); + op2 = sys_reg_Op2(id); + if (crm == 1 || crm == 2 || (crm == 3 && (op2 != 3 && op2 != 7))) + /* AArch32 ID register */ + return true; + + return false; +} + +static int __set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, void __user *uaddr, bool raz) { const u64 id = sys_reg_to_index(rd); + u32 encoding = reg_to_encoding(rd); + struct id_reg_desc *id_reg; int err; u64 val; @@ -1305,11 +1523,33 @@ static int __set_id_reg(const struct kvm_vcpu *vcpu, if (err) return err; - /* This is what we mean by invariant: you can't change it. */ - if (val != read_id_reg(vcpu, rd, raz)) + if (val == read_id_reg(vcpu, rd, raz)) + /* The value is same as the current value. Nothing to do. */ + return 0; + + /* Don't allow to modify the register's value if the register is raz. */ + if (raz) return -EINVAL; - return 0; + /* + * Don't allow to modify the register's value if the register doesn't + * have the id_reg_desc. + */ + id_reg = get_id_reg_desc(encoding); + if (!id_reg) + return -EINVAL; + + /* + * Skip the validation of AArch32 ID registers if the system doesn't + * 32bit EL0 (their value are UNKNOWN). + */ + if (system_supports_32bit_el0() || !is_aarch32_id_reg(encoding)) { + err = validate_id_reg(vcpu, id_reg, val); + if (err) + return err; + } + + return __write_id_reg(vcpu, id_reg, val); } static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, @@ -2872,6 +3112,8 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) return write_demux_regids(uindices); } +static void id_reg_desc_init_all(void); + void kvm_sys_reg_table_init(void) { unsigned int i; @@ -2906,6 +3148,43 @@ void kvm_sys_reg_table_init(void) break; /* Clear all higher bits. */ cache_levels &= (1 << (i*3))-1; + + id_reg_desc_init_all(); +} + +/* + * Update the ID register's field with @fval for the guest. + * The caller is expected to hold the kvm->lock. + * This will not fail unless any vCPUs in the guest have started. + */ +int kvm_set_id_reg_feature(struct kvm *kvm, u32 id, u8 field_shift, u8 fval) +{ + u64 val = ((u64)fval & ARM64_FEATURE_FIELD_MASK) << field_shift; + u64 preserve_mask = ~(ARM64_FEATURE_FIELD_MASK << field_shift); + + return __modify_kvm_id_reg(kvm, id, val, preserve_mask); +} + +/* A table for ID registers's information. */ +static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = {}; + +static inline struct id_reg_desc *get_id_reg_desc(u32 id) +{ + return id_reg_desc_table[IDREG_IDX(id)]; +} + +static void id_reg_desc_init_all(void) +{ + int i; + struct id_reg_desc *id_reg; + + for (i = 0; i < ARRAY_SIZE(id_reg_desc_table); i++) { + id_reg = (struct id_reg_desc *)id_reg_desc_table[i]; + if (!id_reg) + continue; + + id_reg_desc_init(id_reg); + } } /* @@ -2918,6 +3197,7 @@ void set_default_id_regs(struct kvm *kvm) u32 id; const struct sys_reg_desc *rd; u64 val; + struct id_reg_desc *idr; struct sys_reg_params params = { Op0(sys_reg_Op0(SYS_ID_PFR0_EL1)), Op1(sys_reg_Op1(SYS_ID_PFR0_EL1)), @@ -2942,7 +3222,8 @@ void set_default_id_regs(struct kvm *kvm) /* Hidden or reserved ID register */ continue; - val = read_sanitised_ftr_reg(id); - kvm->arch.id_regs[IDREG_IDX(id)] = val; + idr = get_id_reg_desc(id); + val = idr ? idr->vcpu_limit_val : read_sanitised_ftr_reg(id); + WARN_ON_ONCE(write_kvm_id_reg(kvm, id, val)); } } From patchwork Tue Apr 19 06:55:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F003C433FE for ; Tue, 19 Apr 2022 06:58:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=IoRxG6K33LmDPSvaiOb+ArvCXzV5ajXhp+FWbG9odt8=; b=qjRyb0WhQOr67mJoJnQXEt8rLE Px/v/0qspiR9k0i/+M03hscj/itKlBnuyJ51D94t+OQhLjzEC6QCWOk2vhuZBj/Lu5vcr6pUI2gdy kwjgZmT/hJb3G4knBnC0C+vBmMV2Peu8DwzQzvYgy+E00djADLuJO1LKmR1R0L3aHGkU7YWJ2BpPk VEg3cb8R/yGPFnKEwxtwAgPQcAadQUKeOvzqVHPdbMayzy/knVtzBboyQYlayIImRff6bBtFgZT0Z R7CPa2TxfaIrAHTOSFZxPtGF02JJ39xbiPY30oAXQJfAlmtG/0SXINwk8aTQFVCrmWZSz2wW9ZVit Zq7QY97w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghny-001nbS-5V; Tue, 19 Apr 2022 06:57:42 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnV-001nM9-ME for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:15 +0000 Received: by mail-pl1-x649.google.com with SMTP id y12-20020a17090322cc00b001590b19fb1fso2166165plg.16 for ; Mon, 18 Apr 2022 23:57:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=VJImZSIZ+gG1OFTvYyrxAjCUBTqUqO7tRcl+ZvmmrQU=; b=fY034672N11uX9UN7COg34VjlKUqAo7dFya/wOHPBEs1jzO5xKlaqEmIenpptQfc3Z UO7slba7gfWUWNvpAFkm02q8WMmVD74ZeN9mCnYt2u2qXBaNDY4yoKJ/OuV+Z3lqdmmz W278iSjt45hIPJ+VKUtTyZeNHoo6fojiDaHX4KiwL8XTeN7iX5Gc8A/VbEX/dtjLYPWh ToYtzkMaDBmaPztTc/CagS+36DIDmgQw3Pry0pzFNvmBUmLwIjP/b6OljEat0qNHn/Qe uQMzg7jaZcRaQlvLVne9u6lapGzQYrEkbFM1BUCEeNf2SItPlzY0vnkCiPTUt9nqpRf2 xpig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=VJImZSIZ+gG1OFTvYyrxAjCUBTqUqO7tRcl+ZvmmrQU=; b=BOTkyZs1EMC5iIHeO5SAWy3ZysUbQQPwyeVbfzlnLFxlnl8gQEJrD7FDUwH1OJiPYQ Qgj+DkgTOiGFefXwANkdIi8Qhjf2Amul2rTkEqPzkUA5yaXoHzQgYWoVkqIzzf/tZIqZ bqwH71LLVvFSYJs4dMgkphQiajFvHJklovEW+tkoOuCkdvqhHFqEvmubynma5n07MY/S 08nUra3TY8pCVGB+/xdIWzBPQg8cBPP0xjudFaWCN2l9wdIl0EsfjpVn4Afoua70OzfQ Nh1YfM5q2NigYyfxjzO4IS7k1c/wV160i2RsxHttlK+vnod40pDH9hRDeTRCWNROHL+C 24Wg== X-Gm-Message-State: AOAM5339WAzjE6Ggo7ceTpnnOFEH6L8C4ouKdKZVfK6sD1CX5Lixnp63 lAjS82wLYnyn3FQWzUJ0+UBTILRUmCs= X-Google-Smtp-Source: ABdhPJwcF9IGP+oXjWqN513CFHPTbOhEPIcFqBvtuNUAEogsKCaN3cLS4dsvrgirt3TnfNpD+Muf6CEieGo= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:10d0:b0:4f7:5af4:47b6 with SMTP id d16-20020a056a0010d000b004f75af447b6mr16187254pfu.6.1650351431964; Mon, 18 Apr 2022 23:57:11 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:10 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-5-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 04/38] KVM: arm64: Generate id_reg_desc's ftr_bits at KVM init when needed From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235713_793116_C445E2C6 X-CRM114-Status: GOOD ( 18.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Most of entries in ftr_bits[] of id_reg_desc will be UNSIGNED+LOWER_SAFE. Use that as the default arm64_ftr_bits for any entries that are not statically defined in ftr_bits[] so that we don't have to statically define every single UNSIGNED+LOWER_SAFE entry. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 30adc19e4619..b19e14a1206a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -35,6 +35,7 @@ static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id); static inline struct id_reg_desc *get_id_reg_desc(u32 id); +static void id_reg_desc_init_ftr(struct id_reg_desc *idr); /* * All of this file is extremely similar to the ARM coproc.c, but the @@ -325,6 +326,8 @@ struct id_reg_desc { * Used to validate the ID register values with arm64_check_features(). * The last item in the array must be terminated by an item whose * width field is zero as that is expected by arm64_check_features(). + * Entries that are not statically defined will be generated as + * UNSIGNED+LOWER_SAFE entries during KVM's initialization. */ struct arm64_ftr_bits ftr_bits[FTR_FIELDS_NUM]; }; @@ -335,6 +338,9 @@ static void id_reg_desc_init(struct id_reg_desc *id_reg) u64 val = read_sanitised_ftr_reg(id); id_reg->vcpu_limit_val = val; + + id_reg_desc_init_ftr(id_reg); + if (id_reg->init) id_reg->init(id_reg); @@ -3173,6 +3179,54 @@ static inline struct id_reg_desc *get_id_reg_desc(u32 id) return id_reg_desc_table[IDREG_IDX(id)]; } +void kvm_ftr_bits_set_default(u8 shift, struct arm64_ftr_bits *ftrp) +{ + ftrp->sign = FTR_UNSIGNED; + ftrp->type = FTR_LOWER_SAFE; + ftrp->shift = shift; + ftrp->width = ARM64_FEATURE_FIELD_BITS; + ftrp->safe_val = 0; +} + +/* + * Check to see if the id_reg's ftr_bits have statically defined entries + * for all fields of the ID register, and generate the default ones + * (FTR_UNSIGNED+FTR_LOWER_SAFE) for any missing fields. + */ +static void id_reg_desc_init_ftr(struct id_reg_desc *idr) +{ + struct arm64_ftr_bits *ftrp = idr->ftr_bits; + int index = 0; + int shift; + u64 ftr_mask; + u64 mask = 0; + + /* Create a mask for fields that are statically defined */ + for (index = 0; ftrp->width != 0; index++, ftrp++) { + ftr_mask = arm64_ftr_mask(ftrp); + WARN_ON_ONCE(mask & ftr_mask); + mask |= ftr_mask; + } + + if (mask == -1UL) + /* All fields are statically defined */ + return; + + /* The 'index' indicates the first unused index of ftr_bits */ + for (shift = 0; shift < 64; shift += ARM64_FEATURE_FIELD_BITS) { + /* Check if there is an existing ftrp for the field */ + ftr_mask = ARM64_FEATURE_FIELD_MASK << shift; + if (mask & ftr_mask) + continue; + + /* Generate the default arm64_ftr_bits for the field */ + kvm_ftr_bits_set_default(shift, &idr->ftr_bits[index++]); + mask |= ftr_mask; + } + + WARN_ON((mask != -1UL) || (index != (FTR_FIELDS_NUM - 1))); +} + static void id_reg_desc_init_all(void) { int i; From patchwork Tue Apr 19 06:55:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09891C43217 for ; Tue, 19 Apr 2022 06:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=zaOFNhTAbH/PSXrxsZmyfV3Z28zcRkAiFS+1+3LxvxM=; b=xe0QVV//Mb2ZYtya0QCVFFUfKQ FXWDrT/6jz0GMli2wvUq3VipO5KDsJIrU1n+Xn/6Py9ZsZhU2yHJi3cPAvaoenCStmMWJFZUOXi8y Sjy6YlyHoYXAJyRMixk08XoLA2CHhfK7DV8zaoxzD6/j76TjimrnZAYGT0F1efFtigX5sltr7m6Hy iMUiTDTywgBnHtCokwxlvu9TJ/C//3bHIiATdOLs+jhMFQ6jSo4e1mbRcqkGYFysvyaxtclfw1gtH ghlp9PTcBkC9SrKDhug9fAQVWbDCdCTbHAIQPSPxUKICRjoxDYV9ACuABtj7S28l/4ZfYia2wb+aX OOUo2NMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoq-001o5x-3j; Tue, 19 Apr 2022 06:58:36 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnX-001nNI-Az for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:16 +0000 Received: by mail-pj1-x104a.google.com with SMTP id pb1-20020a17090b3c0100b001d2b09b6185so1043887pjb.2 for ; Mon, 18 Apr 2022 23:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=DnB6mkT71yKfiG5xjrOUttE90Hmb51/VYCnn9fFtof4=; b=ZbU4DI8LNyuRtCFqPLEdyNdwHwoaTlUuA0oTrVeKfChCv8RdXwbrsDjHZp/0f6FQnP PZLE4A7NgUR6x0oMr5exTueSSuVho7obJ7dNzlyMTCr7HwLw6BKGJra91wUoMx3wlcb6 bSQgSXwurkj3VYnxA575UdfzsJ87lzw9afbZ03AYvGQBQjegBxyQqcW+BA/oZie6o1mF Yh4sHj8EegW8bDGiPBecdj0wvXoudVP1mUn1WVnV9+uzP0TsHZWRMOL2i/nuqQfZnjxy xbyWDd7Or3+beb4xI3uCxytRvzji52R4qg7KmFzoyO/a+cO5Ag0fHz60VLe8FWFkTWw9 Li0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=DnB6mkT71yKfiG5xjrOUttE90Hmb51/VYCnn9fFtof4=; b=hwGiNmnOho6EVkRlsu+0SbGC1bajCMf7roPge/SLVndyf3dIQhaThI9erzUW7YgpZN MgZHVujN2bWe/mpRqf2r6O/pxfDRol5LWAxqYNb4DTAJxYByKtiSBviN4LGcQja+Ne50 z5TaT5Mm/YYCA/KgxeftDpoHUI9wUnQ8hiVgGmWy5zAElIn8BF+iCbVooFVbEdQXspG1 VsmwqHFarkOp7Qa8OXgLWXaW1OyquSM9V6Vc9Y7Vn5+IXuwhW+QWZDn0/fofwUBH34XT JRNK63Zz6OUiqgd3JFE3DSMb8vhnbOynOiEimkyN0R44S551vWrlgNkLHdpoM6lmy0Ld euJw== X-Gm-Message-State: AOAM5313YevrXRWDvZngzrUvuxGGf5DySMZ/Q5DyTSzTkV2d2HuHqNW1 +PvNAxjLGXQCZoLw/NuEv9B1QXT2zSw= X-Google-Smtp-Source: ABdhPJzKDkHVW1R2MC+Nhg/V/wFyysks9SmrrOZPKWBr9DJqaBdQnJOCmh0zLDSQV1Z/jaqGVIPM47cp9DI= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90b:2384:b0:1cb:5223:9dc4 with SMTP id mr4-20020a17090b238400b001cb52239dc4mr276794pjb.1.1650351433778; Mon, 18 Apr 2022 23:57:13 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:11 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-6-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 05/38] KVM: arm64: Prohibit modifying values of ID regs for 32bit EL1 guests From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235715_452739_9DC277B0 X-CRM114-Status: GOOD ( 12.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Prohibit userspace from modifying values of ID registers. (Don't support configurable ID registers for 32bit EL1 guests) NOTE: The following patches will enable trapping disabled features only based on values of AArch64 ID registers for the guest expecting userspace to make AArch32 ID registers consistent with the AArch64 ones (Otherwise, it will be a userspace bug). Supporting 32bit EL1 guests will require that KVM will not enable trapping based on values of AArch64 ID registers (and should enable trapping based on the AArch32 ID registers when possible). Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b19e14a1206a..bc06570523f4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1537,6 +1537,10 @@ static int __set_id_reg(struct kvm_vcpu *vcpu, if (raz) return -EINVAL; + /* Don't allow to modify the register's value for the 32bit EL1 guest */ + if (test_bit(KVM_ARCH_FLAG_EL1_32BIT, &vcpu->kvm->arch.flags)) + return -EPERM; + /* * Don't allow to modify the register's value if the register doesn't * have the id_reg_desc. From patchwork Tue Apr 19 06:55:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817496 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3AD8C433F5 for ; Tue, 19 Apr 2022 07:00:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=MbtSCbZ0wiKfyT/dQE4jCPJjRzPrGl45ewoG9o+aVJA=; b=wyL+LagdupfJ64eGNB+H2VxNBm styif62/02Hq3CpZmZqDI9b1SEzrkLlf0Ucdr3zwOBXLfeAmw77q4/ayJLGVqoMtE1uQhPblmDk+0 2nEPEiMABikuRTLavgfM4yvxns2NgI9m0lDZGJxayBXSAVokEghKdQPTiTg+R1G4VbUaNs9HzEQ6p /PbuqajJJNJt8L7g3l1L+mVWLhmLJ0N42VdoryhulT5cBbDqXJpZVBDodaePIRPixD6+020bO/XJQ 1vFgZgq28orJMdSXUn055VPmbrYPw9B55QI/BPquhCyV7EZ/TLHkLZ2zrY1TVnd7rH85mwZlzJxYJ AvOwDZ5A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghpD-001oF5-IC; Tue, 19 Apr 2022 06:59:00 +0000 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnZ-001nO9-Mn for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:19 +0000 Received: by mail-pl1-x64a.google.com with SMTP id q6-20020a170902eb8600b001588e49dcaaso9253129plg.9 for ; Mon, 18 Apr 2022 23:57:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=+1i7m94WPnvGucFL2GeFJ3E0bHVaMwecFNukYu6XUWY=; b=gqE5oIxvxoF3RF9Eb6xFb5KdNCFf4iQFf6ZwJ0NHsC/BK9y9cftZ1I7H3bJRyE0iUe 7rl3PcWJ+l1OsF3xvVj5Q3nQ2BFbm3jfjKxAsvB/tYqEfWrKWqC69qFI0e17rUiz+qg5 Yvn6hD5FKR5q3abn1VKgfq++0UGjNqDDN2/vZFCd0Vd6o0eiv5Kt95s/M3CvZ0mwwjx2 27Xg6NFBfwKtDGvz3u9dQyEOH3R2a/I8ES3bN69msrxYETM8MKX2DZhIuH9quJJTobsn mO1sn69F42iUXCHuhRdeGjPk+O9d5b6xGcMcdfTijJYsPjM4TsCO5g9+wSyVqRuAAWPt MIXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=+1i7m94WPnvGucFL2GeFJ3E0bHVaMwecFNukYu6XUWY=; b=md9Xb8CLUmJEHyYr1oh03vY4jhY/SVBzafk8bP1xd81gUqyfhFw9oeH5326XySAIIP sAvBEQ8y+t0I/g9VbHGE8hIlXbNbycbsXyICojNZm8YQ9ytg1xYiTjIV3Rfv6y63IttI dphY65wlpCTAY8ecBx77lA/lQaI7Rj9vsh+XmGae7u1brL7t38vyApXy/uzZ6dkyfpW8 qQ+MpNBeAlwzL6byn3jkhIGY7kt6g0eCRRR4mtZaWFj4tBBzXrl1LMcndLvR5uR+/FS3 R3Qsu4toqKHgy82azoXBpyMvGQDnf9/9HtfWE4qH+wqHjNHPVlmm5mVjVfg/hvXIvLYd rIYQ== X-Gm-Message-State: AOAM533NWPXr01URiBma6Rj156/5e+dW2wccxwQMPWRXfwmfZurjj+20 LgPGCdTwEB6DLRmCIW+hP+VmjG51Law= X-Google-Smtp-Source: ABdhPJw+LFmFhghAXPsnU+QIeZuTJu6vCbhMzC4h4qzizPpPRBlzrz++jClVsuPutXAbnTGljcQXTfwBSdc= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:1505:b0:50a:8a96:2994 with SMTP id q5-20020a056a00150500b0050a8a962994mr5157138pfu.2.1650351435732; Mon, 18 Apr 2022 23:57:15 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:12 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-7-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 06/38] KVM: arm64: Make ID_AA64PFR0_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235717_794681_2F323F2D X-CRM114-Status: GOOD ( 26.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64PFR0_EL1 to make it writable by userspace. Return an error if userspace tries to set SVE/GIC field of the register to a value that conflicts with SVE/GIC configuration for the guest. SIMD/FP/SVE fields of the requested value are validated according to Arm ARM. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/sys_regs.c | 172 +++++++++++++++++++++----------- arch/arm64/kvm/vgic/vgic-init.c | 9 ++ 3 files changed, 123 insertions(+), 59 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 3d860108661b..3adb402fab86 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -834,6 +834,7 @@ #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 #define ID_AA64PFR0_ELx_64BIT_ONLY 0x1 #define ID_AA64PFR0_ELx_32BIT_64BIT 0x2 +#define ID_AA64PFR0_GIC3 0x1 /* id_aa64pfr1 */ #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index bc06570523f4..67a0604fe6f1 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -271,6 +271,19 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, return read_zero(vcpu, p); } +#define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ + .sign = ftr_sign, \ + .type = ftr_type, \ + .shift = bit_pos, \ + .width = ARM64_FEATURE_FIELD_BITS, \ + .safe_val = safe, \ +} + +#define S_FTR_BITS(ftr_type, bit_pos, safe_val) \ + __FTR_BITS(FTR_SIGNED, ftr_type, bit_pos, safe_val) +#define U_FTR_BITS(ftr_type, bit_pos, safe_val) \ + __FTR_BITS(FTR_UNSIGNED, ftr_type, bit_pos, safe_val) + /* * Number of entries in id_reg_desc's ftr_bits[] (Number of 4 bits fields * in 64 bit register + 1 entry for a terminator entry). @@ -354,6 +367,86 @@ static void id_reg_desc_init(struct id_reg_desc *id_reg) id_reg->vcpu_limit_val, val)); } +static int validate_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + int fp, simd; + unsigned int gic; + bool vcpu_has_sve = vcpu_has_sve(vcpu); + bool pfr0_has_sve = id_aa64pfr0_sve(val); + + simd = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_ASIMD_SHIFT); + fp = cpuid_feature_extract_signed_field(val, ID_AA64PFR0_FP_SHIFT); + /* AdvSIMD field must have the same value as FP field */ + if (simd != fp) + return -EINVAL; + + /* fp must be supported when sve is supported */ + if (pfr0_has_sve && (fp < 0)) + return -EINVAL; + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ + if (vcpu_has_sve ^ pfr0_has_sve) + return -EPERM; + + if ((irqchip_in_kernel(vcpu->kvm) && + vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) { + gic = cpuid_feature_extract_unsigned_field(val, + ID_AA64PFR0_GIC_SHIFT); + if (gic == 0) + return -EPERM; + + if (gic > ID_AA64PFR0_GIC3) + return -E2BIG; + } else { + u64 mask = ARM64_FEATURE_MASK(ID_AA64PFR0_GIC); + int r = arm64_check_features(id_reg->ftr_bits, val & mask, + id_reg->vcpu_limit_val & mask); + + if (r) + return r; + } + + return 0; +} + +static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) +{ + u64 limit = id_reg->vcpu_limit_val; + unsigned int gic; + + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU); + if (!system_supports_sve()) + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); + + /* + * The default is to expose CSV2 == 1 and CSV3 == 1 if the HW + * isn't affected. Userspace can override this as long as it + * doesn't promise the impossible. + */ + limit &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2) | + ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3)); + + if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), 1); + if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), 1); + + gic = cpuid_feature_extract_unsigned_field(limit, ID_AA64PFR0_GIC_SHIFT); + if (gic > 1) { + /* Limit to GICv3.0/4.0 */ + limit &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC); + limit |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), ID_AA64PFR0_GIC3); + } + id_reg->vcpu_limit_val = limit; +} + +static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *idr) +{ + return vcpu_has_sve(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); +} + static int validate_id_reg(struct kvm_vcpu *vcpu, const struct id_reg_desc *id_reg, u64 val) { @@ -1330,20 +1423,6 @@ static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) val = read_kvm_id_reg(vcpu->kvm, id); switch (id) { - case SYS_ID_AA64PFR0_EL1: - if (!vcpu_has_sve(vcpu)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2); - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3); - if (irqchip_in_kernel(vcpu->kvm) && - vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1); - } - break; case SYS_ID_AA64PFR1_EL1: if (!kvm_has_mte(vcpu->kvm)) val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); @@ -1443,48 +1522,6 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, return REG_HIDDEN; } -static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, - const struct sys_reg_desc *rd, - const struct kvm_one_reg *reg, void __user *uaddr) -{ - const u64 id = sys_reg_to_index(rd); - u8 csv2, csv3; - int err; - u64 val; - - err = reg_from_user(&val, uaddr, id); - if (err) - return err; - - /* - * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as - * it doesn't promise more than what is actually provided (the - * guest could otherwise be covered in ectoplasmic residue). - */ - csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT); - if (csv2 > 1 || - (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED)) - return -EINVAL; - - /* Same thing for CSV3 */ - csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT); - if (csv3 > 1 || - (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED)) - return -EINVAL; - - /* We can only differ with CSV[23], and anything else is an error */ - val ^= read_id_reg(vcpu, rd, false); - val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) | - (0xFUL << ID_AA64PFR0_CSV3_SHIFT)); - if (val) - return -EINVAL; - - vcpu->kvm->arch.pfr0_csv2 = csv2; - vcpu->kvm->arch.pfr0_csv3 = csv3 ; - - return 0; -} - /* cpufeature ID register user accessors */ static int __get_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, void __user *uaddr, @@ -1809,8 +1846,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* AArch64 ID registers */ /* CRm=4 */ - { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, - .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, }, + ID_SANITISED(ID_AA64PFR0_EL1), ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), @@ -3175,8 +3211,26 @@ int kvm_set_id_reg_feature(struct kvm *kvm, u32 id, u8 field_shift, u8 fval) return __modify_kvm_id_reg(kvm, id, val, preserve_mask); } +static struct id_reg_desc id_aa64pfr0_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64PFR0_EL1), + .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), + .init = init_id_aa64pfr0_el1_desc, + .validate = validate_id_aa64pfr0_el1, + .vcpu_mask = vcpu_mask_id_aa64pfr0_el1, + .ftr_bits = { + S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, ID_AA64PFR0_FP_NI), + S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, ID_AA64PFR0_ASIMD_NI), + } +}; + +#define ID_DESC(id_reg_name, id_reg_desc) \ + [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) + /* A table for ID registers's information. */ -static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = {}; +static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { + /* CRm=4 */ + ID_DESC(ID_AA64PFR0_EL1, &id_aa64pfr0_el1_desc), +}; static inline struct id_reg_desc *get_id_reg_desc(u32 id) { diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index fc00304fe7d8..f0632b46fbf9 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -117,6 +117,15 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) else INIT_LIST_HEAD(&kvm->arch.vgic.rd_regions); + if (type == KVM_DEV_TYPE_ARM_VGIC_V3) + /* + * Set ID_AA64PFR0_EL1.GIC to 1. This shouldn't fail unless + * any vCPU in the guest have started. + */ + WARN_ON_ONCE(kvm_set_id_reg_feature(kvm, SYS_ID_AA64PFR0_EL1, + ID_AA64PFR0_GIC3, + ID_AA64PFR0_GIC_SHIFT)); + out_unlock: unlock_all_vcpus(kvm); return ret; From patchwork Tue Apr 19 06:55:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10661C433F5 for ; Tue, 19 Apr 2022 07:00:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=6C/fojK5teE1cwlVtJqIw4laPyU+pSP6TGHLjdRfDbA=; b=PT1yxzzm+jDCDeBZw9BftI76Es 4ldZyaER6QBlp3ravPK4kSKL2WaWW5LFLaoFavnBPmdDfe7DGBrVtG8ZGcineMrqbhXrFMpmjw3Iu v1qLFqWIL6qqflF0QDXkqIJkmw231YnBtevAh+RYREPQST61nRt3uPQMwyO8bvXzi4lPpPKIONXSu jqiCb4VBymKwMZ+mEe9w8pScitGvb4dB6/TsQ0VW1qKMTlduvphMEDfI4wwaQJ1AB2x8+RMk6hnNM mP68aStaatbiNMq0cZ7c6g1gUOwHz/J9PqOd3CXsuwoH7r5R8/qvzZAuvZWvHFF6q11181KAv+uz/ N+8tdUew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghpd-001oQV-Bs; Tue, 19 Apr 2022 06:59:26 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghna-001nOw-Ry for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:21 +0000 Received: by mail-pj1-x1049.google.com with SMTP id e12-20020a17090a7c4c00b001cb1b3274c9so1041420pjl.4 for ; Mon, 18 Apr 2022 23:57:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=a16GM35sjxxlQKcTXUheYgNf0O4Bz0BcVFGp05uoS+A=; b=hmBUOWaE1NnSP7Cp16j43pFlkvvZ9H4KmuU1Ra0gR7gHPnKNVuuN/naQee0HGOq3wQ fhToaMAKA8werNfqWNDm4scTHg+CXLxsNd0bPmtIZ98ylO0egYYaGed8n9RV3b6YVnU8 TA1nq43ZdqjtTkTT14ylfDZnTljfxNpKCsQr0Jyp5JLqiRNk7vu05YSVXfl8heWvEEcD kyG8xu2676waxirA3V03XO3j1Y8yrruZKhgqfd9LDVUI0Jg2Py76OhPlrZymt9GC87n0 0yLCnkD4UUjAaRUW2fH/FO9u9C3Qozv9NXoUc/5gwc8WpGf//tZLbjmUWuDttbWDIge0 75/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=a16GM35sjxxlQKcTXUheYgNf0O4Bz0BcVFGp05uoS+A=; b=pjyaGXsYo/OjU0xW/E15yzOSuBGGBLewcyzQF8z8oeI9xYQqjogaQXq0IkXakFQ/ZE muTp7tmTGaDouGnkigYeVmHDBEklNat+mIMh6mkMalDSKP/IBJve18whzBIQv/aJ+FpX wugZjoJLhY8aH6RcrCk40N4WZds0u2AgryoSlRT0+ncPQ9MhdSY7r/1EFjCMj7A2cwVf ltfNsFL+CmvUsDoX6sVsNglK/TuDUE/a2DXN7mYl5p66MgGaNEvGodOe8uRCaRFUEpDq 4uZzp2zbbPlLbB7hkOKNbdlGByGy40491ZVsfiDbcKT4Z3rNgjFnJPbH4dP8yUKDowKA ACFA== X-Gm-Message-State: AOAM5330VUqCQyHFO5YUSM3qIjq9hpxme9MzF+KB7QjIW3SSxpTZEsur 3VF5wkZtw/RtCxZJfjH9hCXbUSZCXPU= X-Google-Smtp-Source: ABdhPJwSDKGRLdk5m+uU0CnsYnVPDSIqAFVbJcSmiEhdttrrb/Xm7zdvkXFnaC/AVP85cyC6XCAbFW3dIa0= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:808:b0:50a:870d:6c8c with SMTP id m8-20020a056a00080800b0050a870d6c8cmr5634521pfk.76.1650351437207; Mon, 18 Apr 2022 23:57:17 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:13 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-8-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 07/38] KVM: arm64: Make ID_AA64PFR1_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235718_974370_4BC5726D X-CRM114-Status: GOOD ( 18.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64PFR1_EL1 to make it writable by userspace. Return an error if userspace tries to set MTE field of the register to a value that conflicts with KVM_CAP_ARM_MTE configuration for the guest. Skip fractional feature fields validation at present and they will be handled by the following patches. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/sysreg.h | 1 + arch/arm64/kvm/sys_regs.c | 42 +++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 3adb402fab86..b33b7ce87fb2 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -837,6 +837,7 @@ #define ID_AA64PFR0_GIC3 0x1 /* id_aa64pfr1 */ +#define ID_AA64PFR1_CSV2FRAC_SHIFT 32 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 #define ID_AA64PFR1_RASFRAC_SHIFT 12 #define ID_AA64PFR1_MTE_SHIFT 8 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 67a0604fe6f1..c3537cd4fe58 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -410,6 +410,21 @@ static int validate_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + bool kvm_mte = kvm_has_mte(vcpu->kvm); + unsigned int mte; + + mte = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR1_MTE_SHIFT); + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT. */ + if (kvm_mte ^ (mte > 0)) + return -EPERM; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -441,12 +456,24 @@ static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) id_reg->vcpu_limit_val = limit; } +static void init_id_aa64pfr1_el1_desc(struct id_reg_desc *id_reg) +{ + if (!system_supports_mte()) + id_reg->vcpu_limit_val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); +} + static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, const struct id_reg_desc *idr) { return vcpu_has_sve(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64PFR0_SVE); } +static u64 vcpu_mask_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *idr) +{ + return kvm_has_mte(vcpu->kvm) ? 0 : (ARM64_FEATURE_MASK(ID_AA64PFR1_MTE)); +} + static int validate_id_reg(struct kvm_vcpu *vcpu, const struct id_reg_desc *id_reg, u64 val) { @@ -1423,10 +1450,6 @@ static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) val = read_kvm_id_reg(vcpu->kvm, id); switch (id) { - case SYS_ID_AA64PFR1_EL1: - if (!kvm_has_mte(vcpu->kvm)) - val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); - break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | @@ -3223,6 +3246,16 @@ static struct id_reg_desc id_aa64pfr0_el1_desc = { } }; +static struct id_reg_desc id_aa64pfr1_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64PFR1_EL1), + .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_RASFRAC) | + ARM64_FEATURE_MASK(ID_AA64PFR1_MPAMFRAC) | + ARM64_FEATURE_MASK(ID_AA64PFR1_CSV2FRAC), + .init = init_id_aa64pfr1_el1_desc, + .validate = validate_id_aa64pfr1_el1, + .vcpu_mask = vcpu_mask_id_aa64pfr1_el1, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -3230,6 +3263,7 @@ static struct id_reg_desc id_aa64pfr0_el1_desc = { static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=4 */ ID_DESC(ID_AA64PFR0_EL1, &id_aa64pfr0_el1_desc), + ID_DESC(ID_AA64PFR1_EL1, &id_aa64pfr1_el1_desc), }; static inline struct id_reg_desc *get_id_reg_desc(u32 id) From patchwork Tue Apr 19 06:55:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7582FC433F5 for ; Tue, 19 Apr 2022 07:01:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Cc7CHt33Is8VDCjOcuysuZ1nwNs6chMBWsMjYZqJiqg=; b=fb1h/YbQHtXGwYobvGhwSGkMD3 Nc2Y5nWue7JgZsX0OcgCXS++d/Mffzu2erYVxvEXJ0KSgQT4grku4MxoFDTdD/1Qf03z+jT43o0VC VoHPz+611Y4nM+FsbTjw4o0CB17xxgPRXpzbwUy2CWPd7RN60iQlIBi41kL3WspC0Y7Er31smLebj 1CqrgnXk19DUmk1asSCjOfOaCN+wCq0CsPbwnygfuCDBBddMp0jGDSwtXPY/fK7rI38vyPFO6YqPv gUU5g28z3n75fJVKM3XwW4LVAhayIM8F0LhemTKV80f1yYGFydteYhvys4DBp8NSydsSCOrlRUznH KIJO4n1w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghqA-001odd-RD; Tue, 19 Apr 2022 06:59:59 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnc-001nPq-31 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:21 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id q142-20020a25d994000000b00641d23dbeb9so13778109ybg.9 for ; Mon, 18 Apr 2022 23:57:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=F9GVjgg0f4Eemfa1MtjY71p4mXhfcLBZ4BAQg8wg5XY=; b=X+pobMbVaGwgu5LTnSwRAhxIsSPT3tTWzl4eEAhJdrVtMOSpFKA4Ke42asU/3dvssI 381enhjh7yPijf8pAlX+aqtsdIj0duWitAwAoy42KcoMXeMZTmkNw4w9t3jtqUELlT7n vtJIM8CFxZuqkSv+/d7hpVxYopPx34tb94wNS19mvpV0aVTYCUiO3Ji7bfQgxyj1Zq+M Xxzajz4UsXketmCrnsvZkfgkOdXdgsp1xQ5NNW2ko6f9U22L3NeQx7cwF22PipUE8l1u bR7YuhvhEH5FAdYOx3Z4CTFCXbfRgfY96WHeJlj5IHlUeGIzTLqXst1wNQH5GsLfwIQL exfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=F9GVjgg0f4Eemfa1MtjY71p4mXhfcLBZ4BAQg8wg5XY=; b=1ZOyUbWfilh0g9Yefwk12mX9LfW0SxvwZPBU42a7Jjn5Fr+j0uE4nKd7gs50EUWmDD g8Ncx5ndKv0VbjiVAyJd8MYIBWrWOBJtH9B68YGOZ7azzib8e3vtqoWsePXXsmuc8Jok GRlF0tkUcrF401n/V77gVdQpHhnW3HNQBZcFVY+M6Wjo4nCUja6ZMiGhYsg1mj257uzr 2X0GLHdB/vpkY/8zUeJaAmLKYc+Sg6vfbPx3tcvyCAe/okTgTRKHA0FYy3L6Z/SXu1q+ Y7wTtJMOAClpOYPfNtez0xJn0M0073IZyrKwzGhzllurrBXDCx6pQVIsTfh4Eycm96aD AeVw== X-Gm-Message-State: AOAM533/NwMgiJ6yzy3pxUK/LGQ3VQfoMp0Z+PYDU+wWfU8fO100azEC 89i4lOpy2SxtTwMUkisWycPIuyoC8Zk= X-Google-Smtp-Source: ABdhPJyKCFDKA+Kv2LJacZJZ+S367HCU69wGD+6+X9uBwvbwrCQWpjBQK8XUhugss+g+U3Xwz9Iz0thLwQE= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a25:e050:0:b0:645:3723:f52d with SMTP id x77-20020a25e050000000b006453723f52dmr2116304ybg.144.1650351438821; Mon, 18 Apr 2022 23:57:18 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:14 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-9-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 08/38] KVM: arm64: Make ID_AA64ISAR0_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235720_201673_FC566BB3 X-CRM114-Status: GOOD ( 12.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64ISAR0_EL1 to make it writable by userspace. Updating sm3, sm4, sha1, sha2 and sha3 fields are allowed only if values of those fields follow Arm ARM. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c3537cd4fe58..c01038cbdb31 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -425,6 +425,29 @@ static int validate_id_aa64pfr1_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_id_aa64isar0_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + unsigned int sm3, sm4, sha1, sha2, sha3; + + /* Run consistency checkings according to Arm ARM */ + sm3 = cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR0_SM3_SHIFT); + sm4 = cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR0_SM4_SHIFT); + if (sm3 != sm4) + return -EINVAL; + + sha1 = cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR0_SHA1_SHIFT); + sha2 = cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR0_SHA2_SHIFT); + if ((sha1 == 0) ^ (sha2 == 0)) + return -EINVAL; + + sha3 = cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR0_SHA3_SHIFT); + if (((sha2 == 2) ^ (sha3 == 1)) || (!sha1 && sha3)) + return -EINVAL; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -3256,6 +3279,11 @@ static struct id_reg_desc id_aa64pfr1_el1_desc = { .vcpu_mask = vcpu_mask_id_aa64pfr1_el1, }; +static struct id_reg_desc id_aa64isar0_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64ISAR0_EL1), + .validate = validate_id_aa64isar0_el1, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -3264,6 +3292,9 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=4 */ ID_DESC(ID_AA64PFR0_EL1, &id_aa64pfr0_el1_desc), ID_DESC(ID_AA64PFR1_EL1, &id_aa64pfr1_el1_desc), + + /* CRm=6 */ + ID_DESC(ID_AA64ISAR0_EL1, &id_aa64isar0_el1_desc), }; static inline struct id_reg_desc *get_id_reg_desc(u32 id) From patchwork Tue Apr 19 06:55:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D243FC433F5 for ; Tue, 19 Apr 2022 07:02:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=YJBs6KCCpAaIruVZXqt8r/L1XfyJqYTtoVKe2Hpq9Ns=; b=s82LRvEmCH4a1dndzxsmcjeR8d GWUSpL6puKdzARkT2A2blNjRY87Am3BE6PypspuohXisWbdeTrwsyTabIa/WMrstLWV2WjJD4O2wB 02TO9t1zTCQgSf9kkdITgzO6ZvE9MMW2Jae2SIfeAnlzdRTlBRUxffBGnsmhrJTWm3YzHEnnZWRP5 IiNO5N+b2jC0f9QVqd5ris9cz7ZgCCawwjFc3C2BToXttDN6zQRGlr87a7lzL+FvTohWSCnWFGI+S dot4W9OGxv+EIaA3eIKfiFQkByY40GlZhq3eZuIocmxljkQXmQKymwhC19gS6mrPxqAgNOAW61kXa AWPOedsw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghqj-001opr-Fg; Tue, 19 Apr 2022 07:00:34 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnd-001nQo-Kh for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:23 +0000 Received: by mail-pj1-x104a.google.com with SMTP id r15-20020a17090a4dcf00b001cb7ea0b0bdso1045754pjl.1 for ; Mon, 18 Apr 2022 23:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=T9Xy6Y7bYT/jvhM2kTPbgpDtWYIyMfhZbMRA2+tL7yI=; b=B7PAcAM4HsOqHFYrrY4pedJvy7X9vroe5Q8S1fAV7WVj5N09swKpjJJfF3gnP8/reJ fVsrxBdLBTz0krOUET53ChIdF5mbVTIFS7fAYzQVuE0G4zVoiCbUp6oDmfC6NacuHOvL 5azkE3plJDxC9w7+IUCUwSoBwx+3QnNoA+bcS5LihZhXcM3eaBwKsMHJssp9n5HfwHKT XxU+kZjw65krvFcJcyKGb/f6wFqEB1IZXDd41Bmlf8BLgtY992wK0z7zt0MpLIFxo+9v elPgQc0sBjjCf7YaCd1UsULtfi7TcpBe2ozt6vbyfcigvyUMOupYh5fjS1PWyMiE6JfL KYDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=T9Xy6Y7bYT/jvhM2kTPbgpDtWYIyMfhZbMRA2+tL7yI=; b=jFHqAwHYcEsSA92qXt98bErFY5jG5o5FHXIWLD3q7FEE4u6zN0hPfopxjynys/cxjk GqUPq/3szgC+3dTQUIgVR3fln7WpCbB+ufLk33IxmZPs142QDlX04AZuSZ78ADLa3qAE 2IZc5WGZ3aDgkO7djcYEv2h1h2AIFx8p1H5VXlNOr5cuH92F3150+/72ClEWeCFu9LQE u6aWU0D3Q7Y/8WZk2zNSy5fPpcxTADDwrLDwKmGP6oGEZBwdVElKesZ+TXxfTAGLpoX0 zTJNrM0EXjecYCTUks7IjBwtyGshFXNdFFTr6cL059oBL+X3/70iEEzua/a2ONoHC38P Yb2w== X-Gm-Message-State: AOAM531qWiMinduSJ2Zjjwzd5oJ/s6m8a1+m0PLHVSNZAnL6wS/KkD6t 8YOPsYsY9uV4B8akU/3LfRnr5k9EDrE= X-Google-Smtp-Source: ABdhPJx6kmdRm2h0buoVV6HUHf1SRqgqhPTpvh0hIVJbrpV8QWVshsgJq6Q+Nc4d3tpnnfmRdI/PituH1Jk= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:902:aa8e:b0:158:e948:27 with SMTP id d14-20020a170902aa8e00b00158e9480027mr13672768plr.69.1650351440204; Mon, 18 Apr 2022 23:57:20 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:15 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-10-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 09/38] KVM: arm64: Make ID_AA64ISAR1_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235721_795758_B95F54FB X-CRM114-Status: GOOD ( 17.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64ISAR1_EL1 to make it writable by userspace. Return an error if userspace tries to set PTRAUTH related fields of the register to values that conflict with PTRAUTH configuration, which was configured by KVM_ARM_VCPU_INIT, for the guest. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 90 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c01038cbdb31..dd4dcc1e4982 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -271,6 +271,24 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, return read_zero(vcpu, p); } +#define ISAR1_TRAUTH_MASK (ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)) + +#define aa64isar1_has_apa(val) \ + (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR1_APA_SHIFT) >= \ + ID_AA64ISAR1_APA_ARCHITECTED) +#define aa64isar1_has_api(val) \ + (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR1_API_SHIFT) >= \ + ID_AA64ISAR1_API_IMP_DEF) +#define aa64isar1_has_gpa(val) \ + (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR1_GPA_SHIFT) >= \ + ID_AA64ISAR1_GPA_ARCHITECTED) +#define aa64isar1_has_gpi(val) \ + (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR1_GPI_SHIFT) >= \ + ID_AA64ISAR1_GPI_IMP_DEF) + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -448,6 +466,47 @@ static int validate_id_aa64isar0_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_id_aa64isar1_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + bool has_gpi, has_gpa, has_api, has_apa; + bool generic, address, lim_generic, lim_address; + u64 lim = id_reg->vcpu_limit_val; + + has_gpi = aa64isar1_has_gpi(val); + has_gpa = aa64isar1_has_gpa(val); + has_api = aa64isar1_has_api(val); + has_apa = aa64isar1_has_apa(val); + if ((has_gpi && has_gpa) || (has_api && has_apa)) + return -EINVAL; + + generic = has_gpi || has_gpa; + address = has_api || has_apa; + lim_generic = aa64isar1_has_gpi(lim) || aa64isar1_has_gpa(lim); + lim_address = aa64isar1_has_api(lim) || aa64isar1_has_apa(lim); + + /* + * When PTRAUTH is configured for the vCPU via KVM_ARM_VCPU_INIT, + * it should mean that userspace wants to expose + * one of ID_AA64ISAR1_EL1.GPI, GPA or ID_AA64ISAR2_EL1.GPA3 and + * one of ID_AA64ISAR1_EL1.API, APA or ID_AA64ISAR2_EL1.APA3 to + * the guest (As per Arm ARM, for generic code authentication + * and address authentication, only one of those field can be + * non-zero). + * Check if there is a conflict in the requested value for + * ID_AA64ISAR1_EL1 with PTRAUTH configuration. + * (When lim_generic/lim_address is 0, generic/address must be + * also 0, which is checked by arm64_check_features()) + */ + if (lim_generic && (vcpu_has_ptrauth(vcpu) ^ generic)) + return -EPERM; + + if (lim_address && (vcpu_has_ptrauth(vcpu) ^ address)) + return -EPERM; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -485,6 +544,12 @@ static void init_id_aa64pfr1_el1_desc(struct id_reg_desc *id_reg) id_reg->vcpu_limit_val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); } +static void init_id_aa64isar1_el1_desc(struct id_reg_desc *id_reg) +{ + if (!system_has_full_ptr_auth()) + id_reg->vcpu_limit_val &= ~ISAR1_TRAUTH_MASK; +} + static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, const struct id_reg_desc *idr) { @@ -497,6 +562,12 @@ static u64 vcpu_mask_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, return kvm_has_mte(vcpu->kvm) ? 0 : (ARM64_FEATURE_MASK(ID_AA64PFR1_MTE)); } +static u64 vcpu_mask_id_aa64isar1_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *idr) +{ + return vcpu_has_ptrauth(vcpu) ? 0 : ISAR1_TRAUTH_MASK; +} + static int validate_id_reg(struct kvm_vcpu *vcpu, const struct id_reg_desc *id_reg, u64 val) { @@ -1473,13 +1544,6 @@ static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) val = read_kvm_id_reg(vcpu->kvm, id); switch (id) { - case SYS_ID_AA64ISAR1_EL1: - if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_API) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) | - ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI)); - break; case SYS_ID_AA64ISAR2_EL1: if (!vcpu_has_ptrauth(vcpu)) val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | @@ -3284,6 +3348,17 @@ static struct id_reg_desc id_aa64isar0_el1_desc = { .validate = validate_id_aa64isar0_el1, }; +static struct id_reg_desc id_aa64isar1_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64ISAR1_EL1), + .init = init_id_aa64isar1_el1_desc, + .validate = validate_id_aa64isar1_el1, + .vcpu_mask = vcpu_mask_id_aa64isar1_el1, + .ftr_bits = { + U_FTR_BITS(FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 0), + U_FTR_BITS(FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 0), + }, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -3295,6 +3370,7 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=6 */ ID_DESC(ID_AA64ISAR0_EL1, &id_aa64isar0_el1_desc), + ID_DESC(ID_AA64ISAR1_EL1, &id_aa64isar1_el1_desc), }; static inline struct id_reg_desc *get_id_reg_desc(u32 id) From patchwork Tue Apr 19 06:55:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA14EC433EF for ; Tue, 19 Apr 2022 07:02:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Jf3/5SJbzgUNVL3/F24DFMBR89Q1JspDe0B4Sxkgu8E=; b=PNdVji5QPOFGWV+U3w1G+SnkLW TDCDfEJ/SS/OVWrxsR0gNO8SPzCxMErA1PgaEefVTsgFz6MBg56Zl8mVdfoztnsXtE5H4kF0YXVQ9 Udxf9ASZopuPW2BaiDTJneMJCzFafBCuxe+K4OmT3WdRbSca4UF0PZ9eKQ2nFemCgG83o8685172w lPT/hwquKkWj3gUhCRBxMnB727yS+lu0OTU5a9VtohA0KTpDdwLVGXze4qnNadIaC9EqcRuNi7COx jeCWKaYe1/CDftkDBGEZV1M+dzLIuzN3bUa4taX1y8gKGHxc71HqM+XJHbOQjzeRbgy0f7gQcNE62 18PROBeg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghrK-001p3O-Qn; Tue, 19 Apr 2022 07:01:11 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnf-001nRn-Dz for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:25 +0000 Received: by mail-pl1-x649.google.com with SMTP id f11-20020a170902684b00b00158c67ef30cso6679257pln.7 for ; Mon, 18 Apr 2022 23:57:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=4TCi+sJLW2uaem/+k27V6Nf+rQ0PhWYVioo5Q6rkdZk=; b=Hp9HgO/5PopUEK+kzy6sJa4PypL+kqEMbC0oXyjEuGS+tzp+ZuEBJ5KSrhSO+ILmk6 y3AOpc1wZCpj2wIc6+I+hBwQ3UH842aJJThkW8WOBRZKQFE/jmRiW7GBjnOgjPi0I/Ja AlRFrV3q/j3YxsH9BMEAwDaIr+amb8gc2m4D1tyjC5WJMoZXm451ThezOj25kGVusGj8 Ae2esA2cfwtvUAbyGmHBoQZ+mflUw46F4D9BrYFkYw9TPctz5VQJDQXghVxFQhXKEmcT vYiIHlopdqiMQCAx/nKa/mhAkBI+zDzW7XuUWrAOvDuoE3jerlVF3x+P9zxP8OTvDRxi cLIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=4TCi+sJLW2uaem/+k27V6Nf+rQ0PhWYVioo5Q6rkdZk=; b=pS7R1ZTP+4QhBYCF4q9NuXVsOJy1ouM0xpX6C/3Eaq9XIYD4RlvxIs7rHBQJJs3Byn Kaxq18s1inu2R6Njh7f5tRwhrHl/kFI7ZmicJMk0+nbFXDQDtWD9znD00Wr4kGdJE39b Q9TBXDuJCtu1W4krmKSMMW3noh1j5hBHi1mAMuei56Gq9w1Wkv+R29LpMvuYZBvCTn4+ nwvxJ8PX4AtIFhi6NJFth+F+3gryaeUD0OudDt05iOmgAe38FbPCFURp78kMbjN9tx73 stwLqk4mkmbzeP/Mzq6cJkLqcZOXsT7DLuCxoEKpCLL/2V6o7UYK/MuBoGZWI6etdzko bNcw== X-Gm-Message-State: AOAM531zQHkA6l636/Zy6Bn2XK2GA9JttH2IDeJ8bE2qo6yrrZag4V55 A4npDUdxK9iegeAlZ9zpN6T9e2BDqnk= X-Google-Smtp-Source: ABdhPJzSEZPodaqcIqvMD82N8W0cud+ZqgBHTt/0eiSMy13p/um5GCarQPZcMAPbrjM8K4rm6xCKlIue0Vo= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:903:2283:b0:158:e7f4:7056 with SMTP id b3-20020a170903228300b00158e7f47056mr14258890plh.24.1650351441718; Mon, 18 Apr 2022 23:57:21 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:16 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-11-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 10/38] KVM: arm64: Make ID_AA64ISAR2_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235723_559265_96A3734E X-CRM114-Status: GOOD ( 17.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64ISAR2_EL1 to make it writable by userspace. Return an error if userspace tries to set PTRAUTH related fields of the register to values that conflict with PTRAUTH configuration, which was configured by KVM_ARM_VCPU_INIT, for the guest. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 65 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 60 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dd4dcc1e4982..ba2e6dac7774 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -289,6 +289,16 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR1_GPI_SHIFT) >= \ ID_AA64ISAR1_GPI_IMP_DEF) +#define ISAR2_PTRAUTH_MASK (ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | \ + ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)) + +#define aa64isar2_has_apa3(val) \ + (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR2_APA3_SHIFT) >= \ + ID_AA64ISAR2_APA3_ARCHITECTED) +#define aa64isar2_has_gpa3(val) \ + (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR2_GPA3_SHIFT) >= \ + ID_AA64ISAR2_GPA3_ARCHITECTED) + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -507,6 +517,31 @@ static int validate_id_aa64isar1_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_id_aa64isar2_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + bool has_gpa3, has_apa3, lim_has_gpa3, lim_has_apa3; + u64 lim = id_reg->vcpu_limit_val; + + has_gpa3 = aa64isar2_has_gpa3(val); + has_apa3 = aa64isar2_has_apa3(val); + lim_has_gpa3 = aa64isar2_has_gpa3(lim); + lim_has_apa3 = aa64isar2_has_apa3(lim); + + /* + * Check if there is a conflict in the requested value for + * ID_AA64ISAR2_EL1 with PTRAUTH configuration. + * See comments in validate_id_aa64isar1_el1() for more detail. + */ + if (lim_has_gpa3 && (vcpu_has_ptrauth(vcpu) ^ has_gpa3)) + return -EPERM; + + if (lim_has_apa3 && (vcpu_has_ptrauth(vcpu) ^ has_apa3)) + return -EPERM; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -550,6 +585,13 @@ static void init_id_aa64isar1_el1_desc(struct id_reg_desc *id_reg) id_reg->vcpu_limit_val &= ~ISAR1_TRAUTH_MASK; } +static void init_id_aa64isar2_el1_desc(struct id_reg_desc *id_reg) +{ + if (!system_has_full_ptr_auth()) + id_reg->vcpu_limit_val &= ~ISAR2_PTRAUTH_MASK; +} + + static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, const struct id_reg_desc *idr) { @@ -568,6 +610,13 @@ static u64 vcpu_mask_id_aa64isar1_el1(const struct kvm_vcpu *vcpu, return vcpu_has_ptrauth(vcpu) ? 0 : ISAR1_TRAUTH_MASK; } +static u64 vcpu_mask_id_aa64isar2_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *idr) +{ + return vcpu_has_ptrauth(vcpu) ? 0 : ISAR2_PTRAUTH_MASK; +} + + static int validate_id_reg(struct kvm_vcpu *vcpu, const struct id_reg_desc *id_reg, u64 val) { @@ -1544,11 +1593,6 @@ static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) val = read_kvm_id_reg(vcpu->kvm, id); switch (id) { - case SYS_ID_AA64ISAR2_EL1: - if (!vcpu_has_ptrauth(vcpu)) - val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) | - ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3)); - break; case SYS_ID_AA64DFR0_EL1: /* Limit debug to ARMv8.0 */ val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); @@ -3359,6 +3403,16 @@ static struct id_reg_desc id_aa64isar1_el1_desc = { }, }; +static struct id_reg_desc id_aa64isar2_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64ISAR2_EL1), + .init = init_id_aa64isar2_el1_desc, + .validate = validate_id_aa64isar2_el1, + .vcpu_mask = vcpu_mask_id_aa64isar2_el1, + .ftr_bits = { + U_FTR_BITS(FTR_EXACT, ID_AA64ISAR2_APA3_SHIFT, 0), + }, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -3371,6 +3425,7 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=6 */ ID_DESC(ID_AA64ISAR0_EL1, &id_aa64isar0_el1_desc), ID_DESC(ID_AA64ISAR1_EL1, &id_aa64isar1_el1_desc), + ID_DESC(ID_AA64ISAR2_EL1, &id_aa64isar2_el1_desc), }; static inline struct id_reg_desc *get_id_reg_desc(u32 id) From patchwork Tue Apr 19 06:55:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B304C433EF for ; Tue, 19 Apr 2022 07:02:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=23BSVB8OTl209XVL6WJW0UpR11ei42jQAel9XPk3fPs=; b=ytc0g8+vbUcHBq/VeUz1Zt7x2m JjT1l5gC5uMfabUY3QXowiH9OU+QNyQOAh9c3PM3aHoG64AoVROaaSAEPX1OltPzNoIuSEJZnosra grk7CWg5BeReNeDyKWHvqCtYjdwYZoZEw++vMqFW0MZifp3TRbYKWTnibNAMY9gPtrK0l0Ms4qEuy uaavLuHM9F1QOjVMfkoQTUYpkHrq1TJTu0Dc/tg9SfShRsWeHxEUPMs4L7SavDybivlKJfNkEfA7t 274tmtsAayDxH5nXHiTyPXfnVW361tdtMqZzPLO1sDXLUfiBNDMP9VKdpv2tOYAszY6U4h4gBT6hI nZ9ZMyDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghrm-001pCA-D2; Tue, 19 Apr 2022 07:01:39 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghng-001nSR-Ol for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:26 +0000 Received: by mail-pj1-x104a.google.com with SMTP id m8-20020a17090aab0800b001cb1320ef6eso1184668pjq.3 for ; Mon, 18 Apr 2022 23:57:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=5GFeg0Qhkqt0F/Jtoeb93WWvQllcpb+IlKZnd70ZJik=; b=Fv4yxIMKsOfPGl1VWc42zdtocbfbfZISNCLx3NGwULK0h1JKlUIWpfnlR/UL/RRMyA eKMYR3vCEvPzuoFW6dKiSVM7mNuCTj58732pG3PZ8cRx/V/jpgNu+AzLyMznTWkU7AYm XEbug58FYBe7rIGRKQkJPaCRjF6EBPjlknVNwBqVFn/SJT1P9Opmpy/2CQpay9I+WDBe hZwitU1DkclcjVe3OR1Fg1KMkZ5GPGfwYoC4VNzLLHXq+DhNlaG572W/i2tRZU+M/i+i Wp5xaAMVEBc0q1E5xZnp3K5MrJ62+uiDQ2cSm3mL+VFCJUUn4k8M7XbGWaLgDE7OWKPp ttBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=5GFeg0Qhkqt0F/Jtoeb93WWvQllcpb+IlKZnd70ZJik=; b=EnbVqtFWVer+Gqv36QEMCb3D/c1zORW2lQjmjOGtjJRxWpxNFzQ7XGhO54rdR8OIcy w93RfSG2cZCfeao2vYoSsOa0vITuqmN4N74tXPDAHEkUacz8P05fX9OtRpeekC9PAJvM uAFBadMY+6OCsGUxmgIig77B60M2cGT47sLCJSOPsxDNNpn9uaCukde3ovS3/KiLHstT 73aS14a/pqvx+pWqrc69ostO3lqR7UO9nzKFf3yfcxFzpOuAlnzre/zGbPgA8PLjBcA7 NMjOHHK9w/fk9K08JDex3GpQPYYrWsKSVAyBcS3nkcBslr7wNBGvTBre1j1e408y6hWu QSVA== X-Gm-Message-State: AOAM533mXox5rCifXn9cdScEacziU5lJaJIj0Io5J92KhVznJjON9903 AMbUnlLWU7g9cn1JYntXj0rKthJniIE= X-Google-Smtp-Source: ABdhPJxWTrb+BY8xwpwyXUFdaoymj4StHXGAR+lBoWQZOnAwK6U8eNBK6/ve0byeXMAGA0OzQxHDtDdAAhc= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:902:9696:b0:158:f809:310e with SMTP id n22-20020a170902969600b00158f809310emr9827150plp.16.1650351443506; Mon, 18 Apr 2022 23:57:23 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:17 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-12-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 11/38] KVM: arm64: Make ID_AA64MMFR0_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235724_846166_8D5828D7 X-CRM114-Status: GOOD ( 21.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64MMFR0_EL1 to make it writable by userspace. Since ID_AA64MMFR0_EL1 stage 2 granule size fields don't follow the standard ID scheme, we need a special handling to validate those fields. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 133 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ba2e6dac7774..b68ae53af792 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -542,6 +542,118 @@ static int validate_id_aa64isar2_el1(struct kvm_vcpu *vcpu, return 0; } +/* + * Check if the requested stage2 translation granule size indicated in + * @mmfr0 is also indicated in @mmfr0_lim. + * If TGranX_2 field is zero, the value must be validated based on TGranX + * field because that indicates the feature support is identified in + * TGranX field. + * This function relies on the fact TGranX fields are validated before + * through arm64_check_features. + */ +static int aa64mmfr0_tgran2_check(int field, u64 mmfr0, u64 mmfr0_lim) +{ + s64 tgran2, lim_tgran2, rtgran1; + int f1; + bool is_signed; + + tgran2 = cpuid_feature_extract_unsigned_field(mmfr0, field); + lim_tgran2 = cpuid_feature_extract_unsigned_field(mmfr0_lim, field); + if (tgran2 && lim_tgran2) + /* + * We don't need to check TGranX field. We can simply + * compare tgran2 and lim_tgran2. + */ + return (tgran2 > lim_tgran2) ? -E2BIG : 0; + + if (tgran2 == lim_tgran2) + /* + * Both of them are zero. Since TGranX in @mmfr0 is already + * validated by arm64_check_features, tgran2 must be fine. + */ + return 0; + + /* + * Either tgran2 or lim_tgran2 is zero. + * Need stage1 granule size to validate tgran2. + */ + + /* + * Get TGranX's bit position by subtracting 12 from TGranX_2's bit + * position. + */ + f1 = field - 12; + + /* TGran4/TGran64 is signed and TGran16 is unsigned field. */ + is_signed = (f1 == ID_AA64MMFR0_TGRAN16_SHIFT) ? false : true; + + /* + * If tgran2 == 0 (&& lim_tgran2 != 0), the requested stage2 granule + * size is indicated in the stage1 granule size field of @mmfr0. + * So, validate the stage1 granule size against the stage2 limit + * granule size. + * If lim_tgran2 == 0 (&& tgran2 != 0), the stage2 limit granule size + * is indicated in the stage1 granule size field of @mmfr0_lim. + * So, validate the requested stage2 granule size against the stage1 + * limit granule size. + */ + + /* Get the relevant stage1 granule size to validate tgran2 */ + if (tgran2 == 0) + /* The requested stage1 granule size */ + rtgran1 = cpuid_feature_extract_field(mmfr0, f1, is_signed); + else /* lim_tgran2 == 0 */ + /* The stage1 limit granule size */ + rtgran1 = cpuid_feature_extract_field(mmfr0_lim, f1, is_signed); + + /* + * Adjust the value of rtgran1 to compare with stage2 granule size, + * which indicates: 1: Not supported, 2: Supported, etc. + */ + if (is_signed) + /* For signed, -1: Not supported, 0: Supported, etc. */ + rtgran1 += 0x2; + else + /* For unsigned, 0: Not supported, 1: Supported, etc. */ + rtgran1 += 0x1; + + if ((tgran2 == 0) && (rtgran1 > lim_tgran2)) + /* + * The requested stage1 granule size (== the requested stage2 + * granule size) is larger than the stage2 limit granule size. + */ + return -E2BIG; + else if ((lim_tgran2 == 0) && (tgran2 > rtgran1)) + /* + * The requested stage2 granule size is larger than the stage1 + * limit granulze size (== the stage2 limit granule size). + */ + return -E2BIG; + + return 0; +} + +static int validate_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + u64 limit = id_reg->vcpu_limit_val; + int ret; + + ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN4_2_SHIFT, val, limit); + if (ret) + return ret; + + ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN64_2_SHIFT, val, limit); + if (ret) + return ret; + + ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN16_2_SHIFT, val, limit); + if (ret) + return ret; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -3413,6 +3525,24 @@ static struct id_reg_desc id_aa64isar2_el1_desc = { }, }; +static struct id_reg_desc id_aa64mmfr0_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64MMFR0_EL1), + /* + * When TGranX_2 value is 0, validity of the value depend on TGranX + * value, and TGranX_2 value must be validated against TGranX value, + * which is done by validate_id_aa64mmfr0_el1. + * So, skip the regular validity checking for TGranX_2 fields. + */ + .ignore_mask = ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN4_2) | + ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN64_2) | + ARM64_FEATURE_MASK(ID_AA64MMFR0_TGRAN16_2), + .validate = validate_id_aa64mmfr0_el1, + .ftr_bits = { + S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, ID_AA64MMFR0_TGRAN64_NI), + S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, ID_AA64MMFR0_TGRAN4_NI), + }, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -3426,6 +3556,9 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { ID_DESC(ID_AA64ISAR0_EL1, &id_aa64isar0_el1_desc), ID_DESC(ID_AA64ISAR1_EL1, &id_aa64isar1_el1_desc), ID_DESC(ID_AA64ISAR2_EL1, &id_aa64isar2_el1_desc), + + /* CRm=7 */ + ID_DESC(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1_desc), }; static inline struct id_reg_desc *get_id_reg_desc(u32 id) From patchwork Tue Apr 19 06:55:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D679C433EF for ; Tue, 19 Apr 2022 07:03:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=L/8UdfHm/kQazRdQJLBsTTA47u11GSmSY/sGQpAA3sA=; b=mUBIcoVCdVoSXLkL5Y1hj1/GdZ 0KcaldRADKw5YyBndgjYuWYdlKbS/DYAtybsqemqsW5iCtC4Hj1yPU9e7rSJpURq58BghzDyp4Vsw pDZllskCyjOf71lpFdgSDVVduMA9Q9kLMAz1aFW1pF0xxOB/SmZbHoEt/kcgg73IqlWuNPHJ2k2vo QhMwII3XBpjUSq5gcJQXjCHRlmTYvYZ0kocEYljfKdqEzqRuTw5IHRp5sQS8olGjJAR4YJjIeejNR YeAgtOIkh4JGD5WXrvH1X0DoW3b0q3wf1utebzVLdECD2/fd/xiEgMxN6vcup4weuosyz7IMeoOit db0hVb/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghsD-001pMI-Hl; Tue, 19 Apr 2022 07:02:05 +0000 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghni-001nTJ-LV for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:28 +0000 Received: by mail-pl1-x64a.google.com with SMTP id f6-20020a170902ab8600b0015895212d23so9243328plr.6 for ; Mon, 18 Apr 2022 23:57:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=/vjKAR/Lgrfopo8hEj0HEcKOQxQlZW68o1SkmclVnl4=; b=lzf/QpdqQv9uzaV5AJLSdksISlhdMJg0/X4yt3SQ6Pbv0hF+PdxOMJ8pLE+rdZv61f i15qaeHVtYUyP2dfbRSZD25p4C+rxzvhNV9nTEdGdED+ftIuvIRX25CuQu7SsRHKay0I YG15YkYFJ5L5ER/Zlz9Lcy7QJPO3/2Pguy2ljgPmnfmTnwIn/U+BDnLd59tE5llgaax2 QlBXRvDLgcj/dqlkHez/TKqYPZBwwn9BUAGjjkRm4puiWejX/Kpf36vPPJRPn+7i7tqr zy+Ew1QFJeF2Kin3d8ZeIH0wYeZGlKFCjcM7cAb5Ib41YdGcj2wXN2yIFxLOuyzLvU3S gxog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=/vjKAR/Lgrfopo8hEj0HEcKOQxQlZW68o1SkmclVnl4=; b=Fz58HYF3iJ21RruXeiFDOU2vmTTIxRMx/eo4cq8+SheUsGWvEw496feQZaYHQc09ch 9FcTaeYW+IF1PGV7Wl4BUw4tgpLlAJu5ETqKJmRI+uJhtMiJJ8LkjK59VM0YV55kg3EG NdYU9G5BeT96aybmbpID4voyf6icndOOU4A5mQ/hY1elIZn9v0BxNwMFyNpkA5VRsc4f 5M814YMsjDk+eJmdoQjPJJdtvJlveuQ9Nl1b8cl/Z+vfH5MpNCAPOuJUioEDzFfi6FNU fnHFYd2TVlrMqJRT/GGLkfKO8+n2yGU27+cG2dBqo5CmOfK7uIC+R2k8K/C/49B7hjWt 5Asw== X-Gm-Message-State: AOAM532KBXRTh+XqF17g3kv/YKPr6n46DE1uKzZpP1IJ3isQqThQe42J FOj46D9yn99YuXfPuhlz1ZtNdST/91A= X-Google-Smtp-Source: ABdhPJwLgiVYSYP5oQPSjEjSHx+cLaLtR0/2B0FVBvNOlRvoxy7xj829DfShZuFzYw4gbA0oeKTgAhX0I3s= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:10c7:b0:4fd:9ee6:4130 with SMTP id d7-20020a056a0010c700b004fd9ee64130mr16718408pfu.84.1650351445278; Mon, 18 Apr 2022 23:57:25 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:18 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-13-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 12/38] KVM: arm64: Add a KVM flag indicating emulating debug regs access is needed From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235726_757445_AD3C7A18 X-CRM114-Status: GOOD ( 19.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Highest numbered breakpoints must be context aware breakpoints (as specified by Arm ARM). If the number of non-context aware breakpoints for the guest is decreased by userspace, simply narrowing the breakpoints will be problematic because it will lead to narrowing context aware breakpoints for the guest. Introduce KVM_ARCH_FLAG_EMULATE_DEBUG_REGS for kvm->arch.flags to indicate trapping debug reg access is needed, and enable the trapping when the flag is set. Set the new flag at the first KVM_RUN if the number of non-context aware breakpoints for the guest is decreased by userspace. No code sets the new flag yet since ID_AA64DFR0_EL1 is not configurable by userspace. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/debug.c | 7 ++++++- arch/arm64/kvm/sys_regs.c | 35 +++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index a43fddd58e68..dbed94e759a8 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -136,6 +136,8 @@ struct kvm_arch { */ #define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 3 #define KVM_ARCH_FLAG_EL1_32BIT 4 + /* Access to debug registers need to be emulated ? */ +#define KVM_ARCH_FLAG_EMULATE_DEBUG_REGS 5 unsigned long flags; @@ -786,6 +788,7 @@ long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, void set_default_id_regs(struct kvm *kvm); int kvm_set_id_reg_feature(struct kvm *kvm, u32 id, u8 field_shift, u8 fval); +void kvm_vcpu_breakpoint_config(struct kvm_vcpu *vcpu); /* Guest/host FPSIMD coordination helpers */ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 4fd5c216c4bb..6eb146d908f8 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -106,10 +106,14 @@ static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu) * (KVM_GUESTDBG_USE_HW is set). * - The guest is not using debug (KVM_ARM64_DEBUG_DIRTY is clear). * - The guest has enabled the OS Lock (debug exceptions are blocked). + * - The guest's access to debug registers needs to be emulated + * (the number of non-context aware breakpoints for the guest + * is decreased by userspace). */ if ((vcpu->guest_debug & KVM_GUESTDBG_USE_HW) || !(vcpu->arch.flags & KVM_ARM64_DEBUG_DIRTY) || - kvm_vcpu_os_lock_enabled(vcpu)) + kvm_vcpu_os_lock_enabled(vcpu) || + test_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &vcpu->kvm->arch.flags)) vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA; trace_kvm_arm_set_dreg32("MDCR_EL2", vcpu->arch.mdcr_el2); @@ -124,6 +128,7 @@ static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu) */ void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu) { + kvm_vcpu_breakpoint_config(vcpu); preempt_disable(); kvm_arm_setup_mdcr_el2(vcpu); preempt_enable(); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b68ae53af792..f4aae4ccffd0 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -844,6 +844,41 @@ static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, } } +#define AA64DFR0_BRPS(v) \ + ((u8)cpuid_feature_extract_unsigned_field(v, ID_AA64DFR0_BRPS_SHIFT)) +#define AA64DFR0_CTX_CMPS(v) \ + ((u8)cpuid_feature_extract_unsigned_field(v, ID_AA64DFR0_CTX_CMPS_SHIFT)) + +/* + * Set KVM_ARCH_FLAG_EMULATE_DEBUG_REGS in the VM flags when the number of + * non-context aware breakpoints for the guest is decreased by userspace + * (meaning that debug register accesses need to be emulated). + */ +void kvm_vcpu_breakpoint_config(struct kvm_vcpu *vcpu) +{ + u64 p_val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + u64 v_val = read_id_reg_with_encoding(vcpu, SYS_ID_AA64DFR0_EL1); + u8 v_nbpn, p_nbpn; + struct kvm *kvm = vcpu->kvm; + + /* + * Check the number of normal (non-context aware) breakpoints + * for the guest and the host. + */ + v_nbpn = AA64DFR0_BRPS(v_val) - AA64DFR0_CTX_CMPS(v_val); + p_nbpn = AA64DFR0_BRPS(p_val) - AA64DFR0_CTX_CMPS(p_val); + if (v_nbpn >= p_nbpn) + /* + * Nothing to do if the number of normal breakpoints for the + * guest is not decreased by userspace (meaning KVM doesn't + * need to emulate an access of debug registers). + */ + return; + + if (!test_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &kvm->arch.flags)) + set_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &kvm->arch.flags); +} + /* * We want to avoid world-switching all the DBG registers all the * time: From patchwork Tue Apr 19 06:55:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EF71C433F5 for ; Tue, 19 Apr 2022 07:03:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=uisAcYVANck3p+BVn57ol8N4YtH3bEHtOktikGWrrGc=; b=mu0d3Cit81oHXPDFtX8MNx0BjB +V8iAlqonAoRcAtr1zpg6ea/6cMj058FwWIPNx7RKJ+vX+0BuQuutA6q9fIFYurUUMrMzqOz3XRn2 PDbf3RTzrxC3sPG8zvIvhDwYhWtvPOu6MyRoLnA74JPr23tnooKcbvXGo2OHVEUZIxS+ZBJ1RL4vi z8vP6b6WR5PWJyW7olMpELRcfzQFXAme7oItaiqTU+9bPyiMpRxmFd0LCMr4wzbQQjCZ8dP+kARmj Ud2cwrQzzo5V89NltAIBN59jSWcf99/OtAnNsnEfwZhsn7FRZ60mBcJzo4cD6HoxByw3wn8bHYGYg RBU1iPlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghsa-001pVv-U8; Tue, 19 Apr 2022 07:02:30 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnk-001nU4-ED for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:31 +0000 Received: by mail-pj1-x104a.google.com with SMTP id f2-20020a17090a120200b001cbae0449edso10135681pja.4 for ; Mon, 18 Apr 2022 23:57:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=mY58E5CEbgw/vqLwN8lNA68QyCXeYwjNR+19470Skts=; b=D9zNYiG8IagBlgPRP6t0YDQ+UlvsGKN1XK37MKVh6q28jhcUIa9Dmu/Pqz+qwMe1Hc 9uD0B35UcJfiqoc71UhvmiHmKtEnNVWeNIkJoAMkRrdBl2be+AF27TcvlrHKPoTrMhaA e6v9dP6oybbI9bM7vBx8tYi68GW9bHnu7Bp71AuzVNDqc1f/4Oanh5XM5bbRDPpiCHTH vj2pgmJaD+pcfNRdyTlvO0suXsOBx+H3lOgtUjeIVkAy5nZn5baXdR5KIj6wRhjxvHMw TUKV8iYlDIpkM12jHcrfWsRj1X7mku9VxlrMDIz6YL8oEgOPUXW+T7IOQ5Mu6VRoxwbT O+sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=mY58E5CEbgw/vqLwN8lNA68QyCXeYwjNR+19470Skts=; b=5xn8iYEbfB+CXsetv/GBJzdkpyKQ9KHIwIwnSTAypyGEqeMzjVt7q1GKTCfGyB8Ndi 0GTVMTdEw1GaiRI8GnKX6/O75DSL2QPpKm+MQb0Dli3l9SY3KkQKUBWlhH8xj9AzxMog PJMpShPWYjx6bbm/8UiHXFVA+ohvEbB0TL9/5nB6jlAvca8FX8OV90VT6zhsX6FBBCr4 dhriTdLJJNETKRFuwi345SVrQu+CBZDCwAvKy3HokidqC1mJGI9uGZbCnwqHksCDtx0L DR8RKHugKPVyFb6qFqHCsy7mCWcgj//l+15uiEzr3VVxcJtYDn6bCCTmfzrOo+p5Rzoj LyfQ== X-Gm-Message-State: AOAM530leyITbxOlGBub0R666WHvd7YLRlEPtPHN2uIbVtTZDcPVvOtp NcBiCn9yOWcogfTRixnFdReKShjM7As= X-Google-Smtp-Source: ABdhPJyb61f6We7WvnJKdvErxty6ITBIiKAYfzLLP0LpiwJQ8vRqfcew7l+CKCajxhuS3Re/rGFp4Iewv4A= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:902:aa88:b0:156:914b:dc79 with SMTP id d8-20020a170902aa8800b00156914bdc79mr14409922plr.138.1650351447051; Mon, 18 Apr 2022 23:57:27 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:19 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-14-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 13/38] KVM: arm64: Emulate dbgbcr/dbgbvr accesses From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235728_643701_EBD2F8A7 X-CRM114-Status: GOOD ( 32.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Highest numbered breakpoints must be context aware breakpoints (as specified by Arm ARM). If the number of non-context aware breakpoints for the guest is decreased by userspace (e.g. Lower ID_AA64DFR0.BRPs keeping ID_AA64DFR0.CTX_CMPs the same), simply narrowing the breakpoints will be problematic because it will lead to narrowing context aware breakpoints for the guest. Emulate dbgbcr/dbgbvr accesses in that case and map context aware breakpoints for the vCPU to different numbered breakpoints for the pCPU, but will maintain the offset in context aware breakpoints. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/sysreg.h | 9 +- arch/arm64/kvm/sys_regs.c | 402 ++++++++++++++++++++++++++++++-- 2 files changed, 394 insertions(+), 17 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b33b7ce87fb2..9b475ba95ffd 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -124,9 +124,16 @@ #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) -#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) + +#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) +#define SYS_DBGBCR_EL1_LBN_SHIFT 16 +#define SYS_DBGBCR_EL1_LBN_MASK GENMASK(3, 0) + #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) +#define SYS_DBGWCR_EL1_LBN_SHIFT 16 +#define SYS_DBGWCR_EL1_LBN_MASK GENMASK(3, 0) + #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f4aae4ccffd0..2ee1e0b6c4ce 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -849,17 +849,230 @@ static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, #define AA64DFR0_CTX_CMPS(v) \ ((u8)cpuid_feature_extract_unsigned_field(v, ID_AA64DFR0_CTX_CMPS_SHIFT)) +#define INVALID_BRPN ((u8)-1) + +static u8 get_bcr_lbn(u64 val) +{ + return ((val >> SYS_DBGBCR_EL1_LBN_SHIFT) & SYS_DBGBCR_EL1_LBN_MASK); +} + +static u64 update_bcr_lbn(u64 val, u8 lbn) +{ + u64 new; + + new = val & ~(SYS_DBGBCR_EL1_LBN_MASK << SYS_DBGBCR_EL1_LBN_SHIFT); + new |= ((u64)lbn & SYS_DBGBCR_EL1_LBN_MASK) << SYS_DBGBCR_EL1_LBN_SHIFT; + return new; +} + +/* + * KVM will emulate breakpoints access when the number of non-context + * aware (normal) breakpoints is decreased for the guest. For instsance, + * it will happen when userspace decreases the number of breakpoints + * for the guest keeping the same number of context aware breakpoints. + * Simply narrowing the number of breakpoints for the guest will lead + * to narrowing context aware breakpoints for the guest because as per + * Arm ARM, highest numbered breakpoints are context aware breakpoints. + * So, in that case, KVM will map context aware breakpoints for the + * vCPU to different numbered breakpoints for the pCPU, but will + * maintain the offset in context aware breakpoints. + * For instance, if 5 breakpoints are supported, and 2 of them are + * context aware breakpoints, breakpoint#0, #1 and #2 are normal + * breakpoints, and #3 and #4 are context aware breakpoints. + * If userspace decreases the number of breakpoints to 4 keeping the + * same number of context aware breakpoints (== 2), the guest expects + * breakpoint#0 and #1 to be normal breakpoints, and #2 and #3 to be + * context aware breakpoints. So, KVM will map the (virtual) context + * aware breakpoint #2 and #3 for the vCPU to (physical) context aware + * breakpoint #3 and #4 for the pCPU as follows. + * + * [Example] + * + * Normal Breakpoints Context aware breakpoints + * Virtual #0 #1 #2 #3 + * | | | | + * Physical #0 #1 #2 #3 #4 + * + * So, dbg{b,w}cr.lbn (linked breakpoint number) for vCPU might be + * different from the ones for pCPU (e.g. With the above example, + * when the guest sets dbgbcr0.lbn to 2 for the vCPU, dbgbcr0.lbn + * for the pCPU should be set to 3). + * Values in vcpu_debug_state of kvm_vcpu_arch will basically be the ones + * that are going to be set to the physical registers (indexed by physical + * context breakpoint number). But, they hold the values from the guest + * point of view until the first KVM_RUN (physical/virtual breakpoint + * numbers mapping is fixed) and they will be converted to the + * physical values during the process of first KVM_RUN. + * + * As there is no functional difference between any watchpoints, + * virtual watchpoint# will be always same as physical watchpoint#. + */ + +/* + * Convert breakpoint# for the guest to breakpoint# for the real hardware. + * Return INVALID_BRPN if the given breakpoint# is invalid. + */ +static inline u8 virt_to_phys_bpn(struct kvm_vcpu *vcpu, u8 v_bpn) +{ + u8 virt_ctx_base, phys_ctx_base; + u64 p_val, v_val; + + v_val = read_id_reg_with_encoding(vcpu, SYS_ID_AA64DFR0_EL1); + if (v_bpn > AA64DFR0_BRPS(v_val)) { + /* + * The virtual bpn is out of valid virtual breakpoint number + * range. Return the invalid breakpoint number. + */ + return INVALID_BRPN; + } + + if (!test_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &vcpu->kvm->arch.flags)) + /* physical bpn == virtual bpn when no emulation is needed */ + return v_bpn; + + /* The lowest virtual context aware bpn */ + virt_ctx_base = AA64DFR0_BRPS(v_val) - AA64DFR0_CTX_CMPS(v_val); + if (v_bpn < virt_ctx_base) + /* + * physical bpn == virtual bpn when v_bpn is not a + * context aware breakpoint. + */ + return v_bpn; + + p_val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + /* The lowest physical context aware bpn */ + phys_ctx_base = AA64DFR0_BRPS(p_val) - AA64DFR0_CTX_CMPS(p_val); + + WARN_ON_ONCE(virt_ctx_base >= phys_ctx_base); + + /* + * Context aware bpn. Map it to the same offset of physical + * context aware registers. + */ + return phys_ctx_base + (v_bpn - virt_ctx_base); +} + /* - * Set KVM_ARCH_FLAG_EMULATE_DEBUG_REGS in the VM flags when the number of - * non-context aware breakpoints for the guest is decreased by userspace - * (meaning that debug register accesses need to be emulated). + * Convert breakpoint# for the real hardware to breakpoint# for the guest. + * Return INVALID_BRPN if the given breakpoint# is not used for the guest. + */ +static inline u8 phys_to_virt_bpn(struct kvm_vcpu *vcpu, u8 p_bpn) +{ + u8 virt_ctx_base, phys_ctx_base, v_bpn; + u64 p_val, v_val; + + if (!test_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &vcpu->kvm->arch.flags)) + return p_bpn; + + v_val = read_id_reg_with_encoding(vcpu, SYS_ID_AA64DFR0_EL1); + + /* The lowest virtual context aware bpn */ + virt_ctx_base = AA64DFR0_BRPS(v_val) - AA64DFR0_CTX_CMPS(v_val); + if (p_bpn < virt_ctx_base) + /* + * physical bpn == virtual bpn when p_bpn is smaller than + * the lowest virutual context aware breakpoint number. + */ + return p_bpn; + + p_val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + + /* The lowest physical context aware bpn */ + phys_ctx_base = AA64DFR0_BRPS(p_val) - AA64DFR0_CTX_CMPS(p_val); + if (p_bpn < phys_ctx_base) + /* + * Unused non-context aware breakpoint. + * No virtual breakpoint is assigned for this. + */ + return INVALID_BRPN; + + WARN_ON_ONCE(virt_ctx_base >= phys_ctx_base); + + /* + * Context aware bpn. Map it to the same offset of virtual + * context aware registers. + */ + v_bpn = virt_ctx_base + (p_bpn - phys_ctx_base); + if (v_bpn > AA64DFR0_BRPS(v_val)) { + /* This pysical bpn is not mapped to any virtual bpn */ + return INVALID_BRPN; + } + + return v_bpn; +} + +static u8 get_unused_p_bpn(struct kvm_vcpu *vcpu) +{ + u64 p_val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); + + WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &vcpu->kvm->arch.flags)); + + /* + * The last normal (non-context aware) break point is always unused + * (and disabled) when kvm_arm_need_emulate_debug_regs() is true. + */ + return AA64DFR0_BRPS(p_val) - AA64DFR0_CTX_CMPS(p_val) - 1; +} + +/* + * virt_to_phys_bcr() converts the virtual bcr value (the bcr value from + * the guest point of view) to physical bcr value, which is going to be set + * to the real hardware. More specifically, as a lbn field value of the + * virtual bcr includes the virtual breakpoint number, the function will + * update the bcr with physical breakpoint number, and will return it as + * the physical bcr value. phys_to_virt_bcr()) does the opposite. + * + * As per Arm ARM (ARM DDI 0487H.a), if a Linked Address breakpoint links + * to a breakpoint that is not implemented or that is not context aware, + * then reads of bcr.lbn return an unknown value, and the Linked Address + * breakpoint behaves as if it is either disabled or linked to an UNKNOWN + * context aware breakpoint. In such cases, KVM will return 0 to reads of + * bcr.lbn, and have the breakpoint behaves as if it is disabled by + * setting the lbn to unused (disabled) breakpoint. + */ +static u64 virt_to_phys_bcr(struct kvm_vcpu *vcpu, u64 v_bcr) +{ + u8 v_lbn, p_lbn; + + v_lbn = get_bcr_lbn(v_bcr); + p_lbn = virt_to_phys_bpn(vcpu, v_lbn); + if (p_lbn == INVALID_BRPN) + p_lbn = get_unused_p_bpn(vcpu); + + return update_bcr_lbn(v_bcr, p_lbn); +} + +static u64 phys_to_virt_bcr(struct kvm_vcpu *vcpu, u64 p_bcr) +{ + u8 v_lbn, p_lbn; + + p_lbn = get_bcr_lbn(p_bcr); + v_lbn = phys_to_virt_bpn(vcpu, p_lbn); + if (v_lbn == INVALID_BRPN) + v_lbn = 0; + + return update_bcr_lbn(p_bcr, v_lbn); +} + +/* + * Check if the number of normal breakpoints for the guest is same as + * the one for the host. If so, do nothing. + * Otherwise (accesses of debug registers needs to be emulated), set + * KVM_ARCH_FLAG_EMULATE_DEBUG_REGS in the VM flags, and convert values + * in vcpu->arch.vcpu_debug_state that are values from the guest + * point of view to values that are going to be set to hardware + * registers. See comments for set_bvr() for some more details. */ void kvm_vcpu_breakpoint_config(struct kvm_vcpu *vcpu) { u64 p_val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); u64 v_val = read_id_reg_with_encoding(vcpu, SYS_ID_AA64DFR0_EL1); u8 v_nbpn, p_nbpn; + u64 p_bcr; struct kvm *kvm = vcpu->kvm; + int v; + u8 p_bpn; + struct kvm_guest_debug_arch *dbg = &vcpu->arch.vcpu_debug_state; /* * Check the number of normal (non-context aware) breakpoints @@ -877,11 +1090,39 @@ void kvm_vcpu_breakpoint_config(struct kvm_vcpu *vcpu) if (!test_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &kvm->arch.flags)) set_bit(KVM_ARCH_FLAG_EMULATE_DEBUG_REGS, &kvm->arch.flags); + + /* + * Before the first KVM_RUN, vcpu->arch.vcpu_debug_state holds + * values of the registers to be exposed to the guest and their + * positions are indexed by virtual breakpoint numbers. + * Convert the values to physical values that are going to set + * to hardware registers, and move them to positions indexed + * by physical breakpoint numbers. + */ + for (v = KVM_ARM_MAX_DBG_REGS - 1; v >= 0; v--) { + /* Get physical breakpoint number */ + p_bpn = virt_to_phys_bpn(vcpu, v); + WARN_ON_ONCE(p_bpn < v); + + if (p_bpn != INVALID_BRPN) { + /* Get physical bcr */ + p_bcr = virt_to_phys_bcr(vcpu, dbg->dbg_bcr[v]); + dbg->dbg_bcr[p_bpn] = p_bcr; + dbg->dbg_bvr[p_bpn] = dbg->dbg_bvr[v]; + } + + /* Clear dbg_b{c,v}r, which might not be used */ + if (p_bpn != v) { + dbg->dbg_bcr[v] = 0; + dbg->dbg_bvr[v] = 0; + } + } } /* * We want to avoid world-switching all the DBG registers all the - * time: + * time unless userspace decrease number of non-context break points, + * where emulating of access to debug registers is required. * * - If we've touched any debug register, it is likely that we're * going to touch more of them. It then makes sense to disable the @@ -963,8 +1204,17 @@ static bool trap_bvr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd) { - u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; + u64 p_bpn; + u64 *dbg_reg; + /* Convert the virt breakpoint num to phys breakpoint num */ + p_bpn = virt_to_phys_bpn(vcpu, rd->CRm); + if (p_bpn == INVALID_BRPN) { + kvm_inject_undefined(vcpu); + return false; + } + + dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[p_bpn]; if (p->is_write) reg_to_dbg(vcpu, p, rd, dbg_reg); else @@ -975,23 +1225,85 @@ static bool trap_bvr(struct kvm_vcpu *vcpu, return true; } +/* + * The behaviors of {s,g}et_b{c,v}r change depending on whether they + * are called before or after the first KVM_RUN. + * + * Before the first KVM_RUN (the number of breakpoints is not fixed yet), + * the vcpu->arch.vcpu_debug_state holds debug register values from + * the guest point of view. The set_b{c,v}r() simply save the value + * from userspace in vcpu->arch.vcpu_debug_state, and get_b{c,v}r() + * simply return the value in vcpu->arch.vcpu_debug_state to userspace. + * + * At the first KVM_RUN (where the number of breakpoints is immutable), + * b{c,v}r values in vcpu->arch.vcpu_debug_state are converted to + * the values that are going to be set to hardware registers. + * After that, vcpu->arch.vcpu_debug_state holds debug register values that + * are going to set to hardware registers. The set_b{c,v}r functions convert + * the value from userspace to the one that will be set to the hardware + * register and save the converted value in vcpu->arch.vcpu_debug_state. + * The get_b{c,v}r functions read the value from vcpu->arch.vcpu_debug_state, + * convert it to the value as seen by the guest and return the converted + * value to the userspace. + * + * The {s,g}et_b{c,v}r will treat the invalid breakpoint registers, + * which are not mapped to physical breakpoints, as RAZ/WI after the first + * KVM_RUN (values that userspace attempts to set in those registers will + * not be saved anywhere), which shouldn't be a problem because they will + * never be exposed to the guest anyway. Until the first KVM_RUN, setting + * and getting of those work normally though (The number of breakpoints + * could be changed by userspace until the first KVM_RUN). + */ static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr) { - __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; + u8 v_bpn, p_bpn; + __u64 bvr; - if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) + if (copy_from_user(&bvr, uaddr, KVM_REG_SIZE(reg->id)) != 0) return -EFAULT; + + v_bpn = rd->CRm; + + /* + * Until the first KVM_RUN, vcpu_debug_state holds the virtual bvr. + * After that, vcpu_debug_state holds the physical bvr. + */ + if (vcpu_has_run_once(vcpu)) { + /* Convert the virt breakpoint num to phys breakpoint num */ + p_bpn = virt_to_phys_bpn(vcpu, v_bpn); + if (p_bpn != INVALID_BRPN) + vcpu->arch.vcpu_debug_state.dbg_bvr[p_bpn] = bvr; + } else { + vcpu->arch.vcpu_debug_state.dbg_bvr[v_bpn] = bvr; + } + return 0; } static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr) { - __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; + u8 v_bpn, p_bpn; + u64 bvr = 0; - if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) + v_bpn = rd->CRm; + /* + * Until the first KVM_RUN, vcpu_debug_state holds the virtual bvr. + * After that, vcpu_debug_state holds the physical bvr. + */ + if (vcpu_has_run_once(vcpu)) { + /* Convert the virt breakpoint num to phys breakpoint num */ + p_bpn = virt_to_phys_bpn(vcpu, v_bpn); + if (p_bpn != INVALID_BRPN) + bvr = vcpu->arch.vcpu_debug_state.dbg_bvr[p_bpn]; + } else { + bvr = vcpu->arch.vcpu_debug_state.dbg_bvr[v_bpn]; + } + + if (copy_to_user(uaddr, &bvr, KVM_REG_SIZE(reg->id)) != 0) return -EFAULT; + return 0; } @@ -1005,12 +1317,27 @@ static bool trap_bcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd) { - u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; + u8 p_bpn; + u64 *dbg_reg; - if (p->is_write) + /* Convert the given virt breakpoint num to phys breakpoint num */ + p_bpn = virt_to_phys_bpn(vcpu, rd->CRm); + if (p_bpn == INVALID_BRPN) { + /* Invalid breakpoint number */ + kvm_inject_undefined(vcpu); + return false; + } + + dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[p_bpn]; + if (p->is_write) { + /* Convert virtual bcr to physical bcr */ + p->regval = virt_to_phys_bcr(vcpu, p->regval); reg_to_dbg(vcpu, p, rd, dbg_reg); - else + } else { dbg_to_reg(vcpu, p, rd, dbg_reg); + /* Convert physical bcr to virtual bcr */ + p->regval = phys_to_virt_bcr(vcpu, p->regval); + } trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); @@ -1020,21 +1347,64 @@ static bool trap_bcr(struct kvm_vcpu *vcpu, static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr) { - __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; + u8 v_bpn, p_bpn; + u64 v_bcr, p_bcr; - if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) + if (copy_from_user(&v_bcr, uaddr, KVM_REG_SIZE(reg->id)) != 0) return -EFAULT; + v_bpn = rd->CRm; + + /* + * Until the first KVM_RUN, vcpu_debug_state holds the virtual bcr. + * After that, vcpu_debug_state holds the physical bcr. + */ + if (vcpu_has_run_once(vcpu)) { + /* Convert the virt breakpoint num to phys breakpoint num */ + p_bpn = virt_to_phys_bpn(vcpu, v_bpn); + if (p_bpn != INVALID_BRPN) { + /* Convert virt bcr to phys bcr, and save it */ + p_bcr = virt_to_phys_bcr(vcpu, v_bcr); + vcpu->arch.vcpu_debug_state.dbg_bcr[p_bpn] = p_bcr; + } + } else { + vcpu->arch.vcpu_debug_state.dbg_bcr[v_bpn] = v_bcr; + } + return 0; } static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr) { - __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; + u8 v_bpn, p_bpn; + u64 v_bcr = 0; + u64 p_bcr; - if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) + v_bpn = rd->CRm; + /* + * Until the first KVM_RUN, vcpu_debug_state holds the virtual bcr. + * After that, vcpu_debug_state holds the physical bcr. + */ + if (vcpu_has_run_once(vcpu)) { + /* + * Convert the virtual breakpoint num to phys breakpoint num, + * and get the physical bcr value. + */ + p_bpn = virt_to_phys_bpn(vcpu, v_bpn); + if (p_bpn != INVALID_BRPN) { + p_bcr = vcpu->arch.vcpu_debug_state.dbg_bcr[p_bpn]; + + /* Convert physical bcr to */ + v_bcr = phys_to_virt_bcr(vcpu, p_bcr); + } + } else { + v_bcr = vcpu->arch.vcpu_debug_state.dbg_bcr[v_bpn]; + } + + if (copy_to_user(uaddr, &v_bcr, KVM_REG_SIZE(reg->id)) != 0) return -EFAULT; + return 0; } From patchwork Tue Apr 19 06:55:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC035C433F5 for ; Tue, 19 Apr 2022 07:04:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=PqOxH/c70gLaFYlSodoZgf2nW4Cw/cy/Gwe5H75xzSg=; b=eW2RFUdq75rLEnQ2JOl8QaxKV5 SHwv4Bds+nfNQXUrjMAUPuxy0S881VCbh0S4aKr7ZzTahjSUjgztyYw0uXUA6Y2GR6VY8RMhL/UTB yiLc58XJvTjuYyOTlkaREQofOI4xliZGoe2+KWz7/7+YjM2CLFvuujFlqKKB3zQiduUmKnJR8l7a6 E6Vuws2NGkmtmXwk84Ej5AuUhLzz0vEOCQYpt10mGZg5z1kWz2OTLb9e6EWOWGX89oEVLBFYCJ/6J c7MGTrExbZ1i0pXi9ZN1FI4JjUSF5NhhNChAnLkUOckNJtCruIyYHGyJQUtjS78YIOnGKxjHT3tss wALf51zg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nght5-001pi1-J8; Tue, 19 Apr 2022 07:03:00 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnl-001nV3-NN for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:31 +0000 Received: by mail-pj1-x104a.google.com with SMTP id m8-20020a17090aab0800b001cb1320ef6eso1184879pjq.3 for ; Mon, 18 Apr 2022 23:57:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=/yJ16Mt8opbnIyJryWZlW/i1DVrAZ8RKhaEoLi7HeB0=; b=Oe/2r91Emsx2E5PbEGyFON5CMQ7peKXfIkYXEf+Dvwk+h+u7bTcu0sBc4gLyoKxIqe XGSuzcD9KtYTafz5OTh3OFd/1t82KCEb84vU1lrEnz5sUBjGDEJiHlmIzgnkEjxLzbjf zTMQApVrXK3YKvRyA7Y8Yp0SQVzCjUw7DpQU+E5bKq2oBBkWW4nJZMxqQiusH6/3IuUB fsYEmmr90eKI3K02a2qWau+duznVKS49GPzwEeza6t4nlhGMnErtXr1QueZ4lYBhOPHl mtsPvHa3LrDGjLkYt68ESClCa+EAhZqkacUniOd41o4QKzbc7KqgesHgLcbM0lCZbMU9 J/sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=/yJ16Mt8opbnIyJryWZlW/i1DVrAZ8RKhaEoLi7HeB0=; b=73lf/x3VSdwZa9+CbyUjchJIIUsK6KRD8EG5HKR3AX5BPV1x1QaRWnASzLM1r4ospc FgGSm9PumLH+ECKKqh/k+KLkjrMfs4XYOGgl0B0mODIDjRYcUnqcz3aX59EeAOXqcMaM 7PVjRIGgYIJaOC1H+WBduAM3rWJmAzfU3HGv/rV3sz3h+rg1CHYfD1MPO1zk8agvfw4L Hk91kGKVFx4y0tZ9Q/oqQdkvmPtzHyjYgP+N1l4rocWXy+SADUNmPKbtcClvupne/BUq Odh08wlWTyIgiHDpltqQmkOdKFFsax5CLatnCoNpOYBw1VDzAeFbhkJ1UOL/JWQvSVkB /wbA== X-Gm-Message-State: AOAM5310N2tJV0zCCZ/0c/TUtcPlgk5cYcW4e3fSX4Cimi7OwnjUrSM5 vw5jc+RtvzydcBJL5e2gsEb6NmGQTkQ= X-Google-Smtp-Source: ABdhPJzpVHE/Hi3uFTH3s8KCL9eFCGTPtBsk8Cj93lThGw5OG+gm74bF/4mO6VJ4yjWrPGmPVAnQI23BLZ4= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90a:8a90:b0:1d2:a931:3a03 with SMTP id x16-20020a17090a8a9000b001d2a9313a03mr7597147pjn.69.1650351448687; Mon, 18 Apr 2022 23:57:28 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:20 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-15-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 14/38] KVM: arm64: Emulate dbgwcr accesses From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235729_844074_57F625B1 X-CRM114-Status: GOOD ( 18.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the number of non-context aware breakpoints for the guest is decreased by userspace, KVM will map vCPU's context-aware breakpoints (from the guest point of view) to pCPU's context aware breakpoints. Since dbgwcr.lbn holds a linked breakpoint number, emulate dbgwcr accesses to do conversion of virtual/physical dbgwcr.lbn as needed. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 110 ++++++++++++++++++++++++++++++++------ 1 file changed, 95 insertions(+), 15 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2ee1e0b6c4ce..400fa7ff582f 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -846,20 +846,28 @@ static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, #define AA64DFR0_BRPS(v) \ ((u8)cpuid_feature_extract_unsigned_field(v, ID_AA64DFR0_BRPS_SHIFT)) +#define AA64DFR0_WRPS(v) \ + ((u8)cpuid_feature_extract_unsigned_field(v, ID_AA64DFR0_WRPS_SHIFT)) #define AA64DFR0_CTX_CMPS(v) \ ((u8)cpuid_feature_extract_unsigned_field(v, ID_AA64DFR0_CTX_CMPS_SHIFT)) #define INVALID_BRPN ((u8)-1) -static u8 get_bcr_lbn(u64 val) +static u8 get_bwcr_lbn(u64 val) { + WARN_ON_ONCE(SYS_DBGBCR_EL1_LBN_SHIFT != SYS_DBGWCR_EL1_LBN_SHIFT); + WARN_ON_ONCE(SYS_DBGBCR_EL1_LBN_MASK != SYS_DBGWCR_EL1_LBN_MASK); + return ((val >> SYS_DBGBCR_EL1_LBN_SHIFT) & SYS_DBGBCR_EL1_LBN_MASK); } -static u64 update_bcr_lbn(u64 val, u8 lbn) +static u64 update_bwcr_lbn(u64 val, u8 lbn) { u64 new; + WARN_ON_ONCE(SYS_DBGBCR_EL1_LBN_SHIFT != SYS_DBGWCR_EL1_LBN_SHIFT); + WARN_ON_ONCE(SYS_DBGBCR_EL1_LBN_MASK != SYS_DBGWCR_EL1_LBN_MASK); + new = val & ~(SYS_DBGBCR_EL1_LBN_MASK << SYS_DBGBCR_EL1_LBN_SHIFT); new |= ((u64)lbn & SYS_DBGBCR_EL1_LBN_MASK) << SYS_DBGBCR_EL1_LBN_SHIFT; return new; @@ -1029,29 +1037,51 @@ static u8 get_unused_p_bpn(struct kvm_vcpu *vcpu) * context aware breakpoint. In such cases, KVM will return 0 to reads of * bcr.lbn, and have the breakpoint behaves as if it is disabled by * setting the lbn to unused (disabled) breakpoint. + * + * virt_to_phys_wcr()/phys_to_virt_wcr() does the same thing for wcr. */ -static u64 virt_to_phys_bcr(struct kvm_vcpu *vcpu, u64 v_bcr) +static u64 virt_to_phys_bwcr(struct kvm_vcpu *vcpu, u64 v_bwcr) { u8 v_lbn, p_lbn; - v_lbn = get_bcr_lbn(v_bcr); + v_lbn = get_bwcr_lbn(v_bwcr); p_lbn = virt_to_phys_bpn(vcpu, v_lbn); if (p_lbn == INVALID_BRPN) p_lbn = get_unused_p_bpn(vcpu); - return update_bcr_lbn(v_bcr, p_lbn); + return update_bwcr_lbn(v_bwcr, p_lbn); } -static u64 phys_to_virt_bcr(struct kvm_vcpu *vcpu, u64 p_bcr) +static u64 phys_to_virt_bwcr(struct kvm_vcpu *vcpu, u64 p_bwcr) { u8 v_lbn, p_lbn; - p_lbn = get_bcr_lbn(p_bcr); + p_lbn = get_bwcr_lbn(p_bwcr); v_lbn = phys_to_virt_bpn(vcpu, p_lbn); if (v_lbn == INVALID_BRPN) v_lbn = 0; - return update_bcr_lbn(p_bcr, v_lbn); + return update_bwcr_lbn(p_bwcr, v_lbn); +} + +static u64 virt_to_phys_bcr(struct kvm_vcpu *vcpu, u64 v_bcr) +{ + return virt_to_phys_bwcr(vcpu, v_bcr); +} + +static u64 virt_to_phys_wcr(struct kvm_vcpu *vcpu, u64 v_wcr) +{ + return virt_to_phys_bwcr(vcpu, v_wcr); +} + +static u64 phys_to_virt_bcr(struct kvm_vcpu *vcpu, u64 p_bcr) +{ + return phys_to_virt_bwcr(vcpu, p_bcr); +} + +static u64 phys_to_virt_wcr(struct kvm_vcpu *vcpu, u64 p_wcr) +{ + return phys_to_virt_bwcr(vcpu, p_wcr); } /* @@ -1116,6 +1146,12 @@ void kvm_vcpu_breakpoint_config(struct kvm_vcpu *vcpu) dbg->dbg_bcr[v] = 0; dbg->dbg_bvr[v] = 0; } + + /* + * There is no distinction between physical and virtual + * watchpoint numbers. So, the index stays the same. + */ + dbg->dbg_wcr[v] = virt_to_phys_wcr(vcpu, dbg->dbg_wcr[v]); } } @@ -1461,12 +1497,26 @@ static bool trap_wcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd) { - u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; + u8 wpn = rd->CRm; + u64 *dbg_reg; + u64 v_dfr0 = read_id_reg_with_encoding(vcpu, SYS_ID_AA64DFR0_EL1); - if (p->is_write) + if (wpn > AA64DFR0_WRPS(v_dfr0)) { + /* Invalid watchpoint number for the guest */ + kvm_inject_undefined(vcpu); + return false; + } + + dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[wpn]; + if (p->is_write) { + /* Convert virtual wcr to physical wcr and update debug_reg */ + p->regval = virt_to_phys_wcr(vcpu, p->regval); reg_to_dbg(vcpu, p, rd, dbg_reg); - else + } else { dbg_to_reg(vcpu, p, rd, dbg_reg); + /* Convert physical wcr to virtual wcr */ + p->regval = phys_to_virt_wcr(vcpu, p->regval); + } trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); @@ -1476,19 +1526,49 @@ static bool trap_wcr(struct kvm_vcpu *vcpu, static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr) { - __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; + u8 wpn = rd->CRm; + u64 v_wcr, p_wcr; - if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) + if (copy_from_user(&v_wcr, uaddr, KVM_REG_SIZE(reg->id)) != 0) return -EFAULT; + + /* + * Until the first KVM_RUN, vcpu_debug_state holds the virtual wcr. + * After that, vcpu_debug_state holds the physical wcr. + */ + if (vcpu_has_run_once(vcpu)) { + /* Convert virtual wcr to physical wcr, and save it */ + p_wcr = virt_to_phys_wcr(vcpu, v_wcr); + vcpu->arch.vcpu_debug_state.dbg_wcr[wpn] = p_wcr; + } else { + vcpu->arch.vcpu_debug_state.dbg_wcr[wpn] = v_wcr; + return 0; + } + return 0; } static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr) { - __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm]; + u8 wpn = rd->CRm; + u64 p_wcr, v_wcr; - if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) + /* + * Until the first KVM_RUN, vcpu_debug_state holds the virtual wcr. + * After that, vcpu_debug_state holds the physical wcr. + */ + if (vcpu_has_run_once(vcpu)) { + /* Get the physical wcr value */ + p_wcr = vcpu->arch.vcpu_debug_state.dbg_wcr[wpn]; + + /* Convert physical wcr to virtual wcr */ + v_wcr = phys_to_virt_wcr(vcpu, p_wcr); + } else { + v_wcr = vcpu->arch.vcpu_debug_state.dbg_wcr[wpn]; + } + + if (copy_to_user(uaddr, &v_wcr, KVM_REG_SIZE(reg->id)) != 0) return -EFAULT; return 0; } From patchwork Tue Apr 19 06:55:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D97CBC433F5 for ; Tue, 19 Apr 2022 07:04:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=mh4SPjDfREAbYgKkyg+urQTSuWvtF3wv3ZtQozom9og=; b=4hMCLfylMln1sGPUdX+yR3ReS5 Njh8RLw/bv4RqRIjkURhn9kp9WGqlwSYyKFGW/7b4oZODHbHHU7X/3GnCXNWiGvUb8PrLQrYOe5xJ uKybELisVoys6uQ3iY0wiUgN4XISDt2M1SFIN0r8bm8DyaySg5r7TiBaPEzaMbJ1HrkklSbBdBZ8+ MDMyeEOq/6QFD4H/yfEw0o10UIJLgHrVILOpACOTVpw2FYNgX3dP+j4zxQvbfltZxhK/5HgGJL6Hw QIkr+YllQfFZNRsE5LFvyU3RNGIF/9BOSTATiSg3kloVVUx53OQTXLoM8gJg+qMuJ/MkYQGnBW0WE bMM77sjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghtS-001psF-IE; Tue, 19 Apr 2022 07:03:23 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnn-001nVm-Jy for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:33 +0000 Received: by mail-pl1-x649.google.com with SMTP id n2-20020a170903404200b00158db7879ddso5461887pla.13 for ; Mon, 18 Apr 2022 23:57:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=YXalEvL5V6OCiUslrdBdC3x5nYT2WOf4a/IV/CCw06k=; b=PBolxCNPqF/rYwCSGkME7PiAyjXXHuCvjT0iZNEZCb4UsNO/plPhzccwgGr3BMSa8c qYIv3k9YmvEm0jnHH8aOEfDd+Jz3wW8Pal3dbZm9Zr89ptohuxfunoyyo690KChdXylr BAnxcpKTeQqbIxZeQsKehjYF/qG93pGRQEtb3wEri0PgRyej+PlRhFlyhZhU1VMM25FG 2XNAvsn6BDxTp6+Ol1AO6/cMdXZMNHkoiHvX1S+zju41nFgQs7zJ6P+1qxSqqFMeeyPb 8wU07LHBjIKEM+a0DsU8p638g7ca57j5iBENAizVjw6KVT8brSDjAjq4sQnRneTW4F9r LlRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=YXalEvL5V6OCiUslrdBdC3x5nYT2WOf4a/IV/CCw06k=; b=QZu/b734lzLyRcWCfnOo/dapp3HgaM/mfoyohzkfT+EyRomJkCWj0bTWBeh6bF1dyE B8sMcK43iYk2HA3oJmmW6Ofz9L+SH0sRi+FBuayV17GtTOfd5Ud1V77E8IGBKhiQo/tW vzjDsc0bKek2oWLzui/1pSH1nVlhgvHvhbRj5alHJpB4SQonwmjdVUZxO3AJ8VUj7t8O hAP6fNaMOHRHdqk6t/4TYbeyJsoKEctMezkS2Jhnvf/a0j+mh9/t5iPbYFzMcZZTKQQn fAwjBbL8m3LpNohc2OZWerFwYIniuKO8je9nZnA5VafnvYjiLgeQ3HJSjSPfMG+D4eL/ Pq7Q== X-Gm-Message-State: AOAM532mVjurWH4voT+KtiXLKlvCCsu7+0HLbN21WD/3JU9GAEjMk/7W wjP8qY84EYrwgJx+vBcVdf1fJP7CTHs= X-Google-Smtp-Source: ABdhPJwNeyv4uuU7jneD4R263Q3CDhNQoNxJyLlw5PFrvBvjhbMrkb5ffdVyboN5y95J7aLLHm8T4JnHZ9A= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:1f0b:b0:50a:8181:fecb with SMTP id be11-20020a056a001f0b00b0050a8181fecbmr6190053pfb.12.1650351450390; Mon, 18 Apr 2022 23:57:30 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:21 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-16-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 15/38] KVM: arm64: Make ID_AA64DFR0_EL1/ID_DFR0_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235731_747946_09C9A53C X-CRM114-Status: GOOD ( 23.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_AA64DFR0_EL1 and ID_DFR0_EL1 to make them writable by userspace. Return an error if userspace tries to set PMUVER/PerfMon field of ID_AA64DFR0_EL1/ID_DFR0_EL1 to a value that conflicts with the PMU configuration. When a value of ID_AA64DFR0_EL1.PMUVER or ID_DFR0_EL1.PERFMON on the host is 0xf, which means IMPLEMENTATION DEFINED PMU supported, KVM erroneously expose the value for the guest as it is even though KVM doesn't support it for the guest. In that case, since KVM should expose 0x0 (PMU is not implemented), change the initial value of ID_AA64DFR0_EL1.PMUVER and ID_DFR0_EL1.PERFMON for the guest to 0x0. If userspace requests KVM to set them to 0xf, which shouldn't be allowed as KVM doesn't support IMPLEMENTATION DEFINED PMU for the guest, ignore the request (set the fields to 0x0 instead) so that a live migration from the older kernel works fine. Since number of context-aware breakpoints must be no more than number of supported breakpoints according to Arm ARM, return an error if userspace tries to set CTX_CMPS field to such value. Fixes: 8e35aa642ee4 ("arm64: cpufeature: Extract capped perfmon fields") Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/cpufeature.h | 2 +- arch/arm64/kvm/sys_regs.c | 164 ++++++++++++++++++++++++---- 2 files changed, 143 insertions(+), 23 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 7a009d4e18a6..7ed2d32b3854 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -554,7 +554,7 @@ cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap) /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */ if (val == ID_AA64DFR0_PMUVER_IMP_DEF) - val = 0; + return (features & ~mask); if (val > cap) { features &= ~mask; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 400fa7ff582f..9eca085886f5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -654,6 +654,75 @@ static int validate_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + unsigned int brps, ctx_cmps; + u64 pmu, lim_pmu; + u64 lim = id_reg->vcpu_limit_val; + + brps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_BRPS_SHIFT); + ctx_cmps = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_CTX_CMPS_SHIFT); + + /* + * Number of context-aware breakpoints can be no more than number of + * supported breakpoints. + */ + if (ctx_cmps > brps) + return -EINVAL; + + /* + * KVM will not set PMUVER to 0xf (IMPLEMENTATION DEFINED PMU) + * for the guest because KVM doesn't support it. + * If userspace requests KVM to set the field to 0xf, KVM will treat + * that as 0 instead of returning an error since userspace might do + * that when the guest is migrated from a host with older KVM, + * which sets the field to 0xf when the host value is 0xf. + */ + pmu = cpuid_feature_extract_unsigned_field(val, ID_AA64DFR0_PMUVER_SHIFT); + pmu = (pmu == 0xf) ? 0 : pmu; + lim_pmu = cpuid_feature_extract_unsigned_field(lim, ID_AA64DFR0_PMUVER_SHIFT); + if (pmu > lim_pmu) + return -E2BIG; + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ + if (kvm_vcpu_has_pmu(vcpu) ^ (pmu >= ID_AA64DFR0_PMUVER_8_0)) + return -EPERM; + + return 0; +} + +static int validate_id_dfr0_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + u64 pmon, lim_pmon; + u64 lim = id_reg->vcpu_limit_val; + + /* + * KVM will not set PERFMON to 0xf (IMPLEMENTATION DEFINED PERFMON) + * for the guest because KVM doesn't support it. + * If userspace requests KVM to set the field to 0xf, KVM will treat + * that as 0 instead of returning an error since userspace might do + * that when the guest is migrated from a host with older KVM, + * which sets the field to 0xf when the host value is 0xf. + */ + pmon = cpuid_feature_extract_unsigned_field(val, ID_DFR0_PERFMON_SHIFT); + pmon = (pmon == 0xf) ? 0 : pmon; + lim_pmon = cpuid_feature_extract_unsigned_field(lim, ID_DFR0_PERFMON_SHIFT); + if (pmon > lim_pmon) + return -E2BIG; + + if (pmon == 1 || pmon == 2) + /* PMUv1 or PMUv2 is not allowed on ARMv8. */ + return -EINVAL; + + /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */ + if (kvm_vcpu_has_pmu(vcpu) ^ (pmon >= ID_DFR0_PERFMON_8_0)) + return -EPERM; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -703,6 +772,31 @@ static void init_id_aa64isar2_el1_desc(struct id_reg_desc *id_reg) id_reg->vcpu_limit_val &= ~ISAR2_PTRAUTH_MASK; } +static void init_id_aa64dfr0_el1_desc(struct id_reg_desc *id_reg) +{ + u64 limit = id_reg->vcpu_limit_val; + + /* Limit guests to PMUv3 for ARMv8.4 */ + limit = cpuid_feature_cap_perfmon_field(limit, ID_AA64DFR0_PMUVER_SHIFT, + ID_AA64DFR0_PMUVER_8_4); + /* Limit debug to ARMv8.0 */ + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); + limit |= (FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6)); + + /* Hide SPE from guests */ + limit &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); + + id_reg->vcpu_limit_val = limit; +} + +static void init_id_dfr0_el1_desc(struct id_reg_desc *id_reg) +{ + /* Limit guests to PMUv3 for ARMv8.4 */ + id_reg->vcpu_limit_val = + cpuid_feature_cap_perfmon_field(id_reg->vcpu_limit_val, + ID_DFR0_PERFMON_SHIFT, + ID_DFR0_PERFMON_8_4); +} static u64 vcpu_mask_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, const struct id_reg_desc *idr) @@ -729,6 +823,18 @@ static u64 vcpu_mask_id_aa64isar2_el1(const struct kvm_vcpu *vcpu, } +static u64 vcpu_mask_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *idr) +{ + return kvm_vcpu_has_pmu(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER); +} + +static u64 vcpu_mask_id_dfr0_el1(const struct kvm_vcpu *vcpu, + const struct id_reg_desc *idr) +{ + return kvm_vcpu_has_pmu(vcpu) ? 0 : ARM64_FEATURE_MASK(ID_DFR0_PERFMON); +} + static int validate_id_reg(struct kvm_vcpu *vcpu, const struct id_reg_desc *id_reg, u64 val) { @@ -2186,28 +2292,9 @@ static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) const struct id_reg_desc *id_reg = get_id_reg_desc(id); if (id_reg) - return __read_id_reg(vcpu, id_reg); - - val = read_kvm_id_reg(vcpu->kvm, id); - switch (id) { - case SYS_ID_AA64DFR0_EL1: - /* Limit debug to ARMv8.0 */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER); - val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6); - /* Limit guests to PMUv3 for ARMv8.4 */ - val = cpuid_feature_cap_perfmon_field(val, - ID_AA64DFR0_PMUVER_SHIFT, - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); - /* Hide SPE from guests */ - val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER); - break; - case SYS_ID_DFR0_EL1: - /* Limit guests to PMUv3 for ARMv8.4 */ - val = cpuid_feature_cap_perfmon_field(val, - ID_DFR0_PERFMON_SHIFT, - kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); - break; - } + val = __read_id_reg(vcpu, id_reg); + else + val = read_kvm_id_reg(vcpu->kvm, id); return val; } @@ -4028,15 +4115,48 @@ static struct id_reg_desc id_aa64mmfr0_el1_desc = { }, }; +static struct id_reg_desc id_aa64dfr0_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64DFR0_EL1), + /* + * PMUVER doesn't follow the ID scheme for fields in ID registers. + * So, it will be validated by validate_id_aa64dfr0_el1. + */ + .ignore_mask = ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER), + .init = init_id_aa64dfr0_el1_desc, + .validate = validate_id_aa64dfr0_el1, + .vcpu_mask = vcpu_mask_id_aa64dfr0_el1, + .ftr_bits = { + S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 0xf), + }, +}; + +static struct id_reg_desc id_dfr0_el1_desc = { + .reg_desc = ID_SANITISED(ID_DFR0_EL1), + /* + * PERFMON doesn't follow the ID scheme for fields in ID registers. + * So, it will be validated by validate_id_dfr0_el1. + */ + .ignore_mask = ARM64_FEATURE_MASK(ID_DFR0_PERFMON), + .init = init_id_dfr0_el1_desc, + .validate = validate_id_dfr0_el1, + .vcpu_mask = vcpu_mask_id_dfr0_el1, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) /* A table for ID registers's information. */ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { + /* CRm=1 */ + ID_DESC(ID_DFR0_EL1, &id_dfr0_el1_desc), + /* CRm=4 */ ID_DESC(ID_AA64PFR0_EL1, &id_aa64pfr0_el1_desc), ID_DESC(ID_AA64PFR1_EL1, &id_aa64pfr1_el1_desc), + /* CRm=5 */ + ID_DESC(ID_AA64DFR0_EL1, &id_aa64dfr0_el1_desc), + /* CRm=6 */ ID_DESC(ID_AA64ISAR0_EL1, &id_aa64isar0_el1_desc), ID_DESC(ID_AA64ISAR1_EL1, &id_aa64isar1_el1_desc), From patchwork Tue Apr 19 06:55:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECF74C433EF for ; Tue, 19 Apr 2022 07:05:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=V5wfjQgYIHuj7SIOBS4Q3UcvMHSL5p4DVBZEHMoE5uc=; b=zkuBvHrMTbvXVMiWOrxdcRM3pM 8PD8YDfp4y23raWMbSwQ4zjcR1eP+Bo9Jtv3tNNczgivj9oIE8W9iEZSlKhLyIdWrFFdSdJHjUdyR vQ7m/B04DMtMCCdhYz/fvjc3o2Zng9ok98YgKGTJKWFt/6RTQ1lTc9D6iwxP2lUYaUeH1NLRnGIHL poGoWs/RYkO7D0/nrMl+krM3cemCXHi1P/uhYXytWBQUJYwIpKVYQyWIvfLM46I8IvT/Pcpm7PR07 5FaUmaMA4r2kAKPjHezcXuiGGZGQ7COzW/wmJDBC2V7wzUsm6XwDdnLv4gQTPARhGHeDJ06rYdXdr KIX+y6xA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghu0-001q7k-Pi; Tue, 19 Apr 2022 07:03:57 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnp-001nWe-DI for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:35 +0000 Received: by mail-pl1-x649.google.com with SMTP id ij17-20020a170902ab5100b00158f6f83068so3269191plb.19 for ; Mon, 18 Apr 2022 23:57:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=+RIFV+GBe2M89AsHlXZMsb8M9PH2fcdCA31lX27Exl0=; b=jHfDWDQBRdFMX1KUZ7M8h7PpM144EBI9vT9022UC7DTugoUZgKVXh5XxcMJR3sxN70 aoQkPuceSyyGP29G1menl9lnaI1m0kUA+fvRB7mzGNAWeYz5l/fUgvMoob1N9gab1My7 UWCic2ZNLYXUgeFFIn4H97XVTt+viw27rpDxXWVHJgA1B6p2CmVNcKJ6TLveWXxE/xQk ydfiv5X53K1FVVmXor1T/C4gL3g0lIyJ9MLApM8nzmMIH6pNamH5H0+iUvJ4kqd03eXW b47bh5b8cCNcl9sSjgo+NkhW9d2Yibv3AQ7C9gI5XGp8J4zhObzXeuECjtA3WNtmsgOr Pefg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=+RIFV+GBe2M89AsHlXZMsb8M9PH2fcdCA31lX27Exl0=; b=hRkf4qWtnx2+CfGCBupgtHJL3D+MHG7GLpKOWY5wnrrORUK90ZYTnS6W1uLHQ/UW4S 42rS3cRD2jg7xye/8W+s7hiS0Tv6rr3oj2f7BuMu+oAwbAZl80lg9ha/mwxMNahnbzuf c3BsMCCw64jSAxkeoy1tsxwm9y/eWQ6TOpfaZPozUANiMjgfeFYPp0OEfD+XahYrawbi Pt/QxX422Z3EctKQ8s/nVyvsYkb90ojEucsppE3Ivcr+BjzexIJqZ3k8cuPpb5MRNw+m TYsnHYua+Y05guwaaS1JRI4CfIEcFyEfab/xJ4dU+nTQGSgIpNHCYfP74R/KzrMAPTFP Y4fA== X-Gm-Message-State: AOAM530oC2x61OtU1z4SYvzjld3cU0YsjAL7ALw4Ih/8wW7h/EyVMxr9 gr16ZjRcPBPiOdAyq9nUC6NijioA3vA= X-Google-Smtp-Source: ABdhPJxyzd0FpvVmJHlsUoLjVst/BJV+186a7Jt7JsU7eedDcva2Fw/AIAC6p8ib5uPpHPfQ2iIiPlO8PG0= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:234f:b0:4f6:f0c0:ec68 with SMTP id j15-20020a056a00234f00b004f6f0c0ec68mr16406433pfj.14.1650351451950; Mon, 18 Apr 2022 23:57:31 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:22 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-17-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 16/38] KVM: arm64: KVM: arm64: Make ID_DFR1_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235733_515949_34E462B2 X-CRM114-Status: GOOD ( 10.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_DFR1_EL1 to make it writable by userspace. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9eca085886f5..3892278deb09 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4142,6 +4142,13 @@ static struct id_reg_desc id_dfr0_el1_desc = { .vcpu_mask = vcpu_mask_id_dfr0_el1, }; +static struct id_reg_desc id_dfr1_el1_desc = { + .reg_desc = ID_SANITISED(ID_DFR1_EL1), + .ftr_bits = { + S_FTR_BITS(FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 0xf), + }, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -4150,6 +4157,9 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=1 */ ID_DESC(ID_DFR0_EL1, &id_dfr0_el1_desc), + /* CRm=3 */ + ID_DESC(ID_DFR1_EL1, &id_dfr1_el1_desc), + /* CRm=4 */ ID_DESC(ID_AA64PFR0_EL1, &id_aa64pfr0_el1_desc), ID_DESC(ID_AA64PFR1_EL1, &id_aa64pfr1_el1_desc), From patchwork Tue Apr 19 06:55:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817516 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E00ADC433F5 for ; Tue, 19 Apr 2022 07:06:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=yNtlZ+YfJogrYvm8sv4LXSdD7Z5knrCC4TUoVgypoZE=; b=P0PTXqw0pkdaUeW/hudFp9FoJ8 IvM9iUWm3hhD6CBeKjX5VDU2JVOIOXCTknySdF19zAiLm5W60dPtERwQWZymrkYxNAoDlFajqINl9 GAyjDISXFvyowGBO+a1qiCOJm6Hn/2yrjyKa1exhcRsZoohfl+yU4WdzGQvqkiwp6FnJ36fLV+Y7R QpLfW9UeVKRE6V+l8PwcNhQgMi1UJg+RpZkrfapQMcem5E/YyjTqQZ6EMyFSYs0sDOea7HiK57XNB AJTYO2iStoG2uzMg4VM/gRY6B6b0n4AKoVDOEe2/2VIyp+oZl7D+dWvCJjpmqAwoHseF4PeWVCK6V zft4iw0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghv5-001qZU-46; Tue, 19 Apr 2022 07:05:05 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnq-001nXf-S5 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:36 +0000 Received: by mail-pj1-x104a.google.com with SMTP id r12-20020a17090a690c00b001cb9bce2284so10127939pjj.8 for ; Mon, 18 Apr 2022 23:57:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=kOtruObnAwr73tGi5MZAsEqpA/uKhtQAPuGoRa00WMc=; b=mTJ21013PiSwkw5o3Gbtoin1gGUFTC2f11xhWGdUiETUkhecccbVgbMOAwtXaKBtqw 34ltnUdfLnvlsCBfBtytLBYdcq3Iprqi6xqpEewEB0sE+o7KVrPiafcRnuf2v6WzOaVz PEWZt6iQR+LcBRGuArYRWNqjokJGWZTYDaUxQIXIY/pYCFOQmIuyIaTXxmw/sbJbbr1C yyBD3zGKzxr9xv8DPDiQ998Qbyf/SibU/rYcpFowvPKU2y/xz0ceqb+fEZe2ToqdztS9 zbY7kgN2a91vAerHogjHLztkGGHsfqbki1OYpRjBk4DLs/AKRYh2bDlAC/YTvmeNZDxM WRYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=kOtruObnAwr73tGi5MZAsEqpA/uKhtQAPuGoRa00WMc=; b=vcxKqMnjYEvqwqZ75kOvXo3DHiJGs/1hZh3DcmRs3nx76RSr31P+RMX16u/o2KziPA K8rQZNjXIuO/Z8loh7ArB1LB65qgXwvgdetE6Z62zCsBq1ovgmRJ5STMMraHRPQIpR+6 Vl9NTxVkEpDygjggk3B5hpoNNfxBTQh1mQNsSwCdb1NF3dz4i2YSYQIepDDDdOH5qWRH +QeOJqF3jV/sSOLdigsT7LAd0vbNOiLC/39yJ2eARw5PcoAi7ZqyJqk8fTpJW6Z/PUJa HAvwVVYcvWjNgsIZHHcBPCKQG5kdZ4OY6GUR5FgKm1L0Xk1vAKSa+tEmPafqkRtJOLsq CxHg== X-Gm-Message-State: AOAM531ZX+a8lUeIIiDsMfzshDIu0mi7nn07R5lNg/Gn0tjnZRTz16vW SYSYOWnO/uRZjcpS37M/PZoe57atFOU= X-Google-Smtp-Source: ABdhPJx6qDbSnrgYvhJroWf4jBAE01A6EcpohDsqf8ebCgDlStR+vqVIies+oFNL6BLxOeYZEqyR+y7SKVI= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90b:2384:b0:1cb:5223:9dc4 with SMTP id mr4-20020a17090b238400b001cb52239dc4mr276854pjb.1.1650351453576; Mon, 18 Apr 2022 23:57:33 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:23 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-18-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 17/38] KVM: arm64: KVM: arm64: Make ID_MMFR0_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235734_980748_5707E37A X-CRM114-Status: GOOD ( 10.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for ID_MMFR0_EL1 to make it writable by userspace. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3892278deb09..dfcf95eee139 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4149,6 +4149,14 @@ static struct id_reg_desc id_dfr1_el1_desc = { }, }; +static struct id_reg_desc id_mmfr0_el1_desc = { + .reg_desc = ID_SANITISED(ID_MMFR0_EL1), + .ftr_bits = { + S_FTR_BITS(FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 0xf), + S_FTR_BITS(FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 0xf), + }, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -4156,6 +4164,7 @@ static struct id_reg_desc id_dfr1_el1_desc = { static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=1 */ ID_DESC(ID_DFR0_EL1, &id_dfr0_el1_desc), + ID_DESC(ID_MMFR0_EL1, &id_mmfr0_el1_desc), /* CRm=3 */ ID_DESC(ID_DFR1_EL1, &id_dfr1_el1_desc), From patchwork Tue Apr 19 06:55:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 027ECC433EF for ; Tue, 19 Apr 2022 07:08:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=nhXNuWMPWzAJeiIOvFN317TBluou7LRQyzhh5CYjOXs=; b=3MtYxJDOipedZw4DBIeuG6robr tlk10qgfWc6jMHyOOv6s2HomLz7/nEMsLa7KnSPwwda1M3qOz2Tae5GEd1awU+cUzCtHgQrVBqK8x sKj7KZCTHeVvwaAAV4hra/tIGM/sfoi5EQW3oiBw8FvuOzNTc1pMBx2pJYg7KVRaQRAhsH2I1B3Td +xbadctsRfQ3T3YUam1b6o1F6E70Y6SYxUVMuO2vuj1pZxzrSpNjigh9v8QtOltzgZ/iStieh68Qp nhCDmso0r+cQu4HsS9rW6f00oTFCKQi91vFVk775swzYrCicm5v+NIw9bSUS4NTp2E/AbbSCx5yEY YUWO0xCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghwq-001rG2-7P; Tue, 19 Apr 2022 07:06:52 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghns-001nYi-JC for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:38 +0000 Received: by mail-pl1-x649.google.com with SMTP id w14-20020a1709027b8e00b0015386056d2bso9264339pll.5 for ; Mon, 18 Apr 2022 23:57:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=k1aHxZoAaiwp9IBNDG6Sd3gJpxfpCorD51sV50ZX1Is=; b=Jli11xd8mqtWlIpeSa3R9uzukrE3588Wd4QhntxW82Bu/d8zHdDqy5Vnvhjai2huOG ctO1oRjeEaWQimFertWBqamfLaap9CKRToZztNwFW6AE5f77/xW9p6paFim7Eh7qvzSO ebE76Z2+yGh8wGatmYbFF/t13Q+dURYNiYoKJpRw2q7/OEK020kfrOfRxaTFtD8m1pBL ktAWStxHUd0QTBBINHesSzJ4IiTrb13R5/APAq0j6EGDHxYbYy5APaRw13Y0xyseo7hY rD7XzK+d9NrLLA43JNxU1nQ1vNk3faa9dqHy9TI1prJnH+RtsxwhlLg2kiKVaTaiNKH/ mlng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=k1aHxZoAaiwp9IBNDG6Sd3gJpxfpCorD51sV50ZX1Is=; b=WTkyQLBcggn/1X2ORUrGLpLAQyGCM5K8TjNIMTxrYERb7Spe1SLZpfawvHhrXH8D7j Z2oWkilGLTaSCIIscetrIlRwp2PZzMw91roKt7WRMoFuK23ft22F6TkZ5797nyceeJi7 XJZEriEF+8xmGc8es05WZ/SqW4qDH29GnckO14djxGhgAHnpl/gXaLA+JnEsfxm0M+Rn f+lM079NDevGrTmZZnDa4WJHwK793W1ecmwbGYK8SIMGk31Fhin5Y99uYzRhCZn/ws1I 0axYAypQhLldp0Q3gFR3DYcDiLnONP0wOpwDl6su+TVvYv4fR7FkyPAIU9XWsXvXgGiB psBA== X-Gm-Message-State: AOAM533kd2lPoq7OPpwOJjUoAP/xtybMiSBXrX6eL0lz/iP2fa4nUsVa ToLbIgFLo0N2fPTzQ+HIDHTHOKR/33Y= X-Google-Smtp-Source: ABdhPJw4BjqWGKNFLnPZMZUC1+9yLnqihHWKtPmY8zD8R5Ja1UK3sVAaay5AnyQvY9iXieVJivmijHyA5sg= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:2349:b0:4fa:934f:f6db with SMTP id j9-20020a056a00234900b004fa934ff6dbmr16170589pfj.44.1650351455448; Mon, 18 Apr 2022 23:57:35 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:24 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-19-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 18/38] KVM: arm64: Make MVFR1_EL1 writable From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235736_686925_2676D434 X-CRM114-Status: GOOD ( 16.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds id_reg_desc for MVFR1_EL1 to make it writable by userspace. There are only a few valid combinations of values that can be set for FPHP and SIMDHP fields according to Arm ARM. Return an error when userspace tries to set those fields to values that don't match any of the valid combinations. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index dfcf95eee139..9e090441057a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -723,6 +723,36 @@ static int validate_id_dfr0_el1(struct kvm_vcpu *vcpu, return 0; } +static int validate_mvfr1_el1(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg, u64 val) +{ + unsigned int fphp, simdhp; + struct fphp_simdhp { + unsigned int fphp; + unsigned int simdhp; + }; + /* Permitted fphp/simdhp value combinations according to Arm ARM */ + struct fphp_simdhp valid_fphp_simdhp[3] = {{0, 0}, {2, 1}, {3, 2}}; + int i; + bool is_valid_fphp_simdhp = false; + + fphp = cpuid_feature_extract_unsigned_field(val, MVFR1_FPHP_SHIFT); + simdhp = cpuid_feature_extract_unsigned_field(val, MVFR1_SIMDHP_SHIFT); + + for (i = 0; i < ARRAY_SIZE(valid_fphp_simdhp); i++) { + if (valid_fphp_simdhp[i].fphp == fphp && + valid_fphp_simdhp[i].simdhp == simdhp) { + is_valid_fphp_simdhp = true; + break; + } + } + + if (!is_valid_fphp_simdhp) + return -EINVAL; + + return 0; +} + static void init_id_aa64pfr0_el1_desc(struct id_reg_desc *id_reg) { u64 limit = id_reg->vcpu_limit_val; @@ -4157,6 +4187,11 @@ static struct id_reg_desc id_mmfr0_el1_desc = { }, }; +static struct id_reg_desc mvfr1_el1_desc = { + .reg_desc = ID_SANITISED(MVFR1_EL1), + .validate = validate_mvfr1_el1, +}; + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) @@ -4167,6 +4202,7 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { ID_DESC(ID_MMFR0_EL1, &id_mmfr0_el1_desc), /* CRm=3 */ + ID_DESC(MVFR1_EL1, &mvfr1_el1_desc), ID_DESC(ID_DFR1_EL1, &id_dfr1_el1_desc), /* CRm=4 */ From patchwork Tue Apr 19 06:55:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B1DDC433FE for ; Tue, 19 Apr 2022 07:08:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Do/07SQsq5WkVJCw1uHHyZgRmr0NLjjaRvbw3Xg9MKA=; b=udXpHMCjx/jGKxuankC6DOOiKR HQma155X4ZPyT/pYQ89Ic/xMUNnqiu04GmSSlkXhtuqmqZeVkOpuDH2kblfnb6I1wbtNIURfQpfEk nR2/g46X56snPUW4x3ZDTLvQehoEMujEvlp+EQZCOn0AqXaukFvoX7auozvWjNUJ9Tr75PJn6Aphv hp9YD5Xq9nUGfJDYPWksZ5bV0SU6WKh2I01vLWy6dVjGoHnTrjCsFMEtoIkwIqJwLSLaE23ZxrFxj N95qDma8aTsirP9tb4AocX5zi63WsFZgNQguvsorqSvDZRGpiUFbXYg63KxTuDbM6kp1aVnFYrgYm Ns+PgFfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghxf-001rXa-Qi; Tue, 19 Apr 2022 07:07:44 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnt-001nZJ-T3 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:39 +0000 Received: by mail-pj1-x104a.google.com with SMTP id b16-20020a17090ae39000b001ce8478ea2dso1210634pjz.0 for ; Mon, 18 Apr 2022 23:57:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=XAe9o8/7QtvwA7T4kzsz7p8aDgk6j+Di6GgUS4L29XQ=; b=bjp6ZxrGAh7052Gw6Xdmrg+7KZKA2uAnPjBgjXkIw2dFvt7G7LE/TTe8/W3Oj57ExI cZYBHWsYxkJIQ7lHFYgAKKcsok3iLVBUXssHXQQQ655fJ2DAs1rIPQ936ssjYaDW5leP 74OrsDeIahHKz5IKhc/qqk97SKOd4YF0gSsM2oRzjAKfleXT3nu/pB8ojlS0R+IA2MFb oN9GtMZPUdiMTKCBf2adntBJFKoPdzlR+R0bKWByFsr3b4kJw9P/zVfmY19IQAQJ+qut DV2weGfw90L/YB66aNJH8bfLF+/l6o4j7hpIPYdJMMBKUSgC5sOMHQ0BYi1Zjo5kIT7c BZrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=XAe9o8/7QtvwA7T4kzsz7p8aDgk6j+Di6GgUS4L29XQ=; b=aVt5cuCnx3ZRyw3D3RtQDx2MQz5OmPp8bMbqNK+aL6U4xHN1OFYOqIgN9+ezbQAVdY ujrNPGbgoIn13uAX6BbU7OYu2l2GEUtaBHrms09XhcCJGiIon+IAg4l2T5RKTdvyzu3S jGb++914/yh1D1J9esHFkD3dhbL2uAq2KFvyYx9p5VwZ+8JPWNnDut9EuSz7XaCNXyoy SnGARyRIh0wo/pzJ7PJtcLALlfJX5TUZoUlAG4Ir6tp34cYMoLT4khqfCz5U+cd3laYp FipQAu3TbvGqsAi5XDgYYRgUVxGPRDthYFJITBQ+sp9w8r/DNNZmKM7XCj8A8nFrODgR +1LQ== X-Gm-Message-State: AOAM533zEbw8U2RpUygSesswkTM9Pj7kuPixH+rJEsqd7riGywv2I+fK cIF3tvah9INgEH6aPNToNubxm968qN8= X-Google-Smtp-Source: ABdhPJxlcowD6T6yPgHuseBL0ofs+MsqwJykl/a/FrUlFopUkhnFg/TqdMwK8KVyg1eylJC4AC624op+zHg= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:b89:b0:505:dead:db1d with SMTP id g9-20020a056a000b8900b00505deaddb1dmr16566920pfj.74.1650351456883; Mon, 18 Apr 2022 23:57:36 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:25 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-20-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 19/38] KVM: arm64: Add remaining ID registers to id_reg_desc_table From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235738_005721_F40403AF X-CRM114-Status: GOOD ( 16.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add hidden or reserved ID registers, and remaining ID registers, which don't require special handling, to id_reg_desc_table. Add 'flags' field to id_reg_desc, which is used to indicates hiddden or reserved registers. Since now id_reg_desc_init() is called even for hidden/reserved registers, change it to not do anything for them. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 84 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9e090441057a..479208dedd79 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -331,6 +331,11 @@ struct id_reg_desc { /* Fields that are not validated by arm64_check_features. */ u64 ignore_mask; + /* Miscellaneous flags */ +#define ID_DESC_REG_UNALLOC (1UL << 0) +#define ID_DESC_REG_HIDDEN (1UL << 1) + u64 flags; + /* An optional initialization function of the id_reg_desc */ void (*init)(struct id_reg_desc *id_reg); @@ -376,8 +381,13 @@ struct id_reg_desc { static void id_reg_desc_init(struct id_reg_desc *id_reg) { u32 id = reg_to_encoding(&id_reg->reg_desc); - u64 val = read_sanitised_ftr_reg(id); + u64 val; + + if (id_reg->flags & (ID_DESC_REG_HIDDEN | ID_DESC_REG_UNALLOC)) + /* Nothing to do for a hidden/unalloc ID register */ + return; + val = read_sanitised_ftr_reg(id); id_reg->vcpu_limit_val = val; id_reg_desc_init_ftr(id_reg); @@ -4192,33 +4202,103 @@ static struct id_reg_desc mvfr1_el1_desc = { .validate = validate_mvfr1_el1, }; +#define ID_DESC_DEFAULT(name) \ + [IDREG_IDX(SYS_##name)] = &(struct id_reg_desc) { \ + .reg_desc = ID_SANITISED(name), \ + } + +#define ID_DESC_HIDDEN(name) \ + [IDREG_IDX(SYS_##name)] = &(struct id_reg_desc) { \ + .reg_desc = ID_HIDDEN(name), \ + .flags = ID_DESC_REG_HIDDEN, \ + } + +#define ID_DESC_UNALLOC(crm, op2) \ + [(crm - 1) << 3 | op2] = &(struct id_reg_desc) { \ + .reg_desc = ID_UNALLOCATED(crm, op2), \ + .flags = ID_DESC_REG_UNALLOC, \ + } + #define ID_DESC(id_reg_name, id_reg_desc) \ [IDREG_IDX(SYS_##id_reg_name)] = (id_reg_desc) -/* A table for ID registers's information. */ +/* + * A table for ID registers's information. + * All entries in the table except ID_DESC_HIDDEN and ID_DESC_UNALLOC + * must have corresponding entries in arm64_ftr_regs[] in + * arch/arm64/kernel/cpufeature.c because read_sanitised_ftr_reg() is + * called for each of the ID registers. + */ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=1 */ + ID_DESC_DEFAULT(ID_PFR0_EL1), + ID_DESC_DEFAULT(ID_PFR1_EL1), ID_DESC(ID_DFR0_EL1, &id_dfr0_el1_desc), + ID_DESC_HIDDEN(ID_AFR0_EL1), ID_DESC(ID_MMFR0_EL1, &id_mmfr0_el1_desc), + ID_DESC_DEFAULT(ID_MMFR1_EL1), + ID_DESC_DEFAULT(ID_MMFR2_EL1), + ID_DESC_DEFAULT(ID_MMFR3_EL1), + + /* CRm=2 */ + ID_DESC_DEFAULT(ID_ISAR0_EL1), + ID_DESC_DEFAULT(ID_ISAR1_EL1), + ID_DESC_DEFAULT(ID_ISAR2_EL1), + ID_DESC_DEFAULT(ID_ISAR3_EL1), + ID_DESC_DEFAULT(ID_ISAR4_EL1), + ID_DESC_DEFAULT(ID_ISAR5_EL1), + ID_DESC_DEFAULT(ID_MMFR4_EL1), + ID_DESC_DEFAULT(ID_ISAR6_EL1), /* CRm=3 */ + ID_DESC_DEFAULT(MVFR0_EL1), ID_DESC(MVFR1_EL1, &mvfr1_el1_desc), + ID_DESC_DEFAULT(MVFR2_EL1), + ID_DESC_UNALLOC(3, 3), + ID_DESC_DEFAULT(ID_PFR2_EL1), ID_DESC(ID_DFR1_EL1, &id_dfr1_el1_desc), + ID_DESC_DEFAULT(ID_MMFR5_EL1), + ID_DESC_UNALLOC(3, 7), /* CRm=4 */ ID_DESC(ID_AA64PFR0_EL1, &id_aa64pfr0_el1_desc), ID_DESC(ID_AA64PFR1_EL1, &id_aa64pfr1_el1_desc), + ID_DESC_UNALLOC(4, 2), + ID_DESC_UNALLOC(4, 3), + ID_DESC_DEFAULT(ID_AA64ZFR0_EL1), + ID_DESC_UNALLOC(4, 5), + ID_DESC_UNALLOC(4, 6), + ID_DESC_UNALLOC(4, 7), /* CRm=5 */ ID_DESC(ID_AA64DFR0_EL1, &id_aa64dfr0_el1_desc), + ID_DESC_DEFAULT(ID_AA64DFR1_EL1), + ID_DESC_UNALLOC(5, 2), + ID_DESC_UNALLOC(5, 3), + ID_DESC_HIDDEN(ID_AA64AFR0_EL1), + ID_DESC_HIDDEN(ID_AA64AFR1_EL1), + ID_DESC_UNALLOC(5, 6), + ID_DESC_UNALLOC(5, 7), /* CRm=6 */ ID_DESC(ID_AA64ISAR0_EL1, &id_aa64isar0_el1_desc), ID_DESC(ID_AA64ISAR1_EL1, &id_aa64isar1_el1_desc), ID_DESC(ID_AA64ISAR2_EL1, &id_aa64isar2_el1_desc), + ID_DESC_UNALLOC(6, 3), + ID_DESC_UNALLOC(6, 4), + ID_DESC_UNALLOC(6, 5), + ID_DESC_UNALLOC(6, 6), + ID_DESC_UNALLOC(6, 7), /* CRm=7 */ ID_DESC(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1_desc), + ID_DESC_DEFAULT(ID_AA64MMFR1_EL1), + ID_DESC_DEFAULT(ID_AA64MMFR2_EL1), + ID_DESC_UNALLOC(7, 3), + ID_DESC_UNALLOC(7, 4), + ID_DESC_UNALLOC(7, 5), + ID_DESC_UNALLOC(7, 6), + ID_DESC_UNALLOC(7, 7), }; static inline struct id_reg_desc *get_id_reg_desc(u32 id) From patchwork Tue Apr 19 06:55:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1AEFC433EF for ; Tue, 19 Apr 2022 07:10:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=1i3ADVSoTATWwX0v2orueOwef7mpbm5f0u3TYyv/ujM=; b=JtxSlnZ7sbrzmYlMlC/CZ39dQH wosOCa80Wr0kNUCncCevnwWUDwiy/MAccOtemLOQDTQOWuSl/Atbojf2MdqUEV1hG48c1KWz4w5hU m6RHMWF4zMHFzpWL8gpA+ic2C/rUYJ+p+viTZZOqaG6A3QGsNApSu72AO0E3WEyDuOnZ/ewvLotWF 0C+G1f7W/oevMcMCRCdHHtI3ar+mMcxuh4m2fMPRFKzdYvDyKDjtD0JAZvIXSevAKTXJz0nSq+VFL 2WYH0Vq5nsRHe8xhLceWp/Muup9OI9/UrkA7CCP/mctPGsKn4NuqfLrbE2GUZqAq1Z7MvXonmSujl udgDL1og==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghyw-001rzF-Eq; Tue, 19 Apr 2022 07:09:03 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnv-001naF-Ja for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:41 +0000 Received: by mail-pl1-x649.google.com with SMTP id n2-20020a170903404200b00158db7879ddso5462168pla.13 for ; Mon, 18 Apr 2022 23:57:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=BYNmDR5aS9CIHBUCE54KmU1zVcfj0hKEcHDhO14njTY=; b=Rd3OQG2adxkXSrgalrmYqwRA4enRlDXXdjPxUSYSaHT2dWBBuKK0E8aHDuS5ESL9J4 TZ3Bv1osyFcq4eHT6/SA9wrP1JaZOlZRVjcqTsS519xru7QsPiFkO0IC/zg0g/ZzNvho jS5ABHj/nGNsw6WrVJ/XsZH+eEKM2HIOKf2RadJ0gcol1Zb5LHKFhLZo5Z5Xvp/k24zn /NFSeOZNHGrXgif6ROqLJ1cOTAW+6AvHg2Yl5wKoBE08+VI8c4gLv5M0Zz8vYao9Mxuo W84IC3XbHXuUUxL4EBRv5ieXGWzNg3qOhwynA/6s8/XbHJ/REqwbsvo5SrqNVMjBlZeM TVug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=BYNmDR5aS9CIHBUCE54KmU1zVcfj0hKEcHDhO14njTY=; b=wVC3BMhA57ADvzOQgZ0KRZ1Sp/TR5SDHUmn3x/bhzMVNvaUTy3iqw8bWRYeAqMRrh5 KL4RxrY3/utaeGSLH/N81b26hd4u2FCVpek2WqKbM1/C5O8LHfdgEeHW6SR2xFbqaUbW CmfCkz6U32iwaTfg2lG6ZfhAPL+dt3dQI16yB5OT61LWUL/o6WDCmi+MW2RGV7aTKFeU mB2YMRVZSpkyLkcloJPhR/BzzMfQgGCpN940unO6j/sIKUrQ8QqP/4MkAtPAar+1BdN7 wo6iXHKuws39gG+IV1feCLoPhquGEc0XoM9gfp2c+fqUfOJMls71wpKJnyFkzxu4975w qGFg== X-Gm-Message-State: AOAM530nap6hCWnM8TM67uGNdvmmglvgmdZU0b3SejS7Va1wIYraEKn1 D8anwHxF5EH1kvtsI7jN9RmrAIrXm0E= X-Google-Smtp-Source: ABdhPJysSV5fT+ppkKeqH9Y96RbdCmh9YpcOlscu43gi8Doy318XckzFc1VUDrPpwtYz4XZP/kyrJhwVpoM= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a62:5343:0:b0:4f7:baad:5c22 with SMTP id h64-20020a625343000000b004f7baad5c22mr16124535pfb.30.1650351458319; Mon, 18 Apr 2022 23:57:38 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:26 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-21-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 20/38] KVM: arm64: Use id_reg_desc_table for ID registers From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235739_711588_8EF4276B X-CRM114-Status: GOOD ( 24.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use id_reg_desc_table for ID registers instead of sys_reg_descs as id_reg_desc_table has all ID register entries that sys_reg_descs has, and remove the ID register entries from sys_reg_descs, which are no longer used. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 213 ++++++++++++++++---------------------- 1 file changed, 92 insertions(+), 121 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 479208dedd79..1045319c474e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -378,6 +378,11 @@ struct id_reg_desc { struct arm64_ftr_bits ftr_bits[FTR_FIELDS_NUM]; }; +static inline struct id_reg_desc *sys_to_id_desc(const struct sys_reg_desc *r) +{ + return container_of(r, struct id_reg_desc, reg_desc); +} + static void id_reg_desc_init(struct id_reg_desc *id_reg) { u32 id = reg_to_encoding(&id_reg->reg_desc); @@ -2326,23 +2331,15 @@ static u64 __read_id_reg(const struct kvm_vcpu *vcpu, return val; } -static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 id) +static u64 read_id_reg_with_encoding(const struct kvm_vcpu *vcpu, u32 encoding) { - u64 val; - const struct id_reg_desc *id_reg = get_id_reg_desc(id); - - if (id_reg) - val = __read_id_reg(vcpu, id_reg); - else - val = read_kvm_id_reg(vcpu->kvm, id); - - return val; + return __read_id_reg(vcpu, get_id_reg_desc(encoding)); } static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r, bool raz) { - return raz ? 0 : read_id_reg_with_encoding(vcpu, reg_to_encoding(r)); + return raz ? 0 : __read_id_reg(vcpu, sys_to_id_desc(r)); } static unsigned int id_visibility(const struct kvm_vcpu *vcpu, @@ -2456,13 +2453,7 @@ static int __set_id_reg(struct kvm_vcpu *vcpu, if (test_bit(KVM_ARCH_FLAG_EL1_32BIT, &vcpu->kvm->arch.flags)) return -EPERM; - /* - * Don't allow to modify the register's value if the register doesn't - * have the id_reg_desc. - */ - id_reg = get_id_reg_desc(encoding); - if (!id_reg) - return -EINVAL; + id_reg = sys_to_id_desc(rd); /* * Skip the validation of AArch32 ID registers if the system doesn't @@ -2686,83 +2677,6 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, - /* - * ID regs: all ID_SANITISED() entries here must have corresponding - * entries in arm64_ftr_regs[]. - */ - - /* AArch64 mappings of the AArch32 ID registers */ - /* CRm=1 */ - ID_SANITISED(ID_PFR0_EL1), - ID_SANITISED(ID_PFR1_EL1), - ID_SANITISED(ID_DFR0_EL1), - ID_HIDDEN(ID_AFR0_EL1), - ID_SANITISED(ID_MMFR0_EL1), - ID_SANITISED(ID_MMFR1_EL1), - ID_SANITISED(ID_MMFR2_EL1), - ID_SANITISED(ID_MMFR3_EL1), - - /* CRm=2 */ - ID_SANITISED(ID_ISAR0_EL1), - ID_SANITISED(ID_ISAR1_EL1), - ID_SANITISED(ID_ISAR2_EL1), - ID_SANITISED(ID_ISAR3_EL1), - ID_SANITISED(ID_ISAR4_EL1), - ID_SANITISED(ID_ISAR5_EL1), - ID_SANITISED(ID_MMFR4_EL1), - ID_SANITISED(ID_ISAR6_EL1), - - /* CRm=3 */ - ID_SANITISED(MVFR0_EL1), - ID_SANITISED(MVFR1_EL1), - ID_SANITISED(MVFR2_EL1), - ID_UNALLOCATED(3,3), - ID_SANITISED(ID_PFR2_EL1), - ID_HIDDEN(ID_DFR1_EL1), - ID_SANITISED(ID_MMFR5_EL1), - ID_UNALLOCATED(3,7), - - /* AArch64 ID registers */ - /* CRm=4 */ - ID_SANITISED(ID_AA64PFR0_EL1), - ID_SANITISED(ID_AA64PFR1_EL1), - ID_UNALLOCATED(4,2), - ID_UNALLOCATED(4,3), - ID_SANITISED(ID_AA64ZFR0_EL1), - ID_UNALLOCATED(4,5), - ID_UNALLOCATED(4,6), - ID_UNALLOCATED(4,7), - - /* CRm=5 */ - ID_SANITISED(ID_AA64DFR0_EL1), - ID_SANITISED(ID_AA64DFR1_EL1), - ID_UNALLOCATED(5,2), - ID_UNALLOCATED(5,3), - ID_HIDDEN(ID_AA64AFR0_EL1), - ID_HIDDEN(ID_AA64AFR1_EL1), - ID_UNALLOCATED(5,6), - ID_UNALLOCATED(5,7), - - /* CRm=6 */ - ID_SANITISED(ID_AA64ISAR0_EL1), - ID_SANITISED(ID_AA64ISAR1_EL1), - ID_SANITISED(ID_AA64ISAR2_EL1), - ID_UNALLOCATED(6,3), - ID_UNALLOCATED(6,4), - ID_UNALLOCATED(6,5), - ID_UNALLOCATED(6,6), - ID_UNALLOCATED(6,7), - - /* CRm=7 */ - ID_SANITISED(ID_AA64MMFR0_EL1), - ID_SANITISED(ID_AA64MMFR1_EL1), - ID_SANITISED(ID_AA64MMFR2_EL1), - ID_UNALLOCATED(7,3), - ID_UNALLOCATED(7,4), - ID_UNALLOCATED(7,5), - ID_UNALLOCATED(7,6), - ID_UNALLOCATED(7,7), - { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, @@ -3577,12 +3491,38 @@ static bool is_imp_def_sys_reg(struct sys_reg_params *params) return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; } +static inline const struct sys_reg_desc * +find_id_reg(const struct sys_reg_params *params) +{ + u32 id = reg_to_encoding(params); + struct id_reg_desc *idr; + + if (!is_id_reg(id)) + return NULL; + + idr = get_id_reg_desc(id); + + return idr ? &idr->reg_desc : NULL; +} + +static const struct sys_reg_desc * +find_sys_reg(const struct sys_reg_params *params) +{ + const struct sys_reg_desc *r = NULL; + + r = find_id_reg(params); + if (!r) + r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); + + return r; +} + static int emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params) { const struct sys_reg_desc *r; - r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); + r = find_sys_reg(params); if (likely(r)) { perform_access(vcpu, params, r); @@ -3597,6 +3537,8 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu, return 1; } +static void kvm_reset_id_regs(struct kvm_vcpu *vcpu); + /** * kvm_reset_sys_regs - sets system registers to reset value * @vcpu: The VCPU pointer @@ -3611,6 +3553,8 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) if (sys_reg_descs[i].reset) sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); + + kvm_reset_id_regs(vcpu); } /** @@ -3694,7 +3638,7 @@ static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, if (!index_to_params(id, ¶ms)) return NULL; - r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); + r = find_sys_reg(¶ms); /* Not saved in the sys_reg array and not otherwise accessible? */ if (r && !(r->reg || r->get_user)) @@ -3991,6 +3935,8 @@ static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, return 0; } +static int walk_id_regs(struct kvm_vcpu *vcpu, u64 __user *uind); + /* Assumed ordered tables, see kvm_sys_reg_table_init. */ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) { @@ -4006,6 +3952,12 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) if (err) return err; } + + err = walk_id_regs(vcpu, uind); + if (err < 0) + return err; + + total += err; return total; } @@ -4306,6 +4258,25 @@ static inline struct id_reg_desc *get_id_reg_desc(u32 id) return id_reg_desc_table[IDREG_IDX(id)]; } +static int walk_id_regs(struct kvm_vcpu *vcpu, u64 __user *uind) +{ + const struct sys_reg_desc *sys_reg; + int err, i; + unsigned int total = 0; + + for (i = 0; i < ARRAY_SIZE(id_reg_desc_table); i++) { + if (!id_reg_desc_table[i]) + continue; + + sys_reg = &id_reg_desc_table[i]->reg_desc; + err = walk_one_sys_reg(vcpu, sys_reg, &uind, &total); + if (err) + return err; + } + + return total; +} + void kvm_ftr_bits_set_default(u8 shift, struct arm64_ftr_bits *ftrp) { ftrp->sign = FTR_UNSIGNED; @@ -4376,35 +4347,35 @@ void set_default_id_regs(struct kvm *kvm) { int i; u32 id; - const struct sys_reg_desc *rd; - u64 val; struct id_reg_desc *idr; - struct sys_reg_params params = { - Op0(sys_reg_Op0(SYS_ID_PFR0_EL1)), - Op1(sys_reg_Op1(SYS_ID_PFR0_EL1)), - CRn(sys_reg_CRn(SYS_ID_PFR0_EL1)), - CRm(sys_reg_CRm(SYS_ID_PFR0_EL1)), - Op2(sys_reg_Op2(SYS_ID_PFR0_EL1)), - }; - /* - * Find the first entry of the ID register (ID_PFR0_EL1) from - * sys_reg_descs table, and walk through only the ID register - * entries in the table. - */ - rd = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); - for (i = 0; i < KVM_ARM_ID_REG_MAX_NUM; i++, rd++) { - id = reg_to_encoding(rd); - if (WARN_ON_ONCE(!is_id_reg(id))) - /* Shouldn't happen */ + for (i = 0; i < ARRAY_SIZE(id_reg_desc_table); i++) { + idr = id_reg_desc_table[i]; + if (!idr) continue; - if (rd->access != access_id_reg) - /* Hidden or reserved ID register */ + if (idr->flags & (ID_DESC_REG_HIDDEN | ID_DESC_REG_UNALLOC)) + /* Nothing to do for hidden/unalloc registers */ + continue; + + id = reg_to_encoding(&idr->reg_desc); + WARN_ON_ONCE(write_kvm_id_reg(kvm, id, idr->vcpu_limit_val)); + } +} + +static void kvm_reset_id_regs(struct kvm_vcpu *vcpu) +{ + int i; + const struct sys_reg_desc *r; + struct id_reg_desc *id_reg; + + for (i = 0; i < ARRAY_SIZE(id_reg_desc_table); i++) { + id_reg = (struct id_reg_desc *)id_reg_desc_table[i]; + if (!id_reg) continue; - idr = get_id_reg_desc(id); - val = idr ? idr->vcpu_limit_val : read_sanitised_ftr_reg(id); - WARN_ON_ONCE(write_kvm_id_reg(kvm, id, val)); + r = &id_reg->reg_desc; + if (r->reset) + r->reset(vcpu, r); } } From patchwork Tue Apr 19 06:55:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 013BEC433FE for ; Tue, 19 Apr 2022 07:11:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=7p3pWc/qpZNnbSttpFZnZPkwmQZ4xC5UZdmSGLVEV0Q=; b=QLAO7uYY1YQHvu1M8TqSdN7JvD 9sfcsl2Sla+pTUMX5Dywrc2XerBUy8IIuqtfcPArEz8TrjUvkewxR/iRelI72CQlvBgYDFFEAxE+B NqpI1AGSufjE8/kbQGoNYJqJ/xsRIqzoLS2bX07JjLbmLfuShWclNRCU8JLItP2NnuaZwUsKtxG4m baR2Ga7HwZCNc2UPU6l/MKScPqYIAHhqsnK95lyxwLUZryVoy0dkA2SpzebWBsSY+WnmFQJhTf7fQ K9QrELaZlf4po0tRU9B2wf5uG35nGlPiWO/7Prvf3X+6xFbij8u0UTAqEKO7CIM3pehFwfEOdijJd 63E/rSAw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghzp-001sKq-MX; Tue, 19 Apr 2022 07:09:58 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnx-001nbD-7D for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:43 +0000 Received: by mail-pj1-x1049.google.com with SMTP id v10-20020a17090a0c8a00b001c7a548e4f7so1188785pja.2 for ; Mon, 18 Apr 2022 23:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=JEHgWGXC0IGyIA5eE8wz+3k5C/TVMDQDmfAi50muP4E=; b=RhHlP7hgGeUD2CjcSSfimqmUChdwE2bH2GjXKlWM5/j3UQgqqhx6lx8GLaWJxsg4C0 KxnYyBp8j9Ub95dCV3wbNPlOi/46m46bBl1dpMSNoMPJUf1jE4tgCFCo2q5qEyZ70uxV KTSmCZqjJiGNBxSwlY4wLX4orvMM5bStg05ECjglKfGCWFNzscN6GEvbt0Bxo4vdqyz3 TuNDA6p3+vD3KoXm/LoaiogaivAMZAfLYoEgA3v8T6Zhm+iosT0VzxEcfjk0Tih94IR7 HCdug7BP0BnduCn425Oa53UrTo53AtKe9Q2r4J0+xOiBrE6itQ/ZQd/O+8JhPmNFOswQ Gp5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=JEHgWGXC0IGyIA5eE8wz+3k5C/TVMDQDmfAi50muP4E=; b=mqdazOaQtG04YvDzBW5GwtHwB1HXzHblWC0pu9p4r5/zRXri8bKIWfjkONgDzah5SQ EVsskoLjlNfHUmoEOWv+fWmRqKKDJCgu+Rfz7ahmrQnRN0C5XS7kZU03JlznI9m5kC8I v/geWN4QRGT2FWi/OqXSjIJRPndorLubl2gJm22KgXPJ6+cuHR0H2mAaMZsfTP9RCOxC FUo82Z1IwYVXjn/b+mR/DKCSw/ZOQv1yP/YFMn8bg5LMb6Vj4O8wVCcW+BJbkV7xHJZV wjWjw4FzpUyFi6UyudAb8gHgXMLTdDmtSXWsBGRSXhfvSdoXSpNSo7o9UXhQ/vW/P47+ wXuQ== X-Gm-Message-State: AOAM532NbpPH0hkYAE1pkDIjs8m44bPtRwegvymfx/k4xFVsRxwwZ81t ZFa8yqg5UCynixWLic9jQxmaezhPWVA= X-Google-Smtp-Source: ABdhPJzASKF1mdud+lojqbob7DwNr6IhW5KBhupg9DEi1JxaqrREIndqN+zLI2GeNUHkgP3K/a5UpF/tXz4= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:99c:b0:50a:9b27:a06d with SMTP id u28-20020a056a00099c00b0050a9b27a06dmr131007pfg.27.1650351460083; Mon, 18 Apr 2022 23:57:40 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:27 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-22-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 21/38] KVM: arm64: Add consistency checking for frac fields of ID registers From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235741_306376_858EA05B X-CRM114-Status: GOOD ( 22.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Feature fractional field of an ID register cannot be simply validated at KVM_SET_ONE_REG because its validity depends on its (main) feature field value, which could be in a different ID register (and might be set later). Validate fractional fields at the first KVM_RUN instead. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/arm.c | 3 + arch/arm64/kvm/sys_regs.c | 113 +++++++++++++++++++++++++++++- 3 files changed, 114 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index dbed94e759a8..b85af83b4542 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -789,6 +789,7 @@ long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, void set_default_id_regs(struct kvm *kvm); int kvm_set_id_reg_feature(struct kvm *kvm, u32 id, u8 field_shift, u8 fval); void kvm_vcpu_breakpoint_config(struct kvm_vcpu *vcpu); +int kvm_id_regs_check_frac_fields(const struct kvm_vcpu *vcpu); /* Guest/host FPSIMD coordination helpers */ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 04312f7ee0da..5c1cee04aa95 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -524,6 +524,9 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) if (likely(vcpu_has_run_once(vcpu))) return 0; + if (!kvm_vm_is_protected(kvm) && kvm_id_regs_check_frac_fields(vcpu)) + return -EPERM; + kvm_arm_vcpu_init_debug(vcpu); if (likely(irqchip_in_kernel(kvm))) { diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1045319c474e..fc7a8f2539a4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4028,6 +4028,100 @@ void kvm_sys_reg_table_init(void) id_reg_desc_init_all(); } +/* ID register's fractional field information with its feature field. */ +struct feature_frac { + u32 id; + u32 shift; + u32 frac_id; + u32 frac_shift; +}; + +static struct feature_frac feature_frac_table[] = { + { + .frac_id = SYS_ID_AA64PFR1_EL1, + .frac_shift = ID_AA64PFR1_RASFRAC_SHIFT, + .id = SYS_ID_AA64PFR0_EL1, + .shift = ID_AA64PFR0_RAS_SHIFT, + }, + { + .frac_id = SYS_ID_AA64PFR1_EL1, + .frac_shift = ID_AA64PFR1_MPAMFRAC_SHIFT, + .id = SYS_ID_AA64PFR0_EL1, + .shift = ID_AA64PFR0_MPAM_SHIFT, + }, + { + .frac_id = SYS_ID_AA64PFR1_EL1, + .frac_shift = ID_AA64PFR1_CSV2FRAC_SHIFT, + .id = SYS_ID_AA64PFR0_EL1, + .shift = ID_AA64PFR0_CSV2_SHIFT, + }, +}; + +/* + * Return non-zero if the feature/fractional fields pair are not + * supported. Return zero otherwise. + * This function validates only the fractional feature field, + * and relies on the fact the feature field is validated before + * through arm64_check_features. + */ +static int vcpu_id_reg_feature_frac_check(const struct kvm_vcpu *vcpu, + const struct feature_frac *ftr_frac) +{ + const struct id_reg_desc *id_reg; + u32 id; + u64 val, lim, mask; + + /* Check if the feature field value is same as the limit */ + id = ftr_frac->id; + + mask = ARM64_FEATURE_FIELD_MASK << ftr_frac->shift; + id_reg = get_id_reg_desc(id); + val = __read_id_reg(vcpu, id_reg) & mask; + lim = id_reg->vcpu_limit_val & mask; + + if (val != lim) + /* + * The feature level is lower than the limit. + * Any fractional version should be fine. + */ + return 0; + + /* Check the fractional feature field */ + id = ftr_frac->frac_id; + + mask = ARM64_FEATURE_FIELD_MASK << ftr_frac->frac_shift; + id_reg = get_id_reg_desc(id); + val = __read_id_reg(vcpu, id_reg) & mask; + lim = id_reg->vcpu_limit_val & mask; + + if (val == lim) + /* + * Both the feature and fractional fields are the same + * as limit. + */ + return 0; + + return arm64_check_features(id_reg->ftr_bits, val, lim); +} + +int kvm_id_regs_check_frac_fields(const struct kvm_vcpu *vcpu) +{ + int i, err; + const struct feature_frac *frac; + + /* + * Check ID registers' fractional fields, which aren't checked + * at KVM_SET_ONE_REG. + */ + for (i = 0; i < ARRAY_SIZE(feature_frac_table); i++) { + frac = &feature_frac_table[i]; + err = vcpu_id_reg_feature_frac_check(vcpu, frac); + if (err) + return err; + } + return 0; +} + /* * Update the ID register's field with @fval for the guest. * The caller is expected to hold the kvm->lock. @@ -4055,9 +4149,6 @@ static struct id_reg_desc id_aa64pfr0_el1_desc = { static struct id_reg_desc id_aa64pfr1_el1_desc = { .reg_desc = ID_SANITISED(ID_AA64PFR1_EL1), - .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_RASFRAC) | - ARM64_FEATURE_MASK(ID_AA64PFR1_MPAMFRAC) | - ARM64_FEATURE_MASK(ID_AA64PFR1_CSV2FRAC), .init = init_id_aa64pfr1_el1_desc, .validate = validate_id_aa64pfr1_el1, .vcpu_mask = vcpu_mask_id_aa64pfr1_el1, @@ -4329,6 +4420,8 @@ static void id_reg_desc_init_all(void) { int i; struct id_reg_desc *id_reg; + struct feature_frac *frac; + u64 ftr_mask = ARM64_FEATURE_FIELD_MASK; for (i = 0; i < ARRAY_SIZE(id_reg_desc_table); i++) { id_reg = (struct id_reg_desc *)id_reg_desc_table[i]; @@ -4337,6 +4430,20 @@ static void id_reg_desc_init_all(void) id_reg_desc_init(id_reg); } + + /* + * Update ignore_mask of ID registers based on fractional fields + * information. Any ID register that have fractional fields + * is expected to have its own id_reg_desc. + */ + for (i = 0; i < ARRAY_SIZE(feature_frac_table); i++) { + frac = &feature_frac_table[i]; + id_reg = get_id_reg_desc(frac->frac_id); + if (WARN_ON_ONCE(!id_reg)) + continue; + + id_reg->ignore_mask |= ftr_mask << frac->frac_shift; + } } /* From patchwork Tue Apr 19 06:55:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 258C6C433EF for ; Tue, 19 Apr 2022 07:12:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=gDk+IOaHZFP9jfxqJlcryv+GAjUj8BY32iky+wn8Ql0=; b=Cu7D3U9c4d/q2avsbRMfFNVPds EPIDiHTQXczHX+Wsym4ZhhU4xbLtraDM/yDctjOwRLqohmTrPRwBSu6NRcUJs02qqHbWR2U0RZ1U4 Ii1rzYMb08WwKkJR4KXQ+aSAtqBawiV8Jqey+OhpPsuGNuJevtmZJkR1KmnH9i0lmrqArXJeLns5N bLsQOE/xaURXHc0cKBKHjbuu4ULVrCLaftUbkkGMuqosqmm1p4YtRC2A2/Rl8qtRATAF9mBZHvbV1 8uFYbn3cOgjDbuEqKa5zzJBdth6HDwoI5K4hS1TLJGAyRNpFdCkunDh6JCwtZhy5UIfljmrR7JYf0 bS0Mqwow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi12-001skw-1g; Tue, 19 Apr 2022 07:11:13 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghnz-001ncS-1V for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:44 +0000 Received: by mail-pl1-x649.google.com with SMTP id x23-20020a170902b41700b0015906c1ea31so2612720plr.20 for ; Mon, 18 Apr 2022 23:57:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=U4uOGGGNJJAvE+8qhBWKzG6xiqX6UboPrGG2sNPZOY8=; b=BewbNlPjPqMatcm5XCUJOCpQZV4IoUW4ifHD5JfI6GHGlRBqW2sLCDsPuTDMbF2jUH Wlv1w+R+Edq3e7b8T/1GKHqWp2fKfCDQosSdPRzW1wXYl688u7L0nZNPdsN1cV8hUJlj dA7dU+yyYorRaosHIs3zf7EDl5GaiYDINtqkhAEv928ecEPq4g9QENwKQkaqEVUO+EdU kLtR11yTTd7eAasAJcwfVzE8tSgBo/4cH2y9b/7wc9XFcuKMcMQ188Jx2nOlz6c8Pt6r 4SpvFqlxMnxNrUpursSPLQOzcC+Kc38iLMoD9FEUJ9QWJjCdK6M8OTNlU4b8jYjVazsJ NFYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=U4uOGGGNJJAvE+8qhBWKzG6xiqX6UboPrGG2sNPZOY8=; b=RQMVCrV5gC7ulBw7KJhBWziTJfXEGfToNQD/rBr81AYmv1LWBvEBsCNxq9MK67y9lF o0/ulmZ6VmYEoS1FoF8fy9+wkcs03C8tpKOCTPI7cQ0qUy51vDKCNpfbjun3Og5yqVqA WzDgXRiLPchY2mYNegqEn/Yi3s54VP+PfPlELETVjJYNcDo25ecM6MLzJlkjsxBLbWSo qmNWk9och8Bk+mHBziFUFTWc67m11Y2QO+ozJ2BA7vZqQMo+IWjz8+E21w+MfB/KO8H3 ZMK4WbROIXgNDIY7h9I8I96qbsSO3yZ4GDqjk2nrJRN/NPNHCENM22HUiRjGwoMeF87e 8cDw== X-Gm-Message-State: AOAM532BW3KFE+GVNvlEN0Vz5sItfDa3HkOCOdiIyF6yDNi1eBeVKUH6 YzD1KN7tENVF1/hznmh7oCLbSpnpeAg= X-Google-Smtp-Source: ABdhPJwNvsMFXxj/P4c/uyL22/CuuuumZEIUldC8yuu2qFzsobmd9UhZjjZnKg5gGPfNpCl6SSEUeTinmLA= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90a:cc0b:b0:1cb:8351:a47e with SMTP id b11-20020a17090acc0b00b001cb8351a47emr17191716pju.67.1650351461844; Mon, 18 Apr 2022 23:57:41 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:28 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-23-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 22/38] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_CONFIGURABLE capability From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235743_131620_4443FDFD X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a new capability KVM_CAP_ARM_ID_REG_CONFIGURABLE to indicate that ID registers are writable by userspace. Signed-off-by: Reiji Watanabe --- Documentation/virt/kvm/api.rst | 16 ++++++++++++++++ arch/arm64/kvm/arm.c | 1 + include/uapi/linux/kvm.h | 1 + 3 files changed, 18 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 85c7abc51af5..e2e7b08e64c1 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -2601,6 +2601,14 @@ EINVAL. After the vcpu's SVE configuration is finalized, further attempts to write this register will fail with EPERM. +The arm64 ID registers with encoding Op0=3, Op1=0, CRn=0, 1<=CRm<8, 0<=Op2<8 +are allowed to modified by userspace only for AArch64 EL1 vCPUs if +KVM_CAP_ARM_ID_REG_CONFIGURABLE is available. +They become immutable after calling KVM_RUN on any of the +vcpus in the guest (modifying values of those registers will fail). +Those ID registers are always immutable for AArch32 EL1 vCPUs, which +KVM_ARM_VCPU_EL1_32BIT is configured for, even when +KVM_CAP_ARM_ID_REG_CONFIGURABLE is available. MIPS registers are mapped using the lower 32 bits. The upper 16 of that is the register group type: @@ -7724,6 +7732,14 @@ At this time, KVM_PMU_CAP_DISABLE is the only capability. Setting this capability will disable PMU virtualization for that VM. Usermode should adjust CPUID leaf 0xA to reflect that the PMU is disabled. +8.35 KVM_CAP_ARM_ID_REG_CONFIGURABLE +------------------------------------ + +:Architectures: arm64 + +This capability indicates that userspace can modify the ID registers +via KVM_SET_ONE_REG ioctl. + 9. Known KVM API problems ========================= diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 5c1cee04aa95..b4db368948cc 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -211,6 +211,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_SET_GUEST_DEBUG: case KVM_CAP_VCPU_ATTRIBUTES: case KVM_CAP_PTP_KVM: + case KVM_CAP_ARM_ID_REG_CONFIGURABLE: r = 1; break; case KVM_CAP_SET_GUEST_DEBUG2: diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 91a6fe4e02c0..171f1d0ea1e1 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1144,6 +1144,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_S390_MEM_OP_EXTENSION 211 #define KVM_CAP_PMU_CAPABILITY 212 #define KVM_CAP_DISABLE_QUIRKS2 213 +#define KVM_CAP_ARM_ID_REG_CONFIGURABLE 214 #ifdef KVM_CAP_IRQ_ROUTING From patchwork Tue Apr 19 06:55:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9BC5C433EF for ; Tue, 19 Apr 2022 07:17:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=TbGgsatNlXI+YnMcHkRDUl5ZPfLzxvRsKIXVClxtmq0=; b=hMIIs5YVtxYjxYfREM4aAhOXC7 BZgUAppjOkzNbjAtKUxSdW1JkunP0GoIv1Az0S5uI4l0taHQOla6Igmk8CiuHL64DjzYWaY/FEMvs 1//S/uLK6fjCauJg7OeTh2VrAelAsJ7dTFvS1M++qkSEeBw7uQAmA/PsuTnu0gE8q4s2nlWiCKRKm fhNMJYntbBM+NfKH8ugzvrxfItXl1Dl0othsMCauv70cW0hnx3pI129M5UhgiHYrqep9kRXZydmV6 /C9SMqUSbHNbCMb+YGl1LETnxgnlGoEwoIUViapzvV59sPV2bNuLWE/2MN/qkJQnTO4SvcGVigcyl 8QXPTKoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi5G-001uIe-GA; Tue, 19 Apr 2022 07:15:34 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngho0-001ndA-K5 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:53 +0000 Received: by mail-pj1-x1049.google.com with SMTP id z88-20020a17090a6d6100b001cb89a1969fso10145226pjj.1 for ; Mon, 18 Apr 2022 23:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Vbwtrqr+eHVV/oHotYjLI/3rV0rt1T+kM65UOU/rgIA=; b=REPpged9kFttbzIyZ/YCTSb0/AoOiPFxrc6ZizNpZjiCvowQkfRs4MrZqLc9pZmF5g 55y1bSYWXl39XsZqivfk0dNGnc3aQIZXk1Bfl42nbaxTeK8iQvmq03j5yRgRChR3Yvtg 4HT3uU9Zsz41ooAVIRNNHjT1PAxJFO6QMnOmPea8mFSUJH67F9kofqaDXNA/OUMK9TYS WvtVFJX+KXDj3678fqk5C7NDg6jzBD8xhujtOn3jpQD4ZKcXIt3Ks2o3HYCAFNJ/wuoR iXZWzM2lRrlWpLRu6oPd+enNnA6RGYXmQZyo4RGzZSpnz4c43307Iw6tPUJ264+0y6+V yYxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Vbwtrqr+eHVV/oHotYjLI/3rV0rt1T+kM65UOU/rgIA=; b=AAG8Oz9B53Mbh/uEDBrHX0rW1b9VrvVl9WWzIGTU3T8J38eqhmsEnIkOqProXDgXPl PM+7ThYqlRU/7slLxb6fsgKpS7JKRhb1RNsK3vp5KHCc7PvRYdqD4b94+xS+cJgO7Pfq zEAbFU75AnKRsZYaFdOyo/PVRdagmbhjmMPiU5ZULo5a/wa2g1/Jy2D8bEOyxDtVIiko XlVTxSqD0KJxmaabLrtUp+0I4rNuq6yHMnoRnUOY6o56oVXzwJ3EuvlNIOT63yN+eSaS XEl8OhAjjoQyGUjViLONqa7aclhf/5Ce4/aP7Z7tdY7yRJdlcNlnPZ1aSvt/lnby1CE+ OsDA== X-Gm-Message-State: AOAM532QDNqOnkNe9lH4PbBV/gFcYfopD7RygIUJZjHsEViRw7qrhQe7 wQwu+u3g2crgdhuaJ7BRdhzgM25ASxY= X-Google-Smtp-Source: ABdhPJwnhrejVRefMrvmQDGwzk9+Az3BAg+uNSDFoDPTXNp0c/NSEgSr4ixFwAHzivhuRewJuhcx0BiUDnM= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:26cf:b0:4f6:fc52:7b6a with SMTP id p15-20020a056a0026cf00b004f6fc527b6amr16349280pfw.39.1650351463411; Mon, 18 Apr 2022 23:57:43 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:29 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-24-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 23/38] KVM: arm64: Add kunit test for ID register validation From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235744_789130_87484194 X-CRM114-Status: GOOD ( 23.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add kunit tests for functions that are used for validation of ID registers, CONFIG_KVM_KUNIT_TEST option to enable the tests, and .kunitconfig to run the kunit tests. Since tools/testing/kunit/qemu_configs/arm64.py, which is the default qemu_config for arm64, doesn't have all params that the new tests needs, 'extra_qemu_params' in the default one needs to be replaced with the one below to fully run all of those kunit tests. extra_qemu_params=['-M virt,virtualization=on,mte=on', '-cpu max,sve=on']) (the default one: extra_qemu_params=['-machine virt', '-cpu cortex-a57']) The outputs from the tests are: ----------------------------------------------------------------------- $ tools/testing/kunit/kunit.py run --timeout=60 --jobs=`nproc --all` \ --arch=arm64 --cross_compile=aarch64-linux-gnu- \ --qemu_config arm64_kvm_min.py \ --kunitconfig=arch/arm64/kvm/.kunitconfig [22:45:39] Configuring KUnit Kernel ... [22:45:39] Building KUnit Kernel ... Populating config with: $ make ARCH=arm64 olddefconfig CROSS_COMPILE=aarch64-linux-gnu- O=.kunit Building with: $ make ARCH=arm64 --jobs=96 CROSS_COMPILE=aarch64-linux-gnu- O=.kunit [22:45:47] Starting KUnit Kernel (1/1)... [22:45:47] ============================================================ Running tests with: $ qemu-system-aarch64 -nodefaults -m 1024 -kernel .kunit/arch/arm64/boot/Image.gz -append 'mem=1G console=tty kunit_shutdown=halt console=ttyAMA0 kunit_shutdown=reboot' -no-reboot -nographic -serial stdio -M virt,virtualization=on,mte=on -cpu max,sve=on [22:45:48] ========== kvm-sys-regs-test-suite (14 subtests) =========== [22:45:48] =========== vcpu_id_reg_feature_frac_check_test ============ [22:45:48] [PASSED] feat - shift:28, val:1, lim:2, frac - shift:12, val:1, lim:1 [22:45:48] [PASSED] feat - shift:28, val:1, lim:2, frac - shift:12, val:1, lim:2 [22:45:48] [PASSED] feat - shift:28, val:1, lim:2, frac - shift:12, val:2, lim:1 [22:45:48] [PASSED] feat - shift:28, val:1, lim:1, frac - shift:12, val:1, lim:1 [22:45:48] [PASSED] feat - shift:28, val:1, lim:1, frac - shift:12, val:1, lim:2 [22:45:48] [PASSED] feat - shift:28, val:1, lim:1, frac - shift:12, val:2, lim:1 [22:45:48] ======= [PASSED] vcpu_id_reg_feature_frac_check_test ======= [22:45:48] ============ validate_id_aa64mmfr0_tgran2_test ============= [22:45:48] [PASSED] gran2(field=40): val=2, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=2, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=1, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=1 gran1: val=15 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=2 gran1: val=15 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=2 gran1: val=1 limit=0 [22:45:48] [PASSED] gran2(field=40): val=1, lim=0 gran1: val=0 limit=15 [22:45:48] [PASSED] gran2(field=40): val=1, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=2, lim=0 gran1: val=15 limit=15 [22:45:48] [PASSED] gran2(field=40): val=2, lim=0 gran1: val=0 limit=0 [22:45:48] ======== [PASSED] validate_id_aa64mmfr0_tgran2_test ======== [22:45:48] ============ validate_id_aa64mmfr0_tgran2_test ============= [22:45:48] [PASSED] gran2(field=36): val=2, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=36): val=2, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=36): val=1, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=36): val=0, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=36): val=0, lim=1 gran1: val=15 limit=0 [22:45:48] [PASSED] gran2(field=36): val=0, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=36): val=0, lim=2 gran1: val=15 limit=0 [22:45:48] [PASSED] gran2(field=36): val=1, lim=0 gran1: val=0 limit=15 [22:45:48] [PASSED] gran2(field=36): val=1, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=36): val=2, lim=0 gran1: val=15 limit=15 [22:45:48] [PASSED] gran2(field=36): val=2, lim=0 gran1: val=0 limit=0 [22:45:48] ======== [PASSED] validate_id_aa64mmfr0_tgran2_test ======== [22:45:48] ============ validate_id_aa64mmfr0_tgran2_test ============= [22:45:48] [PASSED] gran2(field=32): val=2, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=2, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=1, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=0, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=0, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=0, lim=1 gran1: val=1 limit=0 [22:45:48] [PASSED] gran2(field=32): val=0, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=0, lim=2 gran1: val=2 limit=2 [22:45:48] [PASSED] gran2(field=32): val=1, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=1, lim=0 gran1: val=0 limit=1 [22:45:48] [PASSED] gran2(field=32): val=2, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=32): val=2, lim=0 gran1: val=0 limit=1 [22:45:48] [PASSED] gran2(field=32): val=2, lim=0 gran1: val=0 limit=2 [22:45:48] ======== [PASSED] validate_id_aa64mmfr0_tgran2_test ======== [22:45:48] [PASSED] validate_id_aa64pfr0_el1_test [22:45:48] [PASSED] validate_id_aa64pfr1_el1_test [22:45:48] [PASSED] validate_id_aa64isar0_el1_test [22:45:48] [PASSED] validate_id_aa64isar1_el1_test [22:45:48] [PASSED] validate_id_aa64isar2_el1_test [22:45:48] ============== validate_id_aa64mmfr0_el1_test ============== [22:45:48] [PASSED] gran2(field=40): val=2, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=2, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=1, lim=2 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=1 gran1: val=15 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=1 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=2 gran1: val=15 limit=0 [22:45:48] [PASSED] gran2(field=40): val=0, lim=2 gran1: val=1 limit=0 [22:45:48] [PASSED] gran2(field=40): val=1, lim=0 gran1: val=0 limit=15 [22:45:48] [PASSED] gran2(field=40): val=1, lim=0 gran1: val=0 limit=0 [22:45:48] [PASSED] gran2(field=40): val=2, lim=0 gran1: val=15 limit=15 [22:45:48] [PASSED] gran2(field=40): val=2, lim=0 gran1: val=0 limit=0 [22:45:48] ========= [PASSED] validate_id_aa64mmfr0_el1_test ========== [22:45:48] [PASSED] validate_id_aa64dfr0_el1_test [22:45:48] [PASSED] validate_id_dfr0_el1_test [22:45:48] [PASSED] validate_mvfr1_el1_test [22:45:48] [PASSED] validate_id_reg_test [22:45:48] ============= [PASSED] kvm-sys-regs-test-suite ============= [22:45:48] ============================================================ [22:45:48] Testing complete. Passed: 63, Failed: 0, Crashed: 0, Skipped: 0, Errors: 0 [22:45:48] Elapsed time: 8.977s total, 0.003s configuring, 7.300s building, 1.620s running ----------------------------------------------------------------------- Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/.kunitconfig | 4 + arch/arm64/kvm/Kconfig | 11 + arch/arm64/kvm/sys_regs.c | 4 + arch/arm64/kvm/sys_regs_test.c | 1068 ++++++++++++++++++++++++++++++++ 4 files changed, 1087 insertions(+) create mode 100644 arch/arm64/kvm/.kunitconfig create mode 100644 arch/arm64/kvm/sys_regs_test.c diff --git a/arch/arm64/kvm/.kunitconfig b/arch/arm64/kvm/.kunitconfig new file mode 100644 index 000000000000..c564c98fc319 --- /dev/null +++ b/arch/arm64/kvm/.kunitconfig @@ -0,0 +1,4 @@ +CONFIG_KUNIT=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_KVM_KUNIT_TEST=y diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index 8a5fbbf084df..0d628d0e7dd5 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -56,4 +56,15 @@ config NVHE_EL2_DEBUG If unsure, say N. +config KVM_KUNIT_TEST + bool "KUnit tests for KVM on ARM64 processors" if !KUNIT_ALL_TESTS + depends on KVM && KUNIT + default KUNIT_ALL_TESTS + help + Say Y here to enable KUnit tests for the KVM on ARM64. + Only useful for KVM/ARM development and are not for inclusion into + a production build. + + If unsure, say N. + endif # VIRTUALIZATION diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index fc7a8f2539a4..a71c52aee34e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4486,3 +4486,7 @@ static void kvm_reset_id_regs(struct kvm_vcpu *vcpu) r->reset(vcpu, r); } } + +#if IS_ENABLED(CONFIG_KVM_KUNIT_TEST) +#include "sys_regs_test.c" +#endif diff --git a/arch/arm64/kvm/sys_regs_test.c b/arch/arm64/kvm/sys_regs_test.c new file mode 100644 index 000000000000..dff146fe0e62 --- /dev/null +++ b/arch/arm64/kvm/sys_regs_test.c @@ -0,0 +1,1068 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * KUnit tests for arch/arm64/kvm/sys_regs.c. + */ + +#include +#include +#include +#include +#include +#include "asm/sysreg.h" + +/* + * Create a vcpu with the minimum fields required for testing in this file + * including the struct kvm. Any resources that are allocated by this + * function must be allocated by kunit_* so that we don't need to explicitly + * free them. + */ +static struct kvm_vcpu *test_kvm_vcpu_init(struct kunit *test) +{ + struct kvm_vcpu *vcpu; + struct kvm *kvm; + + kvm = kunit_kzalloc(test, sizeof(struct kvm), GFP_KERNEL); + if (!kvm) + return NULL; + + vcpu = kunit_kzalloc(test, sizeof(struct kvm_vcpu), GFP_KERNEL); + if (!vcpu) { + kunit_kfree(test, kvm); + return NULL; + } + + vcpu->cpu = -1; + vcpu->kvm = kvm; + vcpu->vcpu_id = 0; + + return vcpu; +} + +static void test_kvm_vcpu_fini(struct kunit *test, struct kvm_vcpu *vcpu) +{ + if (vcpu->kvm) + kunit_kfree(test, vcpu->kvm); + + kunit_kfree(test, vcpu); +} + +/* Test parameter information to test arm64_check_features */ +struct check_features_test { + u64 check_types; + u64 value; + u64 limit; + int expected; +}; + + +/* Used to define test parameters of vcpu_id_reg_feature_frac_check_test() */ +struct feat_info { + u32 id; + u32 shift; + u32 value; + u32 limit; +}; + +struct frac_check_test { + struct feat_info feat; + struct feat_info frac_feat; + int ret; +}; + +#define FRAC_FEAT(id, shift, value, limit) {id, shift, value, limit} + +/* Tests parameters of vcpu_id_reg_feature_frac_check_test() */ +struct frac_check_test frac_params[] = { + { + /* + * The feature value is smaller than its limit. + * Expect no error regardless of the frac value. + */ + FRAC_FEAT(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_RAS_SHIFT, 1, 2), + FRAC_FEAT(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_RASFRAC_SHIFT, 1, 1), + 0, + }, + { + /* + * The feature value is smaller than its limit. + * Expect no error regardless of the frac value. + */ + FRAC_FEAT(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_RAS_SHIFT, 1, 2), + FRAC_FEAT(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_RASFRAC_SHIFT, 1, 2), + 0, + }, + { + /* + * The feature value is smaller than its limit. + * Expect no error regardless of the frac value. + */ + FRAC_FEAT(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_RAS_SHIFT, 1, 2), + FRAC_FEAT(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_RASFRAC_SHIFT, 2, 1), + 0, + }, + { + /* + * Both the feature and frac values are same as their limits. + * Expect no error. + */ + FRAC_FEAT(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_RAS_SHIFT, 1, 1), + FRAC_FEAT(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_RASFRAC_SHIFT, 1, 1), + 0, + }, + { + /* + * The feature value is same as its limit, and the frac value + * is smaller than its limit. Expect no error. + */ + FRAC_FEAT(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_RAS_SHIFT, 1, 1), + FRAC_FEAT(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_RASFRAC_SHIFT, 1, 2), + 0, + }, + { + /* + * The feature value is same as its limit, and the frac value + * is larger than its limit. Expect an error. + */ + FRAC_FEAT(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_RAS_SHIFT, 1, 1), + FRAC_FEAT(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_RASFRAC_SHIFT, 2, 1), + -E2BIG, + }, + +}; + +static void frac_case_to_desc(struct frac_check_test *t, char *desc) +{ + struct feat_info *feat = &t->feat; + struct feat_info *frac = &t->frac_feat; + + snprintf(desc, KUNIT_PARAM_DESC_SIZE, + "feat - shift:%d, val:%d, lim:%d, frac - shift:%d, val:%d, lim:%d\n", + feat->shift, feat->value, feat->limit, + frac->shift, frac->value, frac->limit); +} + +KUNIT_ARRAY_PARAM(frac, frac_params, frac_case_to_desc); + +/* Tests for vcpu_id_reg_feature_frac_check(). */ +static void vcpu_id_reg_feature_frac_check_test(struct kunit *test) +{ + struct kvm_vcpu *vcpu; + u32 id, frac_id; + struct id_reg_desc id_data, frac_id_data; + struct id_reg_desc *idr, *frac_idr; + struct feature_frac frac_data, *frac = &frac_data; + const struct frac_check_test *frct = test->param_value; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + id = frct->feat.id; + frac_id = frct->frac_feat.id; + + frac->id = id; + frac->shift = frct->feat.shift; + frac->frac_id = frac_id; + frac->frac_shift = frct->frac_feat.shift; + + idr = get_id_reg_desc(id); + frac_idr = get_id_reg_desc(frac_id); + + /* Save the original id_reg_desc (and restore later) */ + memcpy(&id_data, idr, sizeof(id_data)); + memcpy(&frac_id_data, frac_idr, sizeof(frac_id_data)); + + /* The id could be same as the frac_id */ + idr->vcpu_limit_val = (u64)frct->feat.limit << frac->shift; + frac_idr->vcpu_limit_val |= + (u64)frct->frac_feat.limit << frac->frac_shift; + + write_kvm_id_reg(vcpu->kvm, id, (u64)frct->feat.value << frac->shift); + write_kvm_id_reg(vcpu->kvm, frac_id, + (u64)frct->frac_feat.value << frac->frac_shift); + + KUNIT_EXPECT_EQ(test, + vcpu_id_reg_feature_frac_check(vcpu, frac), + frct->ret); + + /* Restore id_reg_desc */ + memcpy(idr, &id_data, sizeof(id_data)); + memcpy(frac_idr, &frac_id_data, sizeof(frac_id_data)); +} + +/* + * Test parameter information to test validate_id_aa64mmfr0_tgran2 + * and validate_id_aa64mmfr0_el1_test. + */ +struct tgran_test { + int gran2_field; + int gran2; + int gran2_lim; + int gran1; + int gran1_lim; + int ret; +}; + +/* + * Test parameters of validate_id_aa64mmfr0_tgran2_test() for TGran4_2. + * Defined values for the field are: + * 0x0: Support for 4KB granule at stage 2 is identified in TGran4. + * 0x1: 4KB granule not supported at stage 2. + * 0x2: 4KB granule supported at stage 2. + * 0x3: 4KB granule at stage 2 supports 52-bit input and output addresses. + * + * Defined values for the TGran4 are: + * 0x0: 4KB granule supported. + * 0x1: 4KB granule supports 52-bit input and output addresses. + * 0xf: 4KB granule not supported. + */ +struct tgran_test tgran4_2_test_params[] = { + /* Enable 4KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 2, 2, 0, 0, 0}, + /* Enable 4KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 2, 1, 0, 0, -E2BIG}, + /* Disable 4KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 1, 2, 0, 0, 0}, + /* Enable 4KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 0, 0, 0, 0, 0}, + /* Disable 4KB granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 0, 1, 0xf, 0, 0}, + /* Enable 4KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 0, 1, 0, 0, -E2BIG}, + /* Disable 4KB granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 0, 2, 0xf, 0, 0}, + /* + * Enable 4KB granule with 52 bit address on the host that doesn't + * support it. + */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 0, 2, 1, 0, -E2BIG}, + /* Disable 4KB granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 1, 0, 0, 0xf, 0}, + /* Disable 4KB granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 1, 0, 0, 0, 0}, + /* Enable 4KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 2, 0, 0xf, 0xf, -E2BIG}, + /* Enable 4KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN4_2_SHIFT, 2, 0, 0, 0, 0}, +}; + +/* + * Test parameters of validate_id_aa64mmfr0_tgran2_test() for TGran64_2. + * Defined values for the field are: + * 0x0: Support for 64KB granule at stage 2 is identified in TGran64. + * 0x1: 64KB granule not supported at stage 2. + * 0x2: 64KB granule supported at stage 2. + * 0x3: 64KB granule at stage 2 supports 52-bit input and output addresses. + * + * Defined values for the TGran64 are: + * 0x0: 64KB granule supported. + * 0xf: 64KB granule not supported. + */ +struct tgran_test tgran64_2_test_params[] = { + /* Enable 64KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 2, 2, 0, 0, 0}, + /* Enable 64KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 2, 1, 0, 0, -E2BIG}, + /* Enable 64KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 1, 2, 0, 0, 0}, + /* Enable 64KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 0, 0, 0, 0, 0}, + /* Disable 64KB granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 0, 1, 0xf, 0, 0}, + /* Enable 64KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 0, 1, 0, 0, -E2BIG}, + /* Disable 64KB granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 0, 2, 0xf, 0, 0}, + /* Disable 64KB granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 1, 0, 0, 0xf, 0}, + /* Disable 64KB granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 1, 0, 0, 0, 0}, + /* Enable 64KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 2, 0, 0xf, 0xf, -E2BIG}, + /* Enable 64KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN64_2_SHIFT, 2, 0, 0, 0, 0}, +}; + +/* + * Test parameters of validate_id_aa64mmfr0_tgran2_test() for TGran16_2 + * Defined values for the field are: + * 0x0: Support for 16KB granule at stage 2 is identified in TGran16. + * 0x1: 16KB granule not supported at stage 2. + * 0x2: 16KB granule supported at stage 2. + * 0x3: 16KB granule at stage 2 supports 52-bit input and output addresses. + * + * Defined values for the TGran16 are: + * 0x0: 16KB granule not supported. + * 0x1: 16KB granule supported. + * 0x2: 16KB granule supports 52-bit input and output addresses. + */ +struct tgran_test tgran16_2_test_params[] = { + /* Enable 16KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 2, 2, 0, 0, 0}, + /* Enable 16KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 2, 1, 0, 0, -E2BIG}, + /* Disable 16KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 1, 2, 0, 0, 0}, + /* Disable 16KB granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 0, 0, 0, 0, 0}, + /* Disable 16KB granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 0, 1, 0, 0, 0}, + /* Enable 16KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 0, 1, 1, 0, -E2BIG}, + /* Disable 16KB granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 0, 2, 0, 0, 0}, + /* + * Enable 16KB granule with 52 bit address on the host that doesn't + * support it. + */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 0, 2, 2, 2, -E2BIG}, + /* Disable 16KB granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 1, 0, 0, 0, 0}, + /* Disable 16KB granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 1, 0, 0, 1, 0}, + /* Enable 16KB granule on the host that doesn't support the granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 2, 0, 0, 0, -E2BIG}, + /* Enable 16KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 2, 0, 0, 1, 0}, + /* Enable 16KB granule on the host that supports the granule */ + {ID_AA64MMFR0_TGRAN16_2_SHIFT, 2, 0, 0, 2, 0}, +}; + +static void tgran2_case_to_desc(struct tgran_test *t, char *desc) +{ + snprintf(desc, KUNIT_PARAM_DESC_SIZE, + "gran2(field=%d): val=%d, lim=%d gran1: val=%d limit=%d\n", + t->gran2_field, t->gran2, t->gran2_lim, + t->gran1, t->gran1_lim); +} + +KUNIT_ARRAY_PARAM(tgran4_2, tgran4_2_test_params, tgran2_case_to_desc); +KUNIT_ARRAY_PARAM(tgran64_2, tgran64_2_test_params, tgran2_case_to_desc); +KUNIT_ARRAY_PARAM(tgran16_2, tgran16_2_test_params, tgran2_case_to_desc); + +#define MAKE_MMFR0_TGRAN(shift1, gran1, shift2, gran2) \ + (((u64)((gran1) & 0xf) << (shift1)) | \ + ((u64)((gran2) & 0xf) << (shift2))) + +/* Return the bit position of TGranX field for the given TGranX_2 field. */ +static int tgran2_to_tgran1_shift(int tgran2_shift) +{ + int tgran1_shift = -1; + + switch (tgran2_shift) { + case ID_AA64MMFR0_TGRAN4_2_SHIFT: + tgran1_shift = ID_AA64MMFR0_TGRAN4_SHIFT; + break; + case ID_AA64MMFR0_TGRAN64_2_SHIFT: + tgran1_shift = ID_AA64MMFR0_TGRAN64_SHIFT; + break; + case ID_AA64MMFR0_TGRAN16_2_SHIFT: + tgran1_shift = ID_AA64MMFR0_TGRAN16_SHIFT; + break; + default: + break; + } + + return tgran1_shift; +} + +/* Tests for validate_id_aa64mmfr0_el1(). */ +static void validate_id_aa64mmfr0_tgran2_test(struct kunit *test) +{ + const struct tgran_test *t = test->param_value; + int shift1, shift2; + u64 v, lim; + + shift2 = t->gran2_field; + shift1 = tgran2_to_tgran1_shift(shift2); + v = MAKE_MMFR0_TGRAN(shift1, t->gran1, shift2, t->gran2); + lim = MAKE_MMFR0_TGRAN(shift1, t->gran1_lim, shift2, t->gran2_lim); + + KUNIT_EXPECT_EQ(test, aa64mmfr0_tgran2_check(shift2, v, lim), t->ret); +} + +/* Tests for validate_id_aa64pfr0_el1(). */ +static void validate_id_aa64pfr0_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + id_reg = get_id_reg_desc(SYS_ID_AA64PFR0_EL1); + + v = 0; + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + /* + * Tests for GIC. + * GIC must be 1 when vGIC3 is configured. + */ + v = 0x0000000; /* GIC = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + /* Test with VGIC_V2 */ + vcpu->kvm->arch.vgic.in_kernel = true; + vcpu->kvm->arch.vgic.vgic_model = KVM_DEV_TYPE_ARM_VGIC_V2; + + v = 0x0000000; /* GIC = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + /* Test with VGIC_V3 */ + vcpu->kvm->arch.vgic.vgic_model = KVM_DEV_TYPE_ARM_VGIC_V3; + + v = 0x0000000; /* GIC = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + v = 0x1000000; /* GIC = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + /* Restore the original VGIC state */ + vcpu->kvm->arch.vgic.in_kernel = false; + vcpu->kvm->arch.vgic.vgic_model = 0; + + /* + * Tests for AdvSIMD/FP. + * AdvSIMD must have the same value as FP. + */ + + /* Tests with SVE disabled */ + v = 0x000010000; /* AdvSIMD = 0, FP = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + v = 0x000100000; /* AdvSIMD = 1, FP = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + v = 0x000ff0000; /* AdvSIMD = 0xf, FP = 0xf */ + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + v = 0x100000000; /* SVE =1, AdvSIMD = 0, FP = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + if (!system_supports_sve()) { + kunit_skip(test, "No SVE support. Partial skip)"); + /* Not reached */ + } + + /* Tests with SVE enabled */ + vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE; + + v = 0x100000000; /* SVE =1, AdvSIMD = 0, FP = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + v = 0x100ff0000; /* SVE =1, AdvSIMD = 0, FP = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64pfr0_el1(vcpu, id_reg, v), 0); + + vcpu->arch.flags &= ~KVM_ARM64_GUEST_HAS_SVE; +} + +/* Tests for validate_id_aa64pfr1_el1() */ +static void validate_id_aa64pfr1_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + id_reg = get_id_reg_desc(SYS_ID_AA64PFR1_EL1); + v = 0; + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr1_el1(vcpu, id_reg, v), 0); + + /* Tests for MTE */ + + /* Tests with MTE disabled */ + + v = 0x000; /* MTE = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr1_el1(vcpu, id_reg, v), 0); + + v = 0x100; /* MTE = 1*/ + KUNIT_EXPECT_NE(test, validate_id_aa64pfr1_el1(vcpu, id_reg, v), 0); + + if (!system_supports_mte()) { + kunit_skip(test, "(No MTE support. Partial skip)"); + /* Not reached */ + } + + /* Tests with MTE enabled */ + set_bit(KVM_ARCH_FLAG_MTE_ENABLED, &vcpu->kvm->arch.flags); + + v = 0x100; /* MTE = 1*/ + KUNIT_EXPECT_EQ(test, validate_id_aa64pfr1_el1(vcpu, id_reg, v), 0); + + v = 0x0; /* MTE = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64pfr1_el1(vcpu, id_reg, v), 0); +} + +/* Tests for validate_id_aa64isar0_el1(). */ +static void validate_id_aa64isar0_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + id_reg = get_id_reg_desc(SYS_ID_AA64ISAR0_EL1); + + v = 0; + KUNIT_EXPECT_EQ(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + /* + * Tests for SM3/SM4. + * Arm ARM says SM3 must have the same value as SM4. + */ + + v = 0x01000000000; /* SM4 = 0, SM3 = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x10000000000; /* SM4 = 1, SM3 = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x11000000000; /* SM3 = SM4 = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + + /* + * Tests for SHA1/SHA2/SHA3. Arm ARM says: + * If SHA1 is 0x0, both SHA2 and SHA3 must be 0x0. + * If SHA2 is 0x0, SHA1 must be 0x0. + * If SHA2 is 0x2, SHA3 must be 0x1. + * If SHA3 is 0x1, SHA2 msut be 0x2. + */ + + v = 0x000000100; /* SHA2 = 0, SHA1 = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x000001000; /* SHA2 = 1, SHA1 = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x000001100; /* SHA2 = 1, SHA1 = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x100002000; /* SHA3 = 1, SHA2 = 2 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x000002000; /* SHA3 = 0, SHA2 = 2 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x100001000; /* SHA3 = 1, SHA2 = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x200000000; /* SHA3 = 2, SHA1 = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x200001100; /* SHA3 = 2, SHA2= 1, SHA1 = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); + + v = 0x300003300; /* SHA3 = 3, SHA2 = 3, SHA1 = 3 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar0_el1(vcpu, id_reg, v), 0); +} + +/* Tests for validate_id_aa64isar1_el1() */ +static void validate_id_aa64isar1_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v, org_limit; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + id_reg = get_id_reg_desc(SYS_ID_AA64ISAR1_EL1); + + /* + * Tests for GPI/GPA/API/APA. + * Arm ARM says: + * If GPA is non-zero, GPI must be zero. + * If GPI is non-zero, GPA must be zero. + * If APA is non-zero, API must be zero. + * If API is non-zero, APA must be zero. + */ + + v = 0x11000110; /* GPI = 1, GPA = 1, API = 1, APA = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x11000100; /* GPI = 1, GPA = 1, API = 1, APA = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x11000010; /* GPI = 1, GPA = 1, API = 0, APA = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x10000110; /* GPI = 1, GPA = 0, API = 1, APA = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x01000110; /* GPI = 0, GPA = 1, API = 1, APA = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + /* Tests with PTRAUTH disabled */ + + /* Just for convenience, set all of GPI/GPA/API/APA to 1. */ + org_limit = id_reg->vcpu_limit_val; + id_reg->vcpu_limit_val = 0x11000110; + + v = 0x00000000; /* GPI = 0, GPA = 0, API = 0, APA = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x10000100; /* GPI = 1, GPA = 0, API = 1, APA = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x10000010; /* GPI = 1, GPA = 0, API = 0, APA = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x01000100; /* GPI = 0, GPA = 1, API = 1, APA = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x01000010; /* GPI = 0, GPA = 1, API = 0, APA = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + if (!system_has_full_ptr_auth()) { + id_reg->vcpu_limit_val = org_limit; + kunit_skip(test, "(No PTRAUTH support. Partial skip)"); + /* Not reached */ + } + + /* Tests with PTRAUTH enabled */ + vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH; + + v = 0x10000100; /* GPI = 1, GPA = 0, API = 1, APA = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x10000010; /* GPI = 1, GPA = 0, API = 0, APA = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x01000100; /* GPI = 0, GPA = 1, API = 1, APA = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0x01000010; /* GPI = 0, GPA = 1, API = 0, APA = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + + v = 0; + KUNIT_EXPECT_NE(test, validate_id_aa64isar1_el1(vcpu, id_reg, v), 0); + /* Restore the original value */ + id_reg->vcpu_limit_val = org_limit; +} + +/* Tests for validate_id_aa64isar2_el1() */ +static void validate_id_aa64isar2_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v, org_limit; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + id_reg = get_id_reg_desc(SYS_ID_AA64ISAR2_EL1); + + /* Tests for GPA3/APA3. */ + + /* Tests with PTRAUTH disabled */ + + /* Set the limit of APA3/GPA3 to 1. */ + org_limit = id_reg->vcpu_limit_val; + id_reg->vcpu_limit_val = 0x1100; + + v = 0x0000; /* GPA3 = 0, APA3 = 0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + v = 0x1000; /* GPA3 = 1, APA3 = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + v = 0x0100; /* GPA3 = 0, APA3 = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + v = 0x1100; /* GPA3 = 1, APA3 = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + if (!system_has_full_ptr_auth()) { + id_reg->vcpu_limit_val = org_limit; + kunit_skip(test, "(No PTRAUTH support. Partial skip)"); + /* Not reached */ + } + + /* Tests with PTRAUTH enabled */ + vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH; + + v = 0x1100; /* APA3 = 1, GPA3 = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + v = 0x1000; /* APA3 = 1, GPA3 = 0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + v = 0x0100; /* APA3 = 0, GPA3 = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + v = 0; + KUNIT_EXPECT_NE(test, validate_id_aa64isar2_el1(vcpu, id_reg, v), 0); + + /* Restore the original value */ + id_reg->vcpu_limit_val = org_limit; +} + + +/* Tests for validate_id_aa64mmfr0_el1() */ +static void validate_id_aa64mmfr0_el1_test(struct kunit *test) +{ + struct id_reg_desc id_data, *id_reg; + const struct tgran_test *t4, *t64, *t16; + struct kvm_vcpu *vcpu; + int field4, field4_2, field64, field64_2, field16, field16_2; + u64 v, v4, lim4, v64, lim64, v16, lim16; + int i, j, ret; + + id_reg = get_id_reg_desc(SYS_ID_AA64MMFR0_EL1); + + /* Save the original id_reg_desc (and restore later) */ + memcpy(&id_data, id_reg, sizeof(id_data)); + + vcpu = test_kvm_vcpu_init(test); + + t4 = test->param_value; + field4_2 = t4->gran2_field; + field4 = tgran2_to_tgran1_shift(field4_2); + v4 = MAKE_MMFR0_TGRAN(field4, t4->gran1, field4_2, t4->gran2); + lim4 = MAKE_MMFR0_TGRAN(field4, t4->gran1_lim, field4_2, t4->gran2_lim); + + /* + * For each given gran4_2 params, test validate_id_aa64mmfr0_el1 + * with each of tgran64_2 and tgran16_2 params. + */ + for (i = 0; i < ARRAY_SIZE(tgran64_2_test_params); i++) { + t64 = &tgran64_2_test_params[i]; + field64_2 = t64->gran2_field; + field64 = tgran2_to_tgran1_shift(field64_2); + v64 = MAKE_MMFR0_TGRAN(field64, t64->gran1, + field64_2, t64->gran2); + lim64 = MAKE_MMFR0_TGRAN(field64, t64->gran1_lim, + field64_2, t64->gran2_lim); + + for (j = 0; j < ARRAY_SIZE(tgran16_2_test_params); j++) { + t16 = &tgran16_2_test_params[j]; + + field16_2 = t16->gran2_field; + field16 = tgran2_to_tgran1_shift(field16_2); + v16 = MAKE_MMFR0_TGRAN(field16, t16->gran1, + field16_2, t16->gran2); + lim16 = MAKE_MMFR0_TGRAN(field16, t16->gran1_lim, + field16_2, t16->gran2_lim); + + /* Build id_aa64mmfr0_el1 from tgran16/64/4 values */ + v = v16 | v64 | v4; + id_reg->vcpu_limit_val = lim16 | lim64 | lim4; + + ret = t4->ret ? t4->ret : t64->ret; + ret = ret ? ret : t16->ret; + KUNIT_EXPECT_EQ(test, + validate_id_aa64mmfr0_el1(vcpu, id_reg, v), + ret); + } + } + + /* Restore id_reg_desc */ + memcpy(id_reg, &id_data, sizeof(id_data)); +} + +/* Tests for validate_id_aa64dfr0_el1() */ +static void validate_id_aa64dfr0_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v; + + id_reg = get_id_reg_desc(SYS_ID_AA64DFR0_EL1); + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + v = 0; + KUNIT_EXPECT_EQ(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + /* + * Tests for CTX_CMPS/BRPS. + * Number of context-aware breakpoints can be no more than number + * of supported breakpoints. + */ + v = 0x10001000; /* CTX_CMPS = 1, BRPS = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x20001000; /* CTX_CMPS = 2, BRPS = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + /* Tests for PMUVer */ + + /* Tests with PMUv3 disabled. */ + + v = 0x000; /* PMUVER = 0x0 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + v = 0xf00; /* PMUVER = 0xf */ + KUNIT_EXPECT_EQ(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x100; /* PMUVER = 1 */ + KUNIT_EXPECT_NE(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + /* Tests with PMUv3 enabled */ + set_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features); + + v = 0x000; /* PMUVER = 0x0 */ + KUNIT_EXPECT_NE(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x000; /* PMUVER = 0xf */ + KUNIT_EXPECT_NE(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x100; /* PMUVER = 1 */ + KUNIT_EXPECT_EQ(test, validate_id_aa64dfr0_el1(vcpu, id_reg, v), 0); +} + +/* Tests for validate_id_dfr0_el1() */ +static void validate_id_dfr0_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v; + + id_reg = get_id_reg_desc(SYS_ID_DFR0_EL1); + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + v = 0; + KUNIT_EXPECT_EQ(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + /* Tests for PERFMON */ + + /* Tests with PMUv3 disabled */ + + v = 0x0000000; /* PERFMON = 0x0 */ + KUNIT_EXPECT_EQ(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0xf000000; /* PERFMON = 0xf */ + KUNIT_EXPECT_EQ(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x1000000; /* PERFMON = 1 */ + KUNIT_EXPECT_NE(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x2000000; /* PERFMON = 2 */ + KUNIT_EXPECT_NE(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x3000000; /* PERFMON = 3 */ + KUNIT_EXPECT_NE(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + + /* Tests with PMUv3 enabled */ + set_bit(KVM_ARM_VCPU_PMU_V3, vcpu->arch.features); + + v = 0x0000000; /* PERFMON = 0x0 */ + KUNIT_EXPECT_NE(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0xf000000; /* PERFMON = 0xf */ + KUNIT_EXPECT_NE(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x1000000; /* PERFMON = 1 */ + KUNIT_EXPECT_NE(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x2000000; /* PERFMON = 2 */ + KUNIT_EXPECT_NE(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); + + v = 0x3000000; /* PERFMON = 3 */ + KUNIT_EXPECT_EQ(test, validate_id_dfr0_el1(vcpu, id_reg, v), 0); +} + +/* Tests for validate_mvfr1_el1(). */ +static void validate_mvfr1_el1_test(struct kunit *test) +{ + struct id_reg_desc *id_reg; + struct kvm_vcpu *vcpu; + u64 v; + + id_reg = get_id_reg_desc(SYS_MVFR1_EL1); + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + v = 0; + KUNIT_EXPECT_EQ(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); + + /* + * Tests for FPHP/SIMDHP. + * Arm ARM says the level of support indicated by FPHP must be + * equivalent to the level of support indicated by the SIMDHP, + * meaning the permitted values are: + * FPHP = 0x0, SIMDHP = 0x0 + * FPHP = 0x2, SIMDHP = 0x1 + * FPHP = 0x3, SIMDHP = 0x2 + */ + v = 0x0000000; /* FPHP = 0, SIMDHP = 0 */ + KUNIT_EXPECT_EQ(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); + + v = 0x2100000; /* FPHP = 2, SIMDHP = 1 */ + KUNIT_EXPECT_EQ(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); + + v = 0x3200000; /* FPHP = 3, SIMDHP = 2 */ + KUNIT_EXPECT_EQ(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); + + v = 0x1100000; /* FPHP = 1, SIMDHP = 1 */ + KUNIT_EXPECT_NE(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); + + v = 0x2200000; /* FPHP = 2, SIMDHP = 2 */ + KUNIT_EXPECT_NE(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); + + v = 0x3300000; /* FPHP = 3, SIMDHP = 3 */ + KUNIT_EXPECT_NE(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); + + v = (u64)-1; + KUNIT_EXPECT_NE(test, validate_mvfr1_el1(vcpu, id_reg, v), 0); +} + +/* + * Helper function for validate_id_reg_test(). + * We don't use KUNIT_ASSERT or kunit_skip because this is a helper test + * function and we are not sure if it's safe to exist from the test case. + */ +static void validate_id_reg_test_one_field(struct kunit *test, + u32 id, int pos, int fval, int flimit, + bool is_signed, struct id_reg_desc *idr) +{ + struct kvm_vcpu *vcpu; + int fmin = is_signed ? -1 : 0; + int fmax = is_signed ? 7 : 15; + u64 fmask = ARM64_FEATURE_FIELD_MASK; + u64 val; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + if (flimit > fmax) { + /* Shouldn't happen. Make the test failure. */ + KUNIT_EXPECT_FALSE(test, flimit > fmax); + kunit_err(test, "%s: flimit(%d) > fmax(%d). Must be test bug", + __func__, flimit, fmax); + return; + } + + if (fval > fmin) { + /* Set the field to a smaller value */ + val = ((u64)(fval - 1) & fmask) << pos; + KUNIT_EXPECT_EQ(test, validate_id_reg(vcpu, idr, val), 0); + } + + if (fval < flimit) { + /* Set the field to a larger value, but smaller than flimit */ + val = ((u64)(fval + 1) & fmask) << pos; + KUNIT_EXPECT_EQ(test, validate_id_reg(vcpu, idr, val), 0); + + /* Set the field to the flimit */ + val = ((u64)flimit & fmask) << pos; + KUNIT_EXPECT_EQ(test, validate_id_reg(vcpu, idr, val), 0); + } + + if (flimit < fmax) { + /* Set the field to a larger value than flimit */ + val = ((u64)(flimit + 1) & fmask) << pos; + KUNIT_EXPECT_NE(test, validate_id_reg(vcpu, idr, val), 0); + + /* Test with ignore_mask */ + if (idr) { + idr->ignore_mask = fmask << pos; + KUNIT_EXPECT_EQ(test, validate_id_reg(vcpu, idr, val), 0); + } + } + test_kvm_vcpu_fini(test, vcpu); +} + +static void set_sys_desc(struct sys_reg_desc *rd, u32 encoding) +{ + rd->Op0 = sys_reg_Op0(encoding); + rd->Op1 = sys_reg_Op1(encoding); + rd->CRn = sys_reg_CRn(encoding); + rd->CRm = sys_reg_CRm(encoding); + rd->Op2 = sys_reg_Op2(encoding); +} + +/* + * Test for validate_id_reg(). + */ +static void validate_id_reg_test(struct kunit *test) +{ + struct id_reg_desc idr_data, *idr, *original_idr; + u32 id; + int fval, flim, pos; + u64 val; + bool sign; + + /* Use AA64PFR0_EL1 because it includes both sign/unsigned fields */ + id = SYS_ID_AA64PFR0_EL1; + + /* Test with a temporary id_reg_desc for testing */ + idr = &idr_data; + + fval = 0x1; + flim = 0x2; + + /* Test with unsigned field */ + pos = ID_AA64PFR0_RAS_SHIFT; + + /* Set up id_reg_desc for testing */ + memset(idr, 0, sizeof(*idr)); + set_sys_desc((struct sys_reg_desc *)&idr->reg_desc, id); + + /* Copy ftr_bits from the original one */ + original_idr = get_id_reg_desc(id); + memcpy(idr->ftr_bits, original_idr->ftr_bits, sizeof(idr->ftr_bits)); + idr->vcpu_limit_val = (u64)flim << pos; + validate_id_reg_test_one_field(test, id, pos, fval, flim, false, idr); + + /* Test with signed field */ + pos = ID_AA64PFR0_FP_SHIFT; + + /* Set up id_reg_desc for testing */ + memset(idr, 0, sizeof(*idr)); + set_sys_desc((struct sys_reg_desc *)&idr->reg_desc, id); + + /* Copy ftr_bits from the original one */ + memcpy(idr->ftr_bits, original_idr->ftr_bits, sizeof(idr->ftr_bits)); + + idr->vcpu_limit_val = (u64)flim << pos; + validate_id_reg_test_one_field(test, id, pos, fval, flim, true, idr); + + /* Test with the original limit val */ + val = original_idr->vcpu_limit_val; + idr->vcpu_limit_val = val; + + for (pos = 0; pos < 64; pos += 4) { + if (pos == ID_AA64PFR0_FP_SHIFT || + pos == ID_AA64PFR0_ASIMD_SHIFT) + sign = true; + else + sign = false; + + fval = cpuid_feature_extract_field(val, pos, sign); + validate_id_reg_test_one_field(test, id, pos, fval, fval, + sign, idr); + } +} + +static struct kunit_case kvm_sys_regs_test_cases[] = { + KUNIT_CASE_PARAM(vcpu_id_reg_feature_frac_check_test, frac_gen_params), + KUNIT_CASE_PARAM(validate_id_aa64mmfr0_tgran2_test, tgran4_2_gen_params), + KUNIT_CASE_PARAM(validate_id_aa64mmfr0_tgran2_test, tgran64_2_gen_params), + KUNIT_CASE_PARAM(validate_id_aa64mmfr0_tgran2_test, tgran16_2_gen_params), + KUNIT_CASE(validate_id_aa64pfr0_el1_test), + KUNIT_CASE(validate_id_aa64pfr1_el1_test), + KUNIT_CASE(validate_id_aa64isar0_el1_test), + KUNIT_CASE(validate_id_aa64isar1_el1_test), + KUNIT_CASE(validate_id_aa64isar2_el1_test), + KUNIT_CASE_PARAM(validate_id_aa64mmfr0_el1_test, tgran4_2_gen_params), + KUNIT_CASE(validate_id_aa64dfr0_el1_test), + KUNIT_CASE(validate_id_dfr0_el1_test), + KUNIT_CASE(validate_mvfr1_el1_test), + KUNIT_CASE(validate_id_reg_test), + {} +}; + +static struct kunit_suite kvm_sys_regs_test_suite = { + .name = "kvm-sys-regs-test-suite", + .test_cases = kvm_sys_regs_test_cases, +}; + +kunit_test_suites(&kvm_sys_regs_test_suite); +MODULE_LICENSE("GPL"); From patchwork Tue Apr 19 06:55:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3972C433EF for ; Tue, 19 Apr 2022 07:13:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=KQqu0GktpY89qI4e21J2ZrdmtCpnNhwA1vg6PsOOCUE=; b=2Oa4lFXdKKiUkm5P6c7R9YdkpK tKEUvKgd22CWRQ3Rtmj8NatiAwZLNhECbLt81pc1nQLI8tPFNvxf80KfNb8FhM1KHxJ8t3D8iw4Vt 6EUnDJ6Lg5fL7AvHTI0OY43HRY860riUIBhabHcEpNemz5KWBqkI7rocOM//FKPDFwj3c29C8Sjy1 sSm2sySZEYbNaBpCYPmI6R2lDcO1UFOTzGLHlFBtMp7KbAGcCq8yufPHLpVQ+hHtqhBCbpsO+auAz Q0RFh7IghKI06JKaEcnhon7Pxnf2L6HGruAmgIsG1xmUu+a0vytv0A5cUN53ngGyDsJPw7hq3barw nlS0T3Bg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi2F-001tEx-4p; Tue, 19 Apr 2022 07:12:28 +0000 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngho1-001neN-Rm for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:49 +0000 Received: by mail-pl1-x64a.google.com with SMTP id n2-20020a170903404200b00158db7879ddso5462428pla.13 for ; Mon, 18 Apr 2022 23:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=2o+9+ttxTMbUox0oufQJ1Md0n9qMzaibk65fn3H8nu0=; b=Q54o7m9xWjnYBqzeN6GjnzxQeOUjpDfivGAzBNRDiiIAWNmc3ejzX1qRRDQwRRs3Yh LXm+jCcXuvWeH2qFXu45oVgPBTVjA+XD6MMIOFWztN/nsdAQBFGoMPEQ17/94etPTos7 FIT7eXhJ5eRo0b+MvLUQGWcw6ZaVQkix6gNk86FGXttskL2xOqzt37vW9lJAEuHG045K BJvrcROiIalDnQwYUKs8rGHgeG7Js5UrVo3nCMA/IleYZQkhP3w8RFMfEy9HmJ44YS7Z sz2bYOcptD6MJUt1sn5R0334bxvVmStMnKu9oXQyDLKEsjW47/qZVoXo6c+5ZwE1VGRN c2yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=2o+9+ttxTMbUox0oufQJ1Md0n9qMzaibk65fn3H8nu0=; b=3C2sNvX4oOev9+92t6GV94I7jxSJ6GB9XWHuSWglwBGHfPCa1OgncxpF7TGa8FfVxz LR32eDhBtUv+317N6dvmgZ0aYr2CUke78zRf/DhtqwxGgHLdz7ZCK99TqVHf0zI+XPcC QjxTAF5tL6xFAws+r+wFd5FhKAg/oxMTEZIW7aa6sd8s8CeOr7Zdxes/m/UQa607fjnT cTpa78JzABoabprbe8l5O48eoyuroh20AaAz6ejEkecc+k7dlc5PqiomtvAP6CTNslm/ YXCfxgMXqgzZDdpjMNYFx1oepWvJ7j4+X1HibOn+f7BkM4SbPp1XX+PDeCjmhouUOglm mRuA== X-Gm-Message-State: AOAM530MgNhRZjJoM9sDCMCle/gyZpPcF7eDkf1UtMEoh80gnpsg/0Xh tLdCvxjVWKnaIlabI4Df1C8u8BY6v+Y= X-Google-Smtp-Source: ABdhPJxyb3FmsWLgQqrhUeKnK1tWXDMw3rSUdbZQuckMXcJXZVAhIMqU09FQ5AnJ6GwTEg35SUY2yt83suM= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a63:bf0e:0:b0:386:361f:e97a with SMTP id v14-20020a63bf0e000000b00386361fe97amr13141907pgf.552.1650351464723; Mon, 18 Apr 2022 23:57:44 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:30 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-25-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 24/38] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235745_988255_FA4AD5D3 X-CRM114-Status: GOOD ( 17.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Track the baseline guest value for cptr_el2 in struct kvm_vcpu_arch for VHE. Use this value when setting cptr_el2 for the guest. Currently this value is unchanged, but the following patches will set trapping bits based on features supported for the guest. No functional change intended. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_arm.h | 16 ++++++++++++++++ arch/arm64/kvm/arm.c | 5 ++++- arch/arm64/kvm/hyp/vhe/switch.c | 14 ++------------ 3 files changed, 22 insertions(+), 13 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 1767ded83888..3f74fb16104e 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -288,6 +288,22 @@ GENMASK(19, 14) | \ BIT(11)) +/* + * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to + * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, + * except for some missing controls, such as TAM. + * In this case, CPTR_EL2.TAM has the same position with or without + * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM + * shift value for trapping the AMU accesses. + */ +#define CPTR_EL2_VHE_GUEST_DEFAULT (CPACR_EL1_TTA | CPTR_EL2_TAM) + +/* + * Bits that are copied from vcpu->arch.cptr_el2 to set cptr_el2 for + * guest with VHE. + */ +#define CPTR_EL2_VHE_GUEST_TRACKED_MASK (CPACR_EL1_TTA | CPTR_EL2_TAM) + /* Hyp Debug Configuration Register bits */ #define MDCR_EL2_E2TB_MASK (UL(0x3)) #define MDCR_EL2_E2TB_SHIFT (UL(24)) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index b4db368948cc..e80c059b41d5 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1123,7 +1123,10 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu, } vcpu_reset_hcr(vcpu); - vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT; + if (has_vhe()) + vcpu->arch.cptr_el2 = CPTR_EL2_VHE_GUEST_DEFAULT; + else + vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT; /* * Handle the "start in power-off" case. diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c index 262dfe03134d..066dc4629f02 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -40,20 +40,10 @@ static void __activate_traps(struct kvm_vcpu *vcpu) ___activate_traps(vcpu); val = read_sysreg(cpacr_el1); - val |= CPACR_EL1_TTA; + val &= ~CPTR_EL2_VHE_GUEST_TRACKED_MASK; + val |= (vcpu->arch.cptr_el2 & CPTR_EL2_VHE_GUEST_TRACKED_MASK); val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN); - /* - * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to - * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, - * except for some missing controls, such as TAM. - * In this case, CPTR_EL2.TAM has the same position with or without - * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM - * shift value for trapping the AMU accesses. - */ - - val |= CPTR_EL2_TAM; - if (update_fp_enabled(vcpu)) { if (vcpu_has_sve(vcpu)) val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN; From patchwork Tue Apr 19 06:55:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE728C433EF for ; Tue, 19 Apr 2022 07:14:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=rf3/U5DP++x0XxTRdln0q0KOXxEMxRPCLO9gWuRkiEs=; b=Yj1EUqrqycojBWXyRIP/IeVsOS afc9pSoo1xLMxxtq4SuTKiLJH41Y5NmAGAK7MlrZ5ZJzUH1cneAlL4bWyTffLCxQYduDbdD7pDEkb vSC5/8vheWmGEpNXe99SrHqDB1iicderCxC3bc7sWkInaydKd8fe0bpcZJGAyh5aF9+q9KuTb9B8L yzSEQFwy3FWgv5tVngbdQ4s4HW47m+mPFp9RdxKxxEiBo77S7pbcqrh/foTlSizWhYJ3bhA5kP9Pt a6Poq6CgcFjFAOhtAPm+HYaeuevO0ncPDq3XolghZfw8KnSh8JhQ/LBnLFRmMxLcQSVcPqLOzdgl+ Qxhfjw8g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi3B-001tXy-BQ; Tue, 19 Apr 2022 07:13:26 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngho4-001nfc-7R for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:51 +0000 Received: by mail-pl1-x649.google.com with SMTP id f6-20020a170902ab8600b0015895212d23so9244162plr.6 for ; Mon, 18 Apr 2022 23:57:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=7Pq8Qbz+GZ4aCCwOdPqx7ETMJ7/k84zERQoGVmKMUzo=; b=QNfVA35wFG6vpNs0B+FJaG2Jr6kdDJEcSIeBdn6dvuqTMajbbwxpwfkMCdT+sKXeUp oU3lbXu3dbwakRDJWAlNENKOGeRMwfbY+NbveA1eik6b+jyDSYM5ufu3vN1j6UmkCAUL yBXxITvbqA6RyJ0QdhO+9+JN9TIvKNApWgb6RroL/23xKGZPE8NtuXO1GviHy6km+f4C R/Rt2o16kJwISopgbNVjgGk2phPo+JBiR1S8Khug1JxR2xZVRFG2l13UoK1ZFep5CZJO QthN1tJsAmuY5+6ywiIefC81TvGQhFA5pQ3XAl435GpscoPaBz5CeYlP9CEbZoe/aFuv 9/1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=7Pq8Qbz+GZ4aCCwOdPqx7ETMJ7/k84zERQoGVmKMUzo=; b=Oq9pQYWBHvylNVoAVLccdMyQXWqCicT3WaTBGqBY6xARw5ybQyCLnydfrZRHXGm33U TnWsKtfwGaDQuZXS7tKVuVIMQAAoyDAYHxakzMuvmYTpKjc6kO3PNy/jwgOKiN8En1JO WTbs50ZE0rrjq7IL6CZNPksXUJQ7iwAPqyzdnZgVFMVVd5iCv3L1/KgdTvVyp4wBrB1r fHa0Gal0E9j72no/6YUI8z3iXg8Cu5EMumTntRsmVTCSpSA3ZfHZn21nQHO/kmZKyf2H 9SMcwyLBpOQdQDCx/mssCE/zdrY7C2ETA8gIcAM/scf3DwDWVpLEBZwlzWig5zqoB+VO QN1w== X-Gm-Message-State: AOAM531nuQWhpwLEODEcg0vaRoQzp7CsXIIPDZq0BwMJfbMqGSkzeDFF RE2bCvjA3ReSsDSykYUAZFhRFzvPLo8= X-Google-Smtp-Source: ABdhPJz3oa3JnqAQ9/dpcAbeHIo2jnXfGftCZIoVA3FwRIwngBUtuauyy2Rle18y+lJm7ZVHOsW6cwBm1qM= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90a:9105:b0:1d2:9e98:7e1e with SMTP id k5-20020a17090a910500b001d29e987e1emr277645pjo.0.1650351466369; Mon, 18 Apr 2022 23:57:46 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:31 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-26-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 25/38] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235748_374028_362DE1F2 X-CRM114-Status: GOOD ( 15.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Track the baseline guest value for mdcr_el2 in struct kvm_vcpu_arch. Use this value when setting mdcr_el2 for the guest. Currently this value is unchanged, but the following patches will set trapping bits based on features supported for the guest. No functional change intended. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_arm.h | 16 ++++++++++++++++ arch/arm64/kvm/arm.c | 1 + arch/arm64/kvm/debug.c | 13 ++++--------- 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 3f74fb16104e..90be933b5f08 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -333,6 +333,22 @@ BIT(18) | \ GENMASK(16, 15)) +/* + * The default value for the guest below also clears MDCR_EL2_E2PB_MASK + * and MDCR_EL2_E2TB_MASK to disable guest access to the profiling and + * trace buffers. + */ +#define MDCR_GUEST_FLAGS_DEFAULT \ + (MDCR_EL2_TPM | MDCR_EL2_TPMS | MDCR_EL2_TTRF | \ + MDCR_EL2_TPMCR | MDCR_EL2_TDRA | MDCR_EL2_TDOSA) + +/* Bits that are copied from vcpu->arch.mdcr_el2 to set mdcr_el2 for guest. */ +#define MDCR_GUEST_FLAGS_TRACKED_MASK \ + (MDCR_EL2_TPM | MDCR_EL2_TPMS | MDCR_EL2_TTRF | \ + MDCR_EL2_TPMCR | MDCR_EL2_TDRA | MDCR_EL2_TDOSA | \ + (MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)) + + /* For compatibility with fault code shared with 32-bit */ #define FSC_FAULT ESR_ELx_FSC_FAULT #define FSC_ACCESS ESR_ELx_FSC_ACCESS diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index e80c059b41d5..69189907579c 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1123,6 +1123,7 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu, } vcpu_reset_hcr(vcpu); + vcpu->arch.mdcr_el2 = MDCR_GUEST_FLAGS_DEFAULT; if (has_vhe()) vcpu->arch.cptr_el2 = CPTR_EL2_VHE_GUEST_DEFAULT; else diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index 6eb146d908f8..8e1243972804 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -84,16 +84,11 @@ void kvm_arm_init_debug(void) static void kvm_arm_setup_mdcr_el2(struct kvm_vcpu *vcpu) { /* - * This also clears MDCR_EL2_E2PB_MASK and MDCR_EL2_E2TB_MASK - * to disable guest access to the profiling and trace buffers + * Keep the vcpu->arch.mdcr_el2 bits that are specified by + * MDCR_GUEST_FLAGS_TRACKED_MASK. */ - vcpu->arch.mdcr_el2 = __this_cpu_read(mdcr_el2) & MDCR_EL2_HPMN_MASK; - vcpu->arch.mdcr_el2 |= (MDCR_EL2_TPM | - MDCR_EL2_TPMS | - MDCR_EL2_TTRF | - MDCR_EL2_TPMCR | - MDCR_EL2_TDRA | - MDCR_EL2_TDOSA); + vcpu->arch.mdcr_el2 &= MDCR_GUEST_FLAGS_TRACKED_MASK; + vcpu->arch.mdcr_el2 |= __this_cpu_read(mdcr_el2) & MDCR_EL2_HPMN_MASK; /* Is the VM being debugged by userspace? */ if (vcpu->guest_debug) From patchwork Tue Apr 19 06:55:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E87BC433EF for ; Tue, 19 Apr 2022 07:15:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=cJCVZli7ubWtfHsw8ylnb3yFN7feVC63CtY6IFPwguY=; b=SoZnC388mylKuGiZpAnVO1tMkZ EkyUHvLjBuojwEQ1tUUhB16kVcn+5EEPap8RQr5+pLDTqbyG+UKTZ1B7vYH1xLqYuoTWKhLELOaRe QmruxME13WGkJZalykvOlba8gQnOO8ZyaBS3j7DRN3+Pqr2nzgxpxLzdikgX9YkBUGTltDzImSNj8 Hy7ooAHy8UExKQxGZmb1ndBVXWNt+1nm1rv62q/0ihqiz/0w70zsjaUR+5YwWoMAgLCOw4eK0/4Zo Yyr/bc9PSabUTH2hm7P5MtoXOyvLIgqjQcPswbxdMwQHhGVsNoRMMOCbdxcSu0WH6E41DlDlxg+m5 cI4i/qZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi4J-001txr-GN; Tue, 19 Apr 2022 07:14:36 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngho5-001ngC-HP for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:52 +0000 Received: by mail-pj1-x104a.google.com with SMTP id f2-20020a17090a120200b001cbae0449edso10136548pja.4 for ; Mon, 18 Apr 2022 23:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=B1I2hIjHdTMX5JOJBkL6j3t0rzu4sj1sIMHdlZhAORQ=; b=sLdKpYgmWisFvw0h7w4vqAUGy5Ze3pz+9xltI0cwBnIXOZCk8SJ4JMMtSX69/qpU4w MQ1CbtoOKdWZBT5iEP7QAjdBxJXIU+2i1+xuvL2Bxgwqw7IsamVZ81oLl4ixcYtFI59O xN3n/t1sCzaDNHDXkKLETaKyxQQqRxL8PSHH6lu2uuKBr3DSKcjRwRvtXAZnAWAxd0M5 jqUNRAdecFmD+UoygrYyhbdhhrPAiXaiQaxKhtP7eaexV5wKabO4nr+ozUPwa9hbAXsQ G+/C0K2bNs1fpPEWvTbwEN3UHMHKe8wq5dYQRzd/kEhfhGeK23Bic1Pw8G1TlOe2ExO1 2POw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=B1I2hIjHdTMX5JOJBkL6j3t0rzu4sj1sIMHdlZhAORQ=; b=D5LuJCvgpf7v6RiwiE189bQ0KGJDfC5ZXl5Dr7Wu5947xVWRWEzFZGF5Gp3wwtXedJ 3Y7joQuAzuA1/oNzuJlwvL7yaVm1Phip095ZK867qNhZR1s75/jT7zMTOsTRfgyrptxr mqtILtmcvtaMAlDRbKyUAGfkiJxAM3t+jZcKH/sA9ggd4kyhCir76z1wVmQoKGkQXb2E P24sazCJGYSr89u6Oc9BHMKZyyVCrJVxUpvY0tOyNjHK/CqIk4YWT6mTeOnFXDDQSEYW dWTltP3OLLttNmmLM2CHIm9w7pMkjtMtIIq7hLiHPH++2pjFz2ViY5iGRhnZOO72ybbE Yq2A== X-Gm-Message-State: AOAM532ktYE3Ft6ORIdUJqnoyoO9gywtkXvcImF73ZIeIyWyc8wkqhj7 HoGSgN8zfxeRc5FXejT2ceVGkgSA1Xc= X-Google-Smtp-Source: ABdhPJzN1iwm3YJb0ZtY2RQlAXZkF8VXrNv44zhCAriIwP97RNc+KwflV5KlNxeryAwEWROW0FPqTsPglMU= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a62:8384:0:b0:507:3460:6395 with SMTP id h126-20020a628384000000b0050734606395mr16169854pfe.81.1650351468194; Mon, 18 Apr 2022 23:57:48 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:32 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-27-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 26/38] KVM: arm64: Introduce framework to trap disabled features From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235749_653797_D9127666 X-CRM114-Status: GOOD ( 31.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When a CPU feature that is supported on the host is not exposed to its guest, emulating a real CPU's behavior (by trapping or disabling guest's using the feature) is generally a desirable behavior (when it's possible without any or little side effect). Introduce feature_config_ctrl structure, which manages feature information to program configuration register to trap or disable the feature when the feature is not exposed to the guest, and functions that uses the structure to activate the vcpu's trapping the feature. Those codes don't update trap configuration registers themselves (HCR_EL2, etc) but values for the registers in kvm_vcpu_arch at the first KVM_RUN. At present, no feature has feature_config_ctrl yet and the following patches will add the feature_config_ctrl for some features. Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/arm.c | 13 ++-- arch/arm64/kvm/sys_regs.c | 111 ++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index b85af83b4542..92785b33df0f 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -790,6 +790,7 @@ void set_default_id_regs(struct kvm *kvm); int kvm_set_id_reg_feature(struct kvm *kvm, u32 id, u8 field_shift, u8 fval); void kvm_vcpu_breakpoint_config(struct kvm_vcpu *vcpu); int kvm_id_regs_check_frac_fields(const struct kvm_vcpu *vcpu); +void kvm_vcpu_init_traps(struct kvm_vcpu *vcpu); /* Guest/host FPSIMD coordination helpers */ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 69189907579c..bcccf3876fcf 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -556,13 +556,16 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) static_branch_inc(&userspace_irqchip_in_use); } - /* - * Initialize traps for protected VMs. - * NOTE: Move to run in EL2 directly, rather than via a hypercall, once - * the code is in place for first run initialization at EL2. - */ + /* Initialize traps for the guest. */ if (kvm_vm_is_protected(kvm)) + /* + * NOTE: Move to run in EL2 directly, rather than via a + * hypercall, once the code is in place for first run + * initialization at EL2. + */ kvm_call_hyp_nvhe(__pkvm_vcpu_init_traps, vcpu); + else + kvm_vcpu_init_traps(vcpu); mutex_lock(&kvm->lock); set_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &kvm->arch.flags); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a71c52aee34e..7fe44dec11fd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -299,6 +299,27 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR2_GPA3_SHIFT) >= \ ID_AA64ISAR2_GPA3_ARCHITECTED) +/* + * Feature information to program configuration register to trap or disable + * guest's using a feature when the feature is not exposed to the guest. + */ +struct feature_config_ctrl { + /* ID register/field for the feature */ + u32 ftr_reg; /* ID register */ + bool ftr_signed; /* Is the feature field signed ? */ + u8 ftr_shift; /* Field of ID register for the feature */ + s8 ftr_min; /* Min value that indicate the feature */ + + /* + * Function to check trapping is needed. This is used when the above + * fields are not enough to determine if trapping is needed. + */ + bool (*ftr_need_trap)(struct kvm_vcpu *vcpu); + + /* Function to activate trapping the feature. */ + void (*trap_activate)(struct kvm_vcpu *vcpu); +}; + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -321,6 +342,9 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, struct id_reg_desc { const struct sys_reg_desc reg_desc; + /* Sanitized system value */ + u64 sys_val; + /* * Limit value of the register for a vcpu. The value is the sanitized * system value with bits set/cleared for unsupported features for the @@ -376,6 +400,9 @@ struct id_reg_desc { * UNSIGNED+LOWER_SAFE entries during KVM's initialization. */ struct arm64_ftr_bits ftr_bits[FTR_FIELDS_NUM]; + + /* Information to trap features that are disabled for the guest */ + const struct feature_config_ctrl *(*trap_features)[]; }; static inline struct id_reg_desc *sys_to_id_desc(const struct sys_reg_desc *r) @@ -393,6 +420,7 @@ static void id_reg_desc_init(struct id_reg_desc *id_reg) return; val = read_sanitised_ftr_reg(id); + id_reg->sys_val = val; id_reg->vcpu_limit_val = val; id_reg_desc_init_ftr(id_reg); @@ -908,6 +936,24 @@ static int validate_id_reg(struct kvm_vcpu *vcpu, return err; } +static inline bool feature_avail(const struct feature_config_ctrl *ctrl, + u64 id_val) +{ + int field_val = cpuid_feature_extract_field(id_val, + ctrl->ftr_shift, ctrl->ftr_signed); + + return (field_val >= ctrl->ftr_min); +} + +static inline bool vcpu_feature_is_available(struct kvm_vcpu *vcpu, + const struct feature_config_ctrl *ctrl) +{ + u64 val; + + val = read_id_reg_with_encoding(vcpu, ctrl->ftr_reg); + return feature_avail(ctrl, val); +} + /* * ARMv8.1 mandates at least a trivial LORegion implementation, where all the * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 @@ -2387,6 +2433,46 @@ static bool access_raz_id_reg(struct kvm_vcpu *vcpu, return __access_id_reg(vcpu, p, r, true); } +static void id_reg_features_trap_activate(struct kvm_vcpu *vcpu, + const struct id_reg_desc *id_reg) +{ + u64 val; + int i = 0; + const struct feature_config_ctrl **ctrlp_array, *ctrl; + + if (!id_reg->trap_features) + /* No information to trap a feature */ + return; + + val = __read_id_reg(vcpu, id_reg); + if (val == id_reg->sys_val) + /* No feature needs to be trapped (no feature is disabled). */ + return; + + ctrlp_array = *id_reg->trap_features; + while ((ctrl = ctrlp_array[i++]) != NULL) { + if (WARN_ON_ONCE(!ctrl->trap_activate)) + /* Shouldn't happen */ + continue; + + if (ctrl->ftr_need_trap && ctrl->ftr_need_trap(vcpu)) { + ctrl->trap_activate(vcpu); + continue; + } + + if (!feature_avail(ctrl, id_reg->sys_val)) + /* The feature is not supported on the host. */ + continue; + + if (feature_avail(ctrl, val)) + /* The feature is enabled for the guest. */ + continue; + + /* The feature is supported but disabled. */ + ctrl->trap_activate(vcpu); + } +} + /* Visibility overrides for SVE-specific control registers */ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) @@ -4487,6 +4573,31 @@ static void kvm_reset_id_regs(struct kvm_vcpu *vcpu) } } +/* + * This function activates vcpu's trapping of features that are included in + * trap_features[] of id_reg_desc if the features are supported on the + * host, but are hidden from the guest (i.e. values of ID registers for + * the guest are modified to not show the features' availability). + * This function just updates values for trap configuration registers (e.g. + * HCR_EL2, etc) in kvm_vcpu_arch, which will be restored before switching + * to the guest, but doesn't update the registers themselves. + * This function should be called once at the first KVM_RUN (ID registers + * are immutable after the first KVM_RUN). + */ +void kvm_vcpu_init_traps(struct kvm_vcpu *vcpu) +{ + int i; + struct id_reg_desc *idr; + + for (i = 0; i < ARRAY_SIZE(id_reg_desc_table); i++) { + idr = (struct id_reg_desc *)id_reg_desc_table[i]; + if (!idr) + continue; + + id_reg_features_trap_activate(vcpu, idr); + } +} + #if IS_ENABLED(CONFIG_KVM_KUNIT_TEST) #include "sys_regs_test.c" #endif From patchwork Tue Apr 19 06:55:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB3B1C433EF for ; Tue, 19 Apr 2022 07:17:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=bbPhSfYDP/KKE8doPeEECrA8dVV9CIOq2qZc7pq9wsI=; b=RdiZBv5+/cwnbHybKZUlzeBuku RdY0+HTGe0sOMHu2HSAgpj78IKtV9XGBrsgqxOefjIOlE1ZS5ePLceoCyDk8ljq24U60vOLLV7RjS uZ5faBY/3JEPYK6p1suqbBIyA/Y6ZjltqupAA75y7Ub6usDRGoeNcOW3TobluDYh5gXgG8ktnYKyK FolQAG9q0jQlYDja4uxvp9mhTXddbEu0q965wjNJtpZsKptb6Z5dwm9rFodBrmDwwS3/JnRW4bZe7 6Mk49HogqI0ypeUxd17rZN7pEmL5o9PqhLNowRo4TT2K/ZUF3A54cTtAS3rWp24Kdga86Sk+tYWqc A3TKkTvQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi69-001ub3-Nu; Tue, 19 Apr 2022 07:16:30 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngho7-001nhD-8t for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:53 +0000 Received: by mail-pj1-x1049.google.com with SMTP id r12-20020a17090a690c00b001cb9bce2284so10128609pjj.8 for ; Mon, 18 Apr 2022 23:57:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=xydmrQbn6xBF8/ePfVL7th+l3rERvkG3uvSek2g29PM=; b=B3aAhbDXLtzCKoc11fDKloW896IaGDdEbmBBz/bkUK5ainOaSynxr95k4hqmcFDIOm XSX5BxR7DJS4pmGIm1pdkb9wUUT09tkOPCwpv3fW8NiTBWCkhm65qgJiC3a4BPQ+Ri0M +TPtopVHEVTAWl0UHuYBlZ/vjq4jdcvyIhVhZ1m6yXzS391nw+F+oBa+8z+Dwc0qjuBQ x0v2ScmIGPiHC/L7Gsw0wddnIzIPzFOMEvq+10S1VQ5N8DeDpwYRbaXHRXSTMQh8JkAm ye6N97rv5CM+hd43K7Hqn3bZZrNwsgFp+CA/u0fL/WatKT3gaILa4hshuBhr+8b4j7iL ZW1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=xydmrQbn6xBF8/ePfVL7th+l3rERvkG3uvSek2g29PM=; b=E7QsArTSZZG1M476G8xgoWWPVzuXleLOHstkWJa1m19LYl7CKwoqKpCad6Atys0P7S RWhmu3+l+u2/NKOF7vdlL0a+0rL9D0JNbAGUHwjsDNGMVSPxr/qklGRW+njWWGONkfrx UE/Xo+LW6Omdb92/FA92ghsaN9ze3bmnUiJZqcV0m1xJKdQa3KOF2CI/D9mT/glwUe++ MEIuz/jQfk0X4WMOZnPhQ+P6f7fmNt5vuzr35EiWkpbzOBEhGpDz3hk+Gv6coI4KuGXt /lQKs1AL/dEB9jsd1dEkPpT8FInHXCQR2NN/Utg8ClHCRMh+D+ICfTXyXsE6pBz6GyX4 PSJg== X-Gm-Message-State: AOAM532YTP+sp844JwXAUJL/LHFItMjAgztp2OvY8jberlwb2YEQHUyH DWYkPFP3ECyB5gE2qCA79YpOn/b6UzA= X-Google-Smtp-Source: ABdhPJymWpo78icljcdDrBVhbQitXud9ofh1LnhHGu4eZMLV5WZFlPKgYwB0b6QD2F2Vs2FOm+A56WLFg34= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90a:dd45:b0:1bc:9466:9b64 with SMTP id u5-20020a17090add4500b001bc94669b64mr22322996pjv.23.1650351469934; Mon, 18 Apr 2022 23:57:49 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:33 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-28-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 27/38] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235751_374631_D319D581 X-CRM114-Status: GOOD ( 17.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add feature_config_ctrl for RAS and AMU, which are indicated in ID_AA64PFR0_EL1, to program configuration registers to trap guest's using those features when they are not exposed to the guest. Introduce trap_ras_regs() to change a behavior of guest's access to the registers, which is currently raz/wi, depending on the feature's availability for the guest (and inject undefined instruction exception when guest's RAS register access are trapped and RAS is not exposed to the guest). In order to keep the current visibility of the RAS registers from userspace (always visible), a visibility function for RAS registers is not added. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 92 +++++++++++++++++++++++++++++++++++---- 1 file changed, 83 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 7fe44dec11fd..fecd54a58d34 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -320,6 +320,63 @@ struct feature_config_ctrl { void (*trap_activate)(struct kvm_vcpu *vcpu); }; +enum vcpu_config_reg { + VCPU_HCR_EL2 = 1, + VCPU_MDCR_EL2, + VCPU_CPTR_EL2, +}; + +static void feature_trap_activate(struct kvm_vcpu *vcpu, + enum vcpu_config_reg cfg_reg, + u64 cfg_set, u64 cfg_clear) +{ + u64 *reg_ptr, reg_val; + + switch (cfg_reg) { + case VCPU_HCR_EL2: + reg_ptr = &vcpu->arch.hcr_el2; + break; + case VCPU_MDCR_EL2: + reg_ptr = &vcpu->arch.mdcr_el2; + break; + case VCPU_CPTR_EL2: + reg_ptr = &vcpu->arch.cptr_el2; + break; + } + + /* Clear/Set fields that are indicated by cfg_clear/cfg_set. */ + reg_val = (*reg_ptr & ~cfg_clear); + reg_val |= cfg_set; + *reg_ptr = reg_val; +} + +static void feature_ras_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_HCR_EL2, HCR_TERR | HCR_TEA, HCR_FIEN); +} + +static void feature_amu_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_CPTR_EL2, CPTR_EL2_TAM, 0); +} + +/* For ID_AA64PFR0_EL1 */ +static struct feature_config_ctrl ftr_ctrl_ras = { + .ftr_reg = SYS_ID_AA64PFR0_EL1, + .ftr_shift = ID_AA64PFR0_RAS_SHIFT, + .ftr_min = ID_AA64PFR0_RAS_V1, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_ras_trap_activate, +}; + +static struct feature_config_ctrl ftr_ctrl_amu = { + .ftr_reg = SYS_ID_AA64PFR0_EL1, + .ftr_shift = ID_AA64PFR0_AMU_SHIFT, + .ftr_min = ID_AA64PFR0_AMU, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_amu_trap_activate, +}; + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -954,6 +1011,18 @@ static inline bool vcpu_feature_is_available(struct kvm_vcpu *vcpu, return feature_avail(ctrl, val); } +static bool trap_ras_regs(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (!vcpu_feature_is_available(vcpu, &ftr_ctrl_ras)) { + kvm_inject_undefined(vcpu); + return false; + } + + return trap_raz_wi(vcpu, p, r); +} + /* * ARMv8.1 mandates at least a trivial LORegion implementation, where all the * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 @@ -2786,14 +2855,14 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, - { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, - { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, - { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, - { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, + { SYS_DESC(SYS_ERRIDR_EL1), trap_ras_regs }, + { SYS_DESC(SYS_ERRSELR_EL1), trap_ras_regs }, + { SYS_DESC(SYS_ERXFR_EL1), trap_ras_regs }, + { SYS_DESC(SYS_ERXCTLR_EL1), trap_ras_regs }, + { SYS_DESC(SYS_ERXSTATUS_EL1), trap_ras_regs }, + { SYS_DESC(SYS_ERXADDR_EL1), trap_ras_regs }, + { SYS_DESC(SYS_ERXMISC0_EL1), trap_ras_regs }, + { SYS_DESC(SYS_ERXMISC1_EL1), trap_ras_regs }, MTE_REG(TFSR_EL1), MTE_REG(TFSRE0_EL1), @@ -4230,7 +4299,12 @@ static struct id_reg_desc id_aa64pfr0_el1_desc = { .ftr_bits = { S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, ID_AA64PFR0_FP_NI), S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, ID_AA64PFR0_ASIMD_NI), - } + }, + .trap_features = &(const struct feature_config_ctrl *[]) { + &ftr_ctrl_ras, + &ftr_ctrl_amu, + NULL, + }, }; static struct id_reg_desc id_aa64pfr1_el1_desc = { From patchwork Tue Apr 19 06:55:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD9D7C433F5 for ; Tue, 19 Apr 2022 07:18:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=7sw8TwWh9J6bR1+v2QCYk+NKu+d97kWQ5z58sCLAeMI=; b=YX7nDa+l8vRZIxTxJ+SNPCwSgM MjglXLxnDS/poK8WWvHXw9fjW5Xe2IXHfT15fo0g1lRaray/XNNlkY8uHAqkEgg1yT06pSsBEW9w0 012QUh5Kk9f7tlSx5sZRTQzt5ZRPfE8QrEjLDYrsnypN4a7p+iBQhE6RIEBeP3gHULuPlVytTXchB /qrSukcT+gD0lh0fCxtq57JECkK6FuqxKeyZdakHtkm23U9U/zN6EjSApselcnMArfyC/NixGORzV iij0bU6ziKhwoSBOQw6LevQobOfYGgegn1/VXOWwyro2n1mOKb8ahAwb6Hg+gsf3dI1/Jxqx30gAE EpUwcwNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi6t-001us3-A0; Tue, 19 Apr 2022 07:17:16 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngho9-001niF-1E for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:54 +0000 Received: by mail-pj1-x104a.google.com with SMTP id r15-20020a17090a4dcf00b001cb7ea0b0bdso1046969pjl.1 for ; Mon, 18 Apr 2022 23:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=11aokqGJX88zjYco/n0ZubDfebB61Zyyzannu13jVUU=; b=KGkjLi1nc3eXEFUtTXU9CrYnMm5oE1zb1JyJJ5B7usLojN2sR4jMVUo4tdKam79pra OVVDdODyp0s3nG2ZJo8xAbdCAAdfINz0DvmkTYgcDoJPyjrFRzEMbWEhr3S17VgMcZzD nM3JFqyi9usgPOH9nh6yHH3K9EhDv+VHrkC9rBBlvfOu2MszL4Hs+DDC22Em2O6ZKNxl 5AeVCwzg50biwYCMn8UmZJ1+S+oPSbmtdfJ4IcoWZFIIysV0uXT2l+BZurMipMNhaudj 6H2envE5Qpe3dAMXTa3BuELSOXXVwTJH4rpI5ANhGr44gOvC13Npdua3r4pKU8cmUmQJ 8T2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=11aokqGJX88zjYco/n0ZubDfebB61Zyyzannu13jVUU=; b=Wm4DG29dpdIkZ4j+z1EysvWuy3O7AR7LRsxF/ou1g8f94pmiXydf/ukgEI9H0zOnq0 S2fthQt5kUYveVDsnj/4SuJTFl3nliDTEO73SVkig9My/ck2tUY/qjDS/C8g2flBkH1P 6X/pHp4zadQUbXf+5PdVDpDqPF0WxLZeRd/+19O6dg0JcnU88zInEt7TTWmDiLyDrga7 7G8tL3RtqS0FUblUVfSduVQnagYQ0XZzDX9CbjbXK/0J8XdUwO5RuXG3rnxiGfkCfslo bH5I9LlCu56HgAeJkaH7swXORd8DV7Ev2/NO+OTTOHIRPFIql/Xx9MrQGf0WZAFe2poO 8pBA== X-Gm-Message-State: AOAM533Oznr34s+tS+k4kF4X+/C9Ul9wlyZNdN5Ia6CWfEL5RGL6gMPS 26q+3O75EbaFbESBPapBwEFgnZnTQj4= X-Google-Smtp-Source: ABdhPJxTNMo4W/KfFAQ3BdCNc/v2d2neST1XZcUkDoxRPAerssfdLoDu8lxxEk0L7o4yB7dQku5s92k37v0= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:902:c792:b0:158:ba0c:cf6d with SMTP id w18-20020a170902c79200b00158ba0ccf6dmr14555949pla.131.1650351471625; Mon, 18 Apr 2022 23:57:51 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:34 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-29-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 28/38] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235753_121718_956F2E03 X-CRM114-Status: GOOD ( 11.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add feature_config_ctrl for MTE, which is indicated in ID_AA64PFR1_EL1, to program configuration register to trap the guest's using the feature when it is not exposed to the guest. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index fecd54a58d34..10f366957ce9 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -360,6 +360,11 @@ static void feature_amu_trap_activate(struct kvm_vcpu *vcpu) feature_trap_activate(vcpu, VCPU_CPTR_EL2, CPTR_EL2_TAM, 0); } +static void feature_mte_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_HCR_EL2, HCR_TID5, HCR_DCT | HCR_ATA); +} + /* For ID_AA64PFR0_EL1 */ static struct feature_config_ctrl ftr_ctrl_ras = { .ftr_reg = SYS_ID_AA64PFR0_EL1, @@ -377,6 +382,15 @@ static struct feature_config_ctrl ftr_ctrl_amu = { .trap_activate = feature_amu_trap_activate, }; +/* For ID_AA64PFR1_EL1 */ +static struct feature_config_ctrl ftr_ctrl_mte = { + .ftr_reg = SYS_ID_AA64PFR1_EL1, + .ftr_shift = ID_AA64PFR1_MTE_SHIFT, + .ftr_min = ID_AA64PFR1_MTE_EL0, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_mte_trap_activate, +}; + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -4312,6 +4326,10 @@ static struct id_reg_desc id_aa64pfr1_el1_desc = { .init = init_id_aa64pfr1_el1_desc, .validate = validate_id_aa64pfr1_el1, .vcpu_mask = vcpu_mask_id_aa64pfr1_el1, + .trap_features = &(const struct feature_config_ctrl *[]) { + &ftr_ctrl_mte, + NULL, + }, }; static struct id_reg_desc id_aa64isar0_el1_desc = { From patchwork Tue Apr 19 06:55:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3856C433F5 for ; Tue, 19 Apr 2022 07:19:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=L5v6c9flEUeiVthTGbs0+rnJWQFv7VfisEbIThXGcaI=; b=L8M7pJpHTyRhaMNAvedhBMcQrh QMapaycrkuXNHWDMQFL7xYyEda9LNnw9Tdiv8Gp3IvNNwkIlAfn9jCOnbt19RKdfgwKKiEUtxjXU+ YKAc61DWAQbk1V+eEQtyKITM/PC77LqhO6VzwnIF2XqOW/2pJ7F4QJrMi5N0euBOmljLOCYVQYZwW rZVon6MEGvyf7akpgmaMRWSA8KJZkdkhMvQL7IlJorXkEPa/qKab3Jwws+ZT2zaZ/S1H8lM7s1P0K uPMFsZqnkS5sYlVSoFTrCIAHjN4urckC7o38h1sXfIoTy1rmIYxncqlqz3Tg7kNQwb5m30w99IeoE 71b0CRMQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi7t-001vEE-5N; Tue, 19 Apr 2022 07:18:17 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoA-001njC-76 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:56 +0000 Received: by mail-pj1-x104a.google.com with SMTP id v9-20020a17090a7c0900b001cb45f88cdcso10161949pjf.0 for ; Mon, 18 Apr 2022 23:57:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=6xPTbO2+lphyYIiZZ7nszYhBXnFaCQQSE3MHungiG3k=; b=It96CsYEpNqOcLwAVOb9ZqqedaZuQTEj/TXyGKgn91DGN1sbhJ2YzVPkGyHNPtG0Nv aNAZtDspBnw31IkOSfsaQRnyOa1+vukEVhRRJuyFETlx+Xga9HV7nASuyNJsYJd6eFZO Z24gMEtrO+U5npwqvSLXDznZlYHSyFsmBAFIFZoEMTLt46ZN4DzUxj55xgjRqSxJ6hm5 euhJuYDyTiUwy8G6uL3tc5CKsuhmecf0ulBOQZbgyj0Zgb0i2TxRTfji88zGyTtAvcIk KyaEUd4bs969tANr4AJvZOIcTWBIOCB3bZmNr5U2nuMhhVOvPHgX0HvX8PSt923l0aer fGuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=6xPTbO2+lphyYIiZZ7nszYhBXnFaCQQSE3MHungiG3k=; b=ndEaUqJjJkeG2FBHJ2q3hxSh3smnvq4qbLZ221OoNispQYIgSbYZ1etOSphslFUMIv W2OgcFX+XRDKJ1fdPMb+JhrVOv+jJErhmqngs41UQf2Yp8yOtwLXDuNRl892UaiHZH8q 3TNvz7wqdtpkPjFW8/PLE3p05Yp3AJ5hUV01szGH0GLpgRnOu6ajy8Gv53+V1icJeFTq 7ovdx/e0r4uPSzEF7cHxAx/ebIJucfRJ+YFxC03ouuy56FfEF1ezMjPR1kg7671jnZu4 1rCMgkFgmrETbiCkiItXlnAfrI8V1LZxiNpgqyv+Bf4sajW/rywVJFyzcTbsmoslcRIF h+gA== X-Gm-Message-State: AOAM533RNnqZ+KGGnAx0mfM2T4i7nsSq+cyNxwkYlFlN7tBsMJgKh2Bm NcLgexv4KATrnvsGP/kSiVRce63cPCI= X-Google-Smtp-Source: ABdhPJy3D0n5a+z17jnE0L3OXrhl0HuwRJ6F1nYYDplfhvW3GN0Q2u9zJiIaYhrSBbwPfSrzLKaQHN+kyIk= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:1490:b0:4fb:1544:bc60 with SMTP id v16-20020a056a00149000b004fb1544bc60mr16144093pfu.73.1650351472945; Mon, 18 Apr 2022 23:57:52 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:35 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-30-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 29/38] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1 From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235754_329114_250AF7B0 X-CRM114-Status: GOOD ( 11.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add feature_config_ctrl for PMUv3, PMS and TraceFilt, which are indicated in ID_AA64DFR0_EL1, to program configuration registers to trap guest's using those features when they are not exposed to the guest. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 64 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 10f366957ce9..a09c910198d6 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -365,6 +365,30 @@ static void feature_mte_trap_activate(struct kvm_vcpu *vcpu) feature_trap_activate(vcpu, VCPU_HCR_EL2, HCR_TID5, HCR_DCT | HCR_ATA); } +static void feature_trace_trap_activate(struct kvm_vcpu *vcpu) +{ + if (has_vhe()) + feature_trap_activate(vcpu, VCPU_CPTR_EL2, CPACR_EL1_TTA, 0); + else + feature_trap_activate(vcpu, VCPU_CPTR_EL2, CPTR_EL2_TTA, 0); +} + +static void feature_pmuv3_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_MDCR_EL2, MDCR_EL2_TPM, 0); +} + +static void feature_pms_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_MDCR_EL2, MDCR_EL2_TPMS, + MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT); +} + +static void feature_tracefilt_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_MDCR_EL2, MDCR_EL2_TTRF, 0); +} + /* For ID_AA64PFR0_EL1 */ static struct feature_config_ctrl ftr_ctrl_ras = { .ftr_reg = SYS_ID_AA64PFR0_EL1, @@ -391,6 +415,39 @@ static struct feature_config_ctrl ftr_ctrl_mte = { .trap_activate = feature_mte_trap_activate, }; +/* For ID_AA64DFR0_EL1 */ +static struct feature_config_ctrl ftr_ctrl_trace = { + .ftr_reg = SYS_ID_AA64DFR0_EL1, + .ftr_shift = ID_AA64DFR0_TRACEVER_SHIFT, + .ftr_min = 1, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_trace_trap_activate, +}; + +static struct feature_config_ctrl ftr_ctrl_pmuv3 = { + .ftr_reg = SYS_ID_AA64DFR0_EL1, + .ftr_shift = ID_AA64DFR0_PMUVER_SHIFT, + .ftr_min = ID_AA64DFR0_PMUVER_8_0, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_pmuv3_trap_activate, +}; + +static struct feature_config_ctrl ftr_ctrl_pms = { + .ftr_reg = SYS_ID_AA64DFR0_EL1, + .ftr_shift = ID_AA64DFR0_PMSVER_SHIFT, + .ftr_min = ID_AA64DFR0_PMSVER_8_2, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_pms_trap_activate, +}; + +static struct feature_config_ctrl ftr_ctrl_tracefilt = { + .ftr_reg = SYS_ID_AA64DFR0_EL1, + .ftr_shift = ID_AA64DFR0_TRACE_FILT_SHIFT, + .ftr_min = 1, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_tracefilt_trap_activate, +}; + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -4389,6 +4446,13 @@ static struct id_reg_desc id_aa64dfr0_el1_desc = { .ftr_bits = { S_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 0xf), }, + .trap_features = &(const struct feature_config_ctrl *[]) { + &ftr_ctrl_trace, + &ftr_ctrl_pmuv3, + &ftr_ctrl_pms, + &ftr_ctrl_tracefilt, + NULL, + }, }; static struct id_reg_desc id_dfr0_el1_desc = { From patchwork Tue Apr 19 06:55:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13D88C433EF for ; Tue, 19 Apr 2022 07:20:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=9cLnF93Reg3wjk+/U1gqOYKfKmW7VtJMbabl/01qhBA=; b=HGvjmZa4arpDBCJca0oqmSBd0I fd53XAPAyrry8C+Yjt2Bp1QhL5JXnV/wLt6XAdqFcfocFnPqSOKU/miKyqafNtJ8A0pl1jf1ZScVO TlKtHvuCQ1F4SxKtMuItG5czzKvF3S8bcEVspH9XSh9eCPk9zAs0y8+cytnGGPF+XO9lX6NEkCKWf RqT79yAwGz9YppnI9sDRClDfbJ3S1TxlrAYoHFeZY1iEvCr/2LaXAQp/PRa85Aj2ZKc2XrVFyGkiv jVgHa94Jc+gPUytpuRr3nfIUfjGndGToqIMvzbHl50psdD3rGJUd41S1n7/3tc2E3NXpdXfdvSLvq VlAfdgfQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi8p-001vb1-BW; Tue, 19 Apr 2022 07:19:15 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoB-001nk1-St for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:57 +0000 Received: by mail-pl1-x649.google.com with SMTP id k2-20020a170902ba8200b0015613b12004so9241831pls.22 for ; Mon, 18 Apr 2022 23:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=FGn+d1/fzCMoysQ55Sv7panNzkYFCREIVH43wm5V/xU=; b=nbP6H9eLPB2KRUszqjTjx8oXBwErZ7lIfZHOLtdkJWYF4Y8A1N/NpiaKp37xuFx1Ud XFYUj8R3HIK/2yg2tTUzGPz29aiDAuuxLbJAZvX5j0DVwEfJ9DmZqNZuYwG854scSWEU KCgssLZ9jYfOjk0MY1SCFqfXsElf5DH70nSmWeFUNB3+TPODZGz0TwDe1XiI63R4XGqW dqIprL+Vy62aXPKqODFGp8794SpD9CXf3AgMD2as9uU2afjv9U086jbrTKkU7e+iSTca ZNe8BSjcDOQEwLGE2Riw8tDL09c0xKw6YVhUNpoL+BtOcOk72Wj/EgA9R6I8puV0x1Po kLNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=FGn+d1/fzCMoysQ55Sv7panNzkYFCREIVH43wm5V/xU=; b=n7nTJ2rF6VMjnSVSepYRCzc/MxaIQfQTY6wdtanCd6HXcVHzRKevMmnG1Cu8qWRUXg JKdUzf/m+jPaaIQjnLw1RkRwZxG9UdA59u4I3r3QCQITHHLx+cECPfiDLNY5sK69H7CP H0P9cZgeHorgQND+ujYSnr64OmAIgfMYxzWiabB1lZ41xYc+krQmIZIR5uP8MriLaXvO G+cfJqBSj8D6XqdPP/oqExcM1bQpprt0MnAkHo7QlJxllQ2DhHvDjRbXMfZXeaZjY3zY fYSOS5M3NIRQExL4n+Q3xTnuPrX5hG+jvyHWNXYeRnCBozBtrju8RI+50EbpW786GZZt qzVA== X-Gm-Message-State: AOAM533RJjLtdta1Our+/hA5QY4kucc8PxwzNeSaACueptzbJc5nSj8C FDN0eeBlHtZKnolzFtHIDa3ws/wvsq8= X-Google-Smtp-Source: ABdhPJxpYOikvgNJvHHbbpFpSUMKs8Qh1bxceFJTHg4QBYMxz42FIi3eaMxP3/8CTDdPHB7uL9Sp54w8dR0= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90b:3b86:b0:1d2:66cf:569b with SMTP id pc6-20020a17090b3b8600b001d266cf569bmr14889978pjb.206.1650351474413; Mon, 18 Apr 2022 23:57:54 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:36 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-31-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 30/38] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235755_984229_5BCB4AB8 X-CRM114-Status: GOOD ( 14.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add feature_config_ctrl for LORegions, which is indicated in ID_AA64MMFR1_EL1, to program configuration register to trap guest's using the feature when it is not exposed to the guest. Change trap_loregion() to use vcpu_feature_is_available() to simplify checking of the feature's availability. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a09c910198d6..6a8ed59d8d90 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -389,6 +389,11 @@ static void feature_tracefilt_trap_activate(struct kvm_vcpu *vcpu) feature_trap_activate(vcpu, VCPU_MDCR_EL2, MDCR_EL2_TTRF, 0); } +static void feature_lor_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_HCR_EL2, HCR_TLOR, 0); +} + /* For ID_AA64PFR0_EL1 */ static struct feature_config_ctrl ftr_ctrl_ras = { .ftr_reg = SYS_ID_AA64PFR0_EL1, @@ -448,6 +453,15 @@ static struct feature_config_ctrl ftr_ctrl_tracefilt = { .trap_activate = feature_tracefilt_trap_activate, }; +/* For ID_AA64MMFR1_EL1 */ +static struct feature_config_ctrl ftr_ctrl_lor = { + .ftr_reg = SYS_ID_AA64MMFR1_EL1, + .ftr_shift = ID_AA64MMFR1_LOR_SHIFT, + .ftr_min = 1, + .ftr_signed = FTR_UNSIGNED, + .trap_activate = feature_lor_trap_activate, +}; + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -1104,10 +1118,9 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 val = read_id_reg_with_encoding(vcpu, SYS_ID_AA64MMFR1_EL1); u32 sr = reg_to_encoding(r); - if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { + if (!vcpu_feature_is_available(vcpu, &ftr_ctrl_lor)) { kvm_inject_undefined(vcpu); return false; } @@ -4433,6 +4446,14 @@ static struct id_reg_desc id_aa64mmfr0_el1_desc = { }, }; +static struct id_reg_desc id_aa64mmfr1_el1_desc = { + .reg_desc = ID_SANITISED(ID_AA64MMFR1_EL1), + .trap_features = &(const struct feature_config_ctrl *[]) { + &ftr_ctrl_lor, + NULL, + }, +}; + static struct id_reg_desc id_aa64dfr0_el1_desc = { .reg_desc = ID_SANITISED(ID_AA64DFR0_EL1), /* @@ -4577,7 +4598,7 @@ static struct id_reg_desc *id_reg_desc_table[KVM_ARM_ID_REG_MAX_NUM] = { /* CRm=7 */ ID_DESC(ID_AA64MMFR0_EL1, &id_aa64mmfr0_el1_desc), - ID_DESC_DEFAULT(ID_AA64MMFR1_EL1), + ID_DESC(ID_AA64MMFR1_EL1, &id_aa64mmfr1_el1_desc), ID_DESC_DEFAULT(ID_AA64MMFR2_EL1), ID_DESC_UNALLOC(7, 3), ID_DESC_UNALLOC(7, 4), From patchwork Tue Apr 19 06:55:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C94EFC433F5 for ; Tue, 19 Apr 2022 07:21:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=lykmPrYpCebfQzHdpjz6HPfnhJrxPhRXzR9FEvgCksA=; b=t1js0jSRv1uL1aHMVEKpBJWwh7 lVmVF4gg+D7qTNrCrkZ9hdXQwkIQr5u4jAHeDfbZGsSjntP+UdVvmfB766GFlCUvFnaCjRwi/9vD0 P3hfAK3FC/gsqBbXF0WO0q9w6V+nLa3HPheG73Ct/ANBAOI2wmWEKGecK58XIJjWdx9L47FTJNT9z kCoVYd1hPGLHeaCqaG+ZOVG5CxoHrVPzvO0qSXXDFxflLjKhv+l1W6gPbt1onIwSKb/KgAtTSut+D HtHN64sdqHlbZu5biFSc/pnRWXaFjwbuXEQNMAXk8ePxEZl61OrGuFBVcNXcGBnf3tzHHnm74DioN Agg2PuHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngi9e-001vwe-1G; Tue, 19 Apr 2022 07:20:07 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoD-001nkw-9B for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:57:59 +0000 Received: by mail-pj1-x1049.google.com with SMTP id r12-20020a17090a690c00b001cb9bce2284so10128802pjj.8 for ; Mon, 18 Apr 2022 23:57:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=YLQ/jtBXlP9biEBlw29VzMlxGtkHK85JhXdSg1Dey2k=; b=eAw4dTke4ES4lJseM7OQ6Z/1m7Omzg+78Rf0GXMt1GNKwDyp38SZ6TmEaeL41gIF3V O3W2n9UMmq+6M2Dlqx7kPsxjW9QwgcacCCvhksep5fJ2ps5tbZ4U6zJw0q2UO/Zml3ym 9BCmmDCprmbgGdLCXrZdHzt/XmNLdUXEBH4TBQs6gcdzLkC7ybe3KRk952sC/b6zHZSA iAvYXo/EGdqGvbO71ux5zx0vlb30A3xe8dM0BJSX6BxG1QZD+7b6D7VD8d30WtVdba9j P00CX0knXDaWtBD1id8WQ6fLIy/E99z+vOOTA5nnERYy6RpDQtJR1OgHZ37/lfhfTb+s RrxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=YLQ/jtBXlP9biEBlw29VzMlxGtkHK85JhXdSg1Dey2k=; b=pMbOZlZB++yECgWH9lPi3fNQuwzMyIuF4+Qh2RmEmOhM22aIOQmSBz+2cZk7CIFIbV 55Mt/PgirsuDYg5PGOSEjXxNH3vSzdtwkrMEsu1Qc4oMJ2fD5on7zjBr1qq0ra1FXbhw Jiw0YdlNbdqMi+u7Q9fVqXBB2E3Th0itXGUQ7EfWlQO++Z6Dqaq6XjpJF/zXK0qXITB6 kS7unwkkGUt/a33Yp7qnNu49ogRLEMjd1OHz6ofUBiiaWTugPdXfzRy7XuEwjJGRyAXx iwV2zV2W2cZF0Ezr9ORzoVZJ9JQspC3dLSQ6B6IqxaBWzjH2JdLpRxsNW5CWxkXVLWSj 2MkQ== X-Gm-Message-State: AOAM530yWKkAv0Zmrh5mbHGUOqioi8fA98XLqJfSuOBorZeAJGC9I1pr +thLhws4VR6yChwqjuJV8GvhEO6i1Y8= X-Google-Smtp-Source: ABdhPJwTql5uKFd/srdQQoG38aaRxnbuF6PS3EHwIAVgiky4Itg3RMnrRk+AFOPWQpN2BRiBLUohcU6eXZw= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90b:4b07:b0:1d1:8a08:5096 with SMTP id lx7-20020a17090b4b0700b001d18a085096mr16807088pjb.91.1650351475734; Mon, 18 Apr 2022 23:57:55 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:37 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-32-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 31/38] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235757_417846_985DD422 X-CRM114-Status: GOOD ( 14.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add feature_config_ctrl for PTRAUTH, which is indicated in ID_AA64ISAR1_EL1, to program configuration register to trap guest's using the feature when it is not exposed to the guest. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6a8ed59d8d90..0e3cff91f41d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -299,6 +299,15 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, (cpuid_feature_extract_unsigned_field(val, ID_AA64ISAR2_GPA3_SHIFT) >= \ ID_AA64ISAR2_GPA3_ARCHITECTED) +/* + * Return true if ptrauth needs to be trapped. + * (i.e. if ptrauth is supported on the host but not exposed to the guest) + */ +static bool vcpu_need_trap_ptrauth(struct kvm_vcpu *vcpu) +{ + return (system_has_full_ptr_auth() && !vcpu_has_ptrauth(vcpu)); +} + /* * Feature information to program configuration register to trap or disable * guest's using a feature when the feature is not exposed to the guest. @@ -394,6 +403,11 @@ static void feature_lor_trap_activate(struct kvm_vcpu *vcpu) feature_trap_activate(vcpu, VCPU_HCR_EL2, HCR_TLOR, 0); } +static void feature_ptrauth_trap_activate(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_HCR_EL2, 0, HCR_API | HCR_APK); +} + /* For ID_AA64PFR0_EL1 */ static struct feature_config_ctrl ftr_ctrl_ras = { .ftr_reg = SYS_ID_AA64PFR0_EL1, @@ -462,6 +476,12 @@ static struct feature_config_ctrl ftr_ctrl_lor = { .trap_activate = feature_lor_trap_activate, }; +/* For SYS_ID_AA64ISAR1_EL1 */ +static struct feature_config_ctrl ftr_ctrl_ptrauth = { + .ftr_need_trap = vcpu_need_trap_ptrauth, + .trap_activate = feature_ptrauth_trap_activate, +}; + #define __FTR_BITS(ftr_sign, ftr_type, bit_pos, safe) { \ .sign = ftr_sign, \ .type = ftr_type, \ @@ -4416,6 +4436,10 @@ static struct id_reg_desc id_aa64isar1_el1_desc = { U_FTR_BITS(FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 0), U_FTR_BITS(FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 0), }, + .trap_features = &(const struct feature_config_ctrl *[]) { + &ftr_ctrl_ptrauth, + NULL, + }, }; static struct id_reg_desc id_aa64isar2_el1_desc = { From patchwork Tue Apr 19 06:55:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2AE46C433EF for ; Tue, 19 Apr 2022 07:22:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=5ycb3vAm966xbdTxD6BcTjEHQPqvPXI/eRxGBnSdWJI=; b=tC6DK3YrmpZ5S6sm3r5cANHy+d fG49QrllYQ4mF+ylh9t+wgoGIrhuzghJtclk6w9eh3zCcieIWQowboEZipIKZT3PswV6+yWVzRk74 K/BXa69XRBLB94MNFIdpVeJnIEnagUw6mCTyrVH7RR6evtd8GfqJPQ8EYxmKZAhY+LvspjBb0+264 WoxrItATEcgAWB9zYfa5SAK9SC3MDEBAjS30iarpjMq26FIQ+875874BpWH9dyUPQimDEGQ4Ns0hA 0Z8YZYBvUzgLGVYeuhVkmkwVJYendyxSYuxTNwqgPC6tqPoUTVNiawZTYj8PS17oqXLXrZq46gOPG nkV4yRfQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiAN-001wDS-Dy; Tue, 19 Apr 2022 07:20:51 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoE-001nm5-NZ for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:58:01 +0000 Received: by mail-pj1-x104a.google.com with SMTP id j24-20020a17090aeb1800b001d17733a1a6so1175363pjz.6 for ; Mon, 18 Apr 2022 23:57:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=NuyHwIdLopy65edSNneYdDxbRUfisj8CwS/EiSJPzd8=; b=JuUUKKxB0c/5jIWsiYKyQ96v92kR8U04zVTmghfJqxxpOX8oOFxp3i2Z2Nh093oYyp H0/kx9a1P/1ubVd3lZh6kDtH/OiOf71OtqLY72YPtLpY8YP3ffOIP/lEAVsJQSBvHYot vzBxzkQhgwMMo9LdW17weQLrbPW108wD8tKY1Wbzlos4ZAFAKrE5q0N/q3ZNwaUf4SuT cdlO0hLMTuo62b1V7ayXsfaOxdiaZeIynR2WqLtL3z1lshngrZDzOiNr4pCJeXSHE/TC ruUHeK7oqyDFbziR9rKDw4GGtuul/EAGF4K2GLLmivhjb0emsW0h1fQUYia2GZAa0et3 2qFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=NuyHwIdLopy65edSNneYdDxbRUfisj8CwS/EiSJPzd8=; b=DEI/hpyhVSs/Eu/P+ZW5Jj39h88tEh7FEVuy6DZSF6hb0Y7FMjgitUN9WQXsA/FJJm N4oZWjZQtklGitInenX6XabBVTTrakjFgTz11gx+ctTOJXm9hUMgYwwm2CjjpbR+krF0 8WBJg6gbmMDZZA2q7JZyCuBXXdnht0mtqYJH/H30K0aCrNUhODl7XOt7EA/ARhKZZAPJ 4YUPE9s4UDA1H2t5hIUDz6wINVNSOBH54HLoLXue1JZAGVvAxXQsBwX1gn98Xn6xCgHN s2zgHL/rIY/BLbNRUdSziwaQLKPsCeL3HJTIsk9r+GsAT1rFSb93NeakuKksUkLUAPtS dneA== X-Gm-Message-State: AOAM530ayl1MdHf6sovqdiR22U72c69mcMp8OpWO8DWEj1/t0MyIJk28 3zzx7memML/Z4jg5QVgYqnIfHP42kwI= X-Google-Smtp-Source: ABdhPJydE7fDS2laiwWJTKLimV4fAMnUFfC2eflrLVOosa8XXTixDdxvFoVs0mgS6AY3uBwDt69iQ8327ek= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a63:1141:0:b0:39c:b664:c508 with SMTP id 1-20020a631141000000b0039cb664c508mr13579700pgr.49.1650351477273; Mon, 18 Apr 2022 23:57:57 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:38 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-33-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 32/38] KVM: arm64: Add kunit test for trap initialization From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235758_877084_62C9A5E9 X-CRM114-Status: GOOD ( 17.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add KUnit tests for functions in arch/arm64/kvm/sys_regs_test.c that activates traps for disabled features. Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/sys_regs_test.c | 219 +++++++++++++++++++++++++++++++++ 1 file changed, 219 insertions(+) diff --git a/arch/arm64/kvm/sys_regs_test.c b/arch/arm64/kvm/sys_regs_test.c index dff146fe0e62..f9b032032ec3 100644 --- a/arch/arm64/kvm/sys_regs_test.c +++ b/arch/arm64/kvm/sys_regs_test.c @@ -1041,6 +1041,222 @@ static void validate_id_reg_test(struct kunit *test) } } +struct trap_config_test { + u64 set; + u64 clear; + u64 prev_val; + u64 expect_val; +}; + +struct trap_config_test trap_params[] = { + {0x30000800000, 0, 0, 0x30000800000}, + {0, 0x30000800000, 0, 0}, + {0x30000800000, 0, (u64)-1, (u64)-1}, + {0, 0x30000800000, (u64)-1, (u64)0xfffffcffff7fffff}, +}; + +static void trap_case_to_desc(struct trap_config_test *t, char *desc) +{ + snprintf(desc, KUNIT_PARAM_DESC_SIZE, + "trap - set:0x%llx, clear:0x%llx, prev_val:0x%llx\n", + t->set, t->clear, t->prev_val); +} + +KUNIT_ARRAY_PARAM(trap, trap_params, trap_case_to_desc); + +/* Tests for feature_trap_activate(). */ +static void feature_trap_activate_test(struct kunit *test) +{ + struct kvm_vcpu *vcpu; + const struct trap_config_test *trap = test->param_value; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_ASSERT_TRUE(test, vcpu); + + /* Test for HCR_EL2 */ + vcpu->arch.hcr_el2 = trap->prev_val; + feature_trap_activate(vcpu, VCPU_HCR_EL2, trap->set, trap->clear); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2, trap->expect_val); + + /* Test for MDCR_EL2 */ + vcpu->arch.mdcr_el2 = trap->prev_val; + feature_trap_activate(vcpu, VCPU_MDCR_EL2, trap->set, trap->clear); + KUNIT_EXPECT_EQ(test, vcpu->arch.mdcr_el2, trap->expect_val); + + /* Test for CPTR_EL2 */ + vcpu->arch.cptr_el2 = trap->prev_val; + feature_trap_activate(vcpu, VCPU_CPTR_EL2, trap->set, trap->clear); + KUNIT_EXPECT_EQ(test, vcpu->arch.cptr_el2, trap->expect_val); +} + +static u64 test_trap_set0; +static u64 test_trap_clear0; +static void test_trap_activate0(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_HCR_EL2, + test_trap_set0, test_trap_clear0); +} + +static u64 test_trap_set1; +static u64 test_trap_clear1; +static void test_trap_activate1(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_HCR_EL2, + test_trap_set1, test_trap_clear1); +} + +static u64 test_trap_set2; +static u64 test_trap_clear2; +static void test_trap_activate2(struct kvm_vcpu *vcpu) +{ + feature_trap_activate(vcpu, VCPU_HCR_EL2, + test_trap_set2, test_trap_clear2); +} + + +static void setup_feature_config_ctrl(struct feature_config_ctrl *config, + u32 id, int shift, int min, bool sign, + void *fn) +{ + memset(config, 0, sizeof(*config)); + config->ftr_reg = id; + config->ftr_shift = shift; + config->ftr_min = min; + config->ftr_signed = sign; + config->trap_activate = fn; +} + +/* + * Tests for id_reg_features_trap_activate. + * Setup a id_reg_desc with three entries in id_reg_desc->trap_features[]. + * Check if the config register is updated to enable trap for the disabled + * features. + */ +static void id_reg_features_trap_activate_test(struct kunit *test) +{ + struct kvm_vcpu *vcpu; + u32 id; + u64 cfg_set, cfg_clear, id_reg_sys_val, id_reg_val; + struct id_reg_desc id_reg_data = {}; + struct feature_config_ctrl config0, config1, config2; + struct feature_config_ctrl *trap_features[] = { + &config0, &config1, &config2, NULL, + }; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_EXPECT_TRUE(test, vcpu); + if (!vcpu) + return; + + /* Setup id_reg_desc */ + id_reg_sys_val = 0x7777777777777777; + id = SYS_ID_AA64DFR0_EL1; + set_sys_desc((struct sys_reg_desc *)&id_reg_data.reg_desc, id); + id_reg_data.sys_val = id_reg_sys_val; + id_reg_data.vcpu_limit_val = (u64)-1; + id_reg_data.trap_features = + (const struct feature_config_ctrl *(*)[])trap_features; + + /* Setup the 1st feature_config_ctrl */ + test_trap_set0 = 0x3; + test_trap_clear0 = 0x0; + setup_feature_config_ctrl(&config0, id, 60, 2, FTR_UNSIGNED, + &test_trap_activate0); + + /* Setup the 2nd feature_config_ctrl */ + test_trap_set1 = 0x30000040; + test_trap_clear1 = 0x40000000; + setup_feature_config_ctrl(&config1, id, 0, 1, FTR_UNSIGNED, + &test_trap_activate1); + + /* Setup the 3rd feature_config_ctrl */ + test_trap_set2 = 0x30000000800; + test_trap_clear2 = 0x40000000000; + setup_feature_config_ctrl(&config2, id, 4, 0, FTR_SIGNED, + &test_trap_activate2); + +#define ftr_dis(cfg) \ + ((u64)(((cfg)->ftr_min - 1) & 0xf) << (cfg)->ftr_shift) + +#define ftr_en(cfg) \ + ((u64)(cfg)->ftr_min << (cfg)->ftr_shift) + + /* Test with features enabled for config0, 1 and 2 */ + id_reg_val = ftr_en(&config0) | ftr_en(&config1) | ftr_en(&config2); + write_kvm_id_reg(vcpu->kvm, id, id_reg_val); + vcpu->arch.hcr_el2 = 0; + id_reg_features_trap_activate(vcpu, &id_reg_data); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2, 0); + + + /* Test with features disabled for config0 only */ + id_reg_val = ftr_dis(&config0) | ftr_en(&config1) | ftr_en(&config2); + write_kvm_id_reg(vcpu->kvm, id, id_reg_val); + vcpu->arch.hcr_el2 = 0; + cfg_set = test_trap_set0; + cfg_clear = test_trap_clear0; + + id_reg_features_trap_activate(vcpu, &id_reg_data); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2 & cfg_set, cfg_set); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2 & cfg_clear, 0); + + + /* Test with features disabled for config0 and config1 */ + id_reg_val = ftr_dis(&config0) | ftr_dis(&config1) | ftr_en(&config2); + write_kvm_id_reg(vcpu->kvm, id, id_reg_val); + vcpu->arch.hcr_el2 = 0; + + cfg_set = test_trap_set0 | test_trap_set1; + cfg_clear = test_trap_clear0 | test_trap_clear1; + + id_reg_features_trap_activate(vcpu, &id_reg_data); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2 & cfg_set, cfg_set); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2 & cfg_clear, 0); + + + /* Test with features disabled for config0, config1, and config2 */ + id_reg_val = ftr_dis(&config0) | ftr_dis(&config1) | ftr_dis(&config2); + write_kvm_id_reg(vcpu->kvm, id, id_reg_val); + vcpu->arch.hcr_el2 = 0; + + cfg_set = test_trap_set0 | test_trap_set1 | test_trap_set2; + cfg_clear = test_trap_clear0 | test_trap_clear1 | test_trap_clear2; + + id_reg_features_trap_activate(vcpu, &id_reg_data); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2 & cfg_set, cfg_set); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2 & cfg_clear, 0); + + + /* Test with id_reg_data.trap_features = NULL */ + id_reg_data.trap_features = NULL; + vcpu->arch.hcr_el2 = 0; + id_reg_features_trap_activate(vcpu, &id_reg_data); + KUNIT_EXPECT_EQ(test, vcpu->arch.hcr_el2, 0); +} + +/* Tests for vcpu_need_trap_ptrauth(). */ +static void vcpu_need_trap_ptrauth_test(struct kunit *test) +{ + struct kvm_vcpu *vcpu; + + vcpu = test_kvm_vcpu_init(test); + KUNIT_EXPECT_TRUE(test, vcpu); + if (!vcpu) + return; + + if (system_has_full_ptr_auth()) { + /* Tests with PTRAUTH disabled vCPU */ + KUNIT_EXPECT_TRUE(test, vcpu_need_trap_ptrauth(vcpu)); + + /* Tests with PTRAUTH enabled vCPU */ + vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH; + + KUNIT_EXPECT_FALSE(test, vcpu_need_trap_ptrauth(vcpu)); + } else { + KUNIT_EXPECT_FALSE(test, vcpu_need_trap_ptrauth(vcpu)); + } +} + static struct kunit_case kvm_sys_regs_test_cases[] = { KUNIT_CASE_PARAM(vcpu_id_reg_feature_frac_check_test, frac_gen_params), KUNIT_CASE_PARAM(validate_id_aa64mmfr0_tgran2_test, tgran4_2_gen_params), @@ -1056,6 +1272,9 @@ static struct kunit_case kvm_sys_regs_test_cases[] = { KUNIT_CASE(validate_id_dfr0_el1_test), KUNIT_CASE(validate_mvfr1_el1_test), KUNIT_CASE(validate_id_reg_test), + KUNIT_CASE(vcpu_need_trap_ptrauth_test), + KUNIT_CASE_PARAM(feature_trap_activate_test, trap_gen_params), + KUNIT_CASE(id_reg_features_trap_activate_test), {} }; From patchwork Tue Apr 19 06:55:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08A3CC433F5 for ; Tue, 19 Apr 2022 07:22:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=tP8l65o9K9uNO5eObVdOCpEv0zizxiUCJnLyE78Se5U=; b=0MxMHTxBHr3c8ffFmGk4qLcsdl UqbIpm17DSc3zX2UZh4TdBjLtJpYjyXM9KVsXDJA4vOsQJ7M3HwkpBylJj8AkFj3tAIDzWHyoqQ/7 pY9PliyCbHwQ+7ZHBVHDtdV6jmkdNOc4rN37oVEypPeByrCbA3W4eblm8ImoAJm/5KD8Kr8vsXJbD 1ZDJ1d6F1XNnicIY5UuMY1Z7nUVm5jm/51MqTU0/7m3ofuXPYaWg4ndefpfQcMFy9Y6hPWoVAbldN 6yMYt2dKYgHHcBg7nYJmih+hMstbqsenoO8z/mIce34lDVfBsWa6lcI6A6jHdVFUr8lt9LdyMR0XH x5LTMgpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiBA-001wbB-0c; Tue, 19 Apr 2022 07:21:40 +0000 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoF-001nmh-Vi for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:58:03 +0000 Received: by mail-pl1-x64a.google.com with SMTP id q6-20020a170902eb8600b001588e49dcaaso9254778plg.9 for ; Mon, 18 Apr 2022 23:57:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=xBTLHLT7VrzBgTmY/Z5pWtMxjNk9GRjM0Wsv/9rlNHc=; b=VXqtSraq8cu7MS05g2E9z+XuvMzeSXl2fFGX5Y01D5E/dIxxlzx8ieTe37RrjIk3U8 Qh9dlqkHr26rlE7cUeUJ722X9fORrcSyls/mjjfEdxkk7qv/i5exSe67vJL6znd7Jmxj XQleVnWUgNa/U6XHeLU4cVi7jJbuACQra/1UYgGqj4K+tkf/7sFnacr1qvJFFrXMhwrq LjiCU6LR5oMDmzv/AEuJDND+2wNX7EIcualNNJMKjPM+NXlYzs2C04kgPXIuXt8MTbBE VzdBDFwig9oH+F/vqkUZNWb/QeEljHfxo03ihPpY/Au8WjocLvzfT43Yox/2khE42Mcv XECg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=xBTLHLT7VrzBgTmY/Z5pWtMxjNk9GRjM0Wsv/9rlNHc=; b=Ot56EkIHeSaK0Djck7ETNat0QHWPYZFLwgpgs5VbF0DGuvbY39vzwRJmxW31wI7Az8 asIMQu+tFgfqfv8w0D7l4zQ/2x6bH/bYWcBHcF45XvVwKlsqN1XYl/YjST1x96xSTEhb g5TXkH5GrYLaLkgon1L47x6BcSEzHyU9eVctAy7Pz5FSV6JDcuQt0/NEjuIpJl2ICEsx Tbc0gVhhzTTRtaKTfajHCDRdLJhutd628KgWC/B1CFLfZOj9Qzq3zYC1UHUxSLXwR67p dRuuWOnBITT1Hjy5wGXKVZHk2SE8CYAknKPoyUEQThWhtwuBFjEOhBUG3UU7P7Lanwit d7aA== X-Gm-Message-State: AOAM531FRZq/uamt8/BYLpuXi5fAulZ8+arZzcSuc2Sl895aalWZM0Xs a9C80c35sT+aydHIeoSwaN/8CtGAyyE= X-Google-Smtp-Source: ABdhPJwdi9SagPghJ2ANdJN9l35v2yt6f3eckRDsDVajt8Roakd+ylnifLm17O2VDNHE6Bdtl1/igHdjhO4= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90b:390d:b0:1d2:7a7d:170e with SMTP id ob13-20020a17090b390d00b001d27a7d170emr13243483pjb.230.1650351478693; Mon, 18 Apr 2022 23:57:58 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:39 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-34-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 33/38] KVM: arm64: selftests: Add helpers to extract a field of ID registers From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235800_074975_FABC833D X-CRM114-Status: UNSURE ( 9.59 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a couple of helpers to extract a field of ID registers. Signed-off-by: Reiji Watanabe --- .../selftests/kvm/include/aarch64/processor.h | 5 ++++ .../selftests/kvm/lib/aarch64/processor.c | 27 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/tools/testing/selftests/kvm/include/aarch64/processor.h b/tools/testing/selftests/kvm/include/aarch64/processor.h index 8f9f46979a00..e12411fec822 100644 --- a/tools/testing/selftests/kvm/include/aarch64/processor.h +++ b/tools/testing/selftests/kvm/include/aarch64/processor.h @@ -185,4 +185,9 @@ static inline void local_irq_disable(void) asm volatile("msr daifset, #3" : : : "memory"); } +int extract_signed_field(uint64_t val, int field, int width); +unsigned int extract_unsigned_field(uint64_t val, int field, int width); +int cpuid_extract_ftr(uint64_t val, int field, bool sign); +int cpuid_extract_sftr(uint64_t val, int field); +unsigned int cpuid_extract_uftr(uint64_t val, int field); #endif /* SELFTEST_KVM_PROCESSOR_H */ diff --git a/tools/testing/selftests/kvm/lib/aarch64/processor.c b/tools/testing/selftests/kvm/lib/aarch64/processor.c index 9343d82519b4..c55f7dfc8567 100644 --- a/tools/testing/selftests/kvm/lib/aarch64/processor.c +++ b/tools/testing/selftests/kvm/lib/aarch64/processor.c @@ -500,3 +500,30 @@ void __attribute__((constructor)) init_guest_modes(void) { guest_modes_append_default(); } + +/* Helpers to get a feature field from ID register value */ +int extract_signed_field(uint64_t val, int field, int width) +{ + return (int64_t)(val << (64 - width - field)) >> (64 - width); +} + +unsigned int extract_unsigned_field(uint64_t val, int field, int width) +{ + return (uint64_t)(val << (64 - width - field)) >> (64 - width); +} + +int cpuid_extract_ftr(uint64_t val, int field, bool sign) +{ + return (sign) ? extract_signed_field(val, field, 4) : + extract_unsigned_field(val, field, 4); +} + +int cpuid_extract_sftr(uint64_t val, int field) +{ + return cpuid_extract_ftr(val, field, true); +} + +unsigned int cpuid_extract_uftr(uint64_t val, int field) +{ + return cpuid_extract_ftr(val, field, false); +} From patchwork Tue Apr 19 06:55:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32002C433F5 for ; Tue, 19 Apr 2022 07:26:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=qrQPz/REKww0RQ1PQH74Fl5GgDOtlYyWPpo1+2p3sFQ=; b=DvGgT4e16MPge6Dg4yfLojud3w Wfbraj01bYfsm7kmeDvaDv0cLM48aWjPnEVlXouWen/JvlncqDImLbJoZzgfq4S2v5RHI41HfqE1v 3FZXDLVop+Ai8tbywg26D7Do7/hUG/N7frC4YAgP5wLA8tbfd40vNHT8spCjTZlX44ze1dL2WY9DH RC0BEf2b3/hrN3OKxx8X4kxlk2gzVMQ/7IdKRA+F0j07BEyE9wYOQ0y+dfVNecUa67qrGq9eW0aRw RrUQbE9p31DXzQj7DQxgvdUO6s+OnIjfRlkY7fMs2U46okV6ndG1Y0ryAMi/qFX9ks4U/oMh212kZ Z/1wOWdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiDp-001xmz-VG; Tue, 19 Apr 2022 07:24:26 +0000 Received: from mail-pl1-x64a.google.com ([2607:f8b0:4864:20::64a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoH-001nng-DZ for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:58:11 +0000 Received: by mail-pl1-x64a.google.com with SMTP id i10-20020a170902e48a00b00153f493fa9aso9253328ple.17 for ; Mon, 18 Apr 2022 23:58:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=E1XfTguN90Go61iTkkkzTptNztp763kRSY9BfJYJx8g=; b=hTfjMXkK1IW7Ujub7V2ilUYVfF6VAlnBA0VMLVD6fG5AXF+hXdPgXnEx3i5uhGJufU 6dcx5E8NPxLT7UOvCvvxEn/PyARnrnvwZThc/jcV8Ccvj68dnTidyDlrojATU9CcqAAG JAdPxGBNCNa0IT4JeOT1I2GBc6cHfuM80QJIO+8wL4xxfPPAO1tvI+lB8VUmvJnXjNjc 7Q9Ax7w0dcj61LdAFxV7X0RqDFxSxkQqLaecLvBwBZFl5B04WhsniJ2p3CjtPnF32vBu DXB4SJniQLf9XFcIDAUHlYGOhyfVM/V7WxFZ8DySWhtiuqhXhix0q9Qowkhdex5aOvDR U2OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=E1XfTguN90Go61iTkkkzTptNztp763kRSY9BfJYJx8g=; b=PAV6jnz8ZfPjwYW2rQ1EoGwpslCmLkp02oAunUD7A8uNEq8qTu0eUZKJnHyVs3Z+zs dA/MtaM0ktTedzf91E0zeYwxEj8093J2nInetFNzJU/Dv1HE63rUVngL74QL2eri8KQ3 InZvyWtZa9chQl6/Votv7REDvOHFlT5n5iSnizNxBMOAT/wdVinlDeBgBDxWxDP3A/Ro tJePFdTci0cMcxSGd1MjQfxGZmQ92773ZkKcPJwFieSZdwimHXDB8E4PhM7xjVUccyHu gTL1BdZBalcdsi+YHHFH7K/myewfEBNnwq4nFfB3EMxK2rZOndmpb+DjiQmstPEakaBN AGxQ== X-Gm-Message-State: AOAM53045fj+NOUaWhwaVVFe0jv5pxenuHiaOFYCLM1S/OteANck/qGL 25gfovkh9xGr28XKceRW7sW3tnCeC7E= X-Google-Smtp-Source: ABdhPJyunNkl9z4aMdkR7T/XBkKMRhcjzBt9WIsuvah5sAiLNnC9wGtf0/TjQNBd5JJQF8vtvKE6M1R1xlc= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:aa7:8a06:0:b0:506:28c:1282 with SMTP id m6-20020aa78a06000000b00506028c1282mr16337757pfa.19.1650351480368; Mon, 18 Apr 2022 23:58:00 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:40 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-35-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 34/38] KVM: arm64: selftests: Introduce id_reg_test From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235801_574950_6B1054E0 X-CRM114-Status: GOOD ( 23.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a test for aarch64 to validate basic behavior of KVM_GET_ONE_REG and KVM_SET_ONE_REG for ID registers. This test runs only when KVM_CAP_ARM_ID_REG_CONFIGURABLE is supported. Signed-off-by: Reiji Watanabe --- tools/arch/arm64/include/asm/sysreg.h | 1 + tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/aarch64/id_reg_test.c | 1297 +++++++++++++++++ 3 files changed, 1299 insertions(+) create mode 100644 tools/testing/selftests/kvm/aarch64/id_reg_test.c diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h index 7640fa27be94..be3947c125f1 100644 --- a/tools/arch/arm64/include/asm/sysreg.h +++ b/tools/arch/arm64/include/asm/sysreg.h @@ -793,6 +793,7 @@ #define ID_AA64PFR0_ELx_32BIT_64BIT 0x2 /* id_aa64pfr1 */ +#define ID_AA64PFR1_CSV2FRAC_SHIFT 32 #define ID_AA64PFR1_MPAMFRAC_SHIFT 16 #define ID_AA64PFR1_RASFRAC_SHIFT 12 #define ID_AA64PFR1_MTE_SHIFT 8 diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 681b173aa87c..e94e4dc45297 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -105,6 +105,7 @@ TEST_GEN_PROGS_x86_64 += system_counter_offset_test TEST_GEN_PROGS_aarch64 += aarch64/arch_timer TEST_GEN_PROGS_aarch64 += aarch64/debug-exceptions TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list +TEST_GEN_PROGS_aarch64 += aarch64/id_reg_test TEST_GEN_PROGS_aarch64 += aarch64/psci_cpu_on_test TEST_GEN_PROGS_aarch64 += aarch64/vcpu_width_config TEST_GEN_PROGS_aarch64 += aarch64/vgic_init diff --git a/tools/testing/selftests/kvm/aarch64/id_reg_test.c b/tools/testing/selftests/kvm/aarch64/id_reg_test.c new file mode 100644 index 000000000000..7e7e66b867c0 --- /dev/null +++ b/tools/testing/selftests/kvm/aarch64/id_reg_test.c @@ -0,0 +1,1297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * id_reg_test.c - Tests reading/writing the aarch64's ID registers + * + * The test validates KVM_SET_ONE_REG/KVM_GET_ONE_REG ioctl for ID + * registers as well as reading ID register from the guest works fine. + * + * Copyright (c) 2022, Google LLC. + */ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include + +#include "kvm_util.h" +#include "processor.h" +#include "vgic.h" + +/* Reserved ID registers */ +#define SYS_ID_REG_3_3_EL1 sys_reg(3, 0, 0, 3, 3) +#define SYS_ID_REG_3_7_EL1 sys_reg(3, 0, 0, 3, 7) + +#define SYS_ID_REG_4_2_EL1 sys_reg(3, 0, 0, 4, 2) +#define SYS_ID_REG_4_3_EL1 sys_reg(3, 0, 0, 4, 3) +#define SYS_ID_REG_4_5_EL1 sys_reg(3, 0, 0, 4, 5) +#define SYS_ID_REG_4_6_EL1 sys_reg(3, 0, 0, 4, 6) +#define SYS_ID_REG_4_7_EL1 sys_reg(3, 0, 0, 4, 7) + +#define SYS_ID_REG_5_2_EL1 sys_reg(3, 0, 0, 5, 2) +#define SYS_ID_REG_5_3_EL1 sys_reg(3, 0, 0, 5, 3) +#define SYS_ID_REG_5_6_EL1 sys_reg(3, 0, 0, 5, 6) +#define SYS_ID_REG_5_7_EL1 sys_reg(3, 0, 0, 5, 7) + +#define SYS_ID_REG_6_2_EL1 sys_reg(3, 0, 0, 6, 2) +#define SYS_ID_REG_6_3_EL1 sys_reg(3, 0, 0, 6, 3) +#define SYS_ID_REG_6_4_EL1 sys_reg(3, 0, 0, 6, 4) +#define SYS_ID_REG_6_5_EL1 sys_reg(3, 0, 0, 6, 5) +#define SYS_ID_REG_6_6_EL1 sys_reg(3, 0, 0, 6, 6) +#define SYS_ID_REG_6_7_EL1 sys_reg(3, 0, 0, 6, 7) + +#define SYS_ID_REG_7_3_EL1 sys_reg(3, 0, 0, 7, 3) +#define SYS_ID_REG_7_4_EL1 sys_reg(3, 0, 0, 7, 4) +#define SYS_ID_REG_7_5_EL1 sys_reg(3, 0, 0, 7, 5) +#define SYS_ID_REG_7_6_EL1 sys_reg(3, 0, 0, 7, 6) +#define SYS_ID_REG_7_7_EL1 sys_reg(3, 0, 0, 7, 7) + +#define READ_ID_REG_FN(name) read_## name ## _EL1 + +#define DEFINE_READ_SYS_REG(reg_name) \ +uint64_t read_##reg_name(void) \ +{ \ + return read_sysreg_s(SYS_##reg_name); \ +} + +#define DEFINE_READ_ID_REG(name) \ + DEFINE_READ_SYS_REG(name ## _EL1) + +#define __ID_REG(reg_name) \ + .name = #reg_name, \ + .id = SYS_## reg_name ##_EL1, \ + .read_reg = READ_ID_REG_FN(reg_name), + +#define ID_REG_ENT(reg_name) \ + [ID_IDX(reg_name)] = { __ID_REG(reg_name) } + +/* Functions to read each ID register */ +/* CRm=1 */ +DEFINE_READ_ID_REG(ID_PFR0) +DEFINE_READ_ID_REG(ID_PFR1) +DEFINE_READ_ID_REG(ID_DFR0) +DEFINE_READ_ID_REG(ID_AFR0) +DEFINE_READ_ID_REG(ID_MMFR0) +DEFINE_READ_ID_REG(ID_MMFR1) +DEFINE_READ_ID_REG(ID_MMFR2) +DEFINE_READ_ID_REG(ID_MMFR3) + +/* CRm=2 */ +DEFINE_READ_ID_REG(ID_ISAR0) +DEFINE_READ_ID_REG(ID_ISAR1) +DEFINE_READ_ID_REG(ID_ISAR2) +DEFINE_READ_ID_REG(ID_ISAR3) +DEFINE_READ_ID_REG(ID_ISAR4) +DEFINE_READ_ID_REG(ID_ISAR5) +DEFINE_READ_ID_REG(ID_MMFR4) +DEFINE_READ_ID_REG(ID_ISAR6) + +/* CRm=3 */ +DEFINE_READ_ID_REG(MVFR0) +DEFINE_READ_ID_REG(MVFR1) +DEFINE_READ_ID_REG(MVFR2) +DEFINE_READ_ID_REG(ID_REG_3_3) +DEFINE_READ_ID_REG(ID_PFR2) +DEFINE_READ_ID_REG(ID_DFR1) +DEFINE_READ_ID_REG(ID_MMFR5) +DEFINE_READ_ID_REG(ID_REG_3_7) + +/* CRm=4 */ +DEFINE_READ_ID_REG(ID_AA64PFR0) +DEFINE_READ_ID_REG(ID_AA64PFR1) +DEFINE_READ_ID_REG(ID_REG_4_2) +DEFINE_READ_ID_REG(ID_REG_4_3) +DEFINE_READ_ID_REG(ID_AA64ZFR0) +DEFINE_READ_ID_REG(ID_REG_4_5) +DEFINE_READ_ID_REG(ID_REG_4_6) +DEFINE_READ_ID_REG(ID_REG_4_7) + +/* CRm=5 */ +DEFINE_READ_ID_REG(ID_AA64DFR0) +DEFINE_READ_ID_REG(ID_AA64DFR1) +DEFINE_READ_ID_REG(ID_REG_5_2) +DEFINE_READ_ID_REG(ID_REG_5_3) +DEFINE_READ_ID_REG(ID_AA64AFR0) +DEFINE_READ_ID_REG(ID_AA64AFR1) +DEFINE_READ_ID_REG(ID_REG_5_6) +DEFINE_READ_ID_REG(ID_REG_5_7) + +/* CRm=6 */ +DEFINE_READ_ID_REG(ID_AA64ISAR0) +DEFINE_READ_ID_REG(ID_AA64ISAR1) +DEFINE_READ_ID_REG(ID_REG_6_2) +DEFINE_READ_ID_REG(ID_REG_6_3) +DEFINE_READ_ID_REG(ID_REG_6_4) +DEFINE_READ_ID_REG(ID_REG_6_5) +DEFINE_READ_ID_REG(ID_REG_6_6) +DEFINE_READ_ID_REG(ID_REG_6_7) + +/* CRm=7 */ +DEFINE_READ_ID_REG(ID_AA64MMFR0) +DEFINE_READ_ID_REG(ID_AA64MMFR1) +DEFINE_READ_ID_REG(ID_AA64MMFR2) +DEFINE_READ_ID_REG(ID_REG_7_3) +DEFINE_READ_ID_REG(ID_REG_7_4) +DEFINE_READ_ID_REG(ID_REG_7_5) +DEFINE_READ_ID_REG(ID_REG_7_6) +DEFINE_READ_ID_REG(ID_REG_7_7) + +#define ID_IDX(name) REG_IDX_## name + +enum id_reg_idx { + /* CRm=1 */ + ID_IDX(ID_PFR0) = 0, + ID_IDX(ID_PFR1), + ID_IDX(ID_DFR0), + ID_IDX(ID_AFR0), + ID_IDX(ID_MMFR0), + ID_IDX(ID_MMFR1), + ID_IDX(ID_MMFR2), + ID_IDX(ID_MMFR3), + + /* CRm=2 */ + ID_IDX(ID_ISAR0), + ID_IDX(ID_ISAR1), + ID_IDX(ID_ISAR2), + ID_IDX(ID_ISAR3), + ID_IDX(ID_ISAR4), + ID_IDX(ID_ISAR5), + ID_IDX(ID_MMFR4), + ID_IDX(ID_ISAR6), + + /* CRm=3 */ + ID_IDX(MVFR0), + ID_IDX(MVFR1), + ID_IDX(MVFR2), + ID_IDX(ID_REG_3_3), + ID_IDX(ID_PFR2), + ID_IDX(ID_DFR1), + ID_IDX(ID_MMFR5), + ID_IDX(ID_REG_3_7), + + /* CRm=4 */ + ID_IDX(ID_AA64PFR0), + ID_IDX(ID_AA64PFR1), + ID_IDX(ID_REG_4_2), + ID_IDX(ID_REG_4_3), + ID_IDX(ID_AA64ZFR0), + ID_IDX(ID_REG_4_5), + ID_IDX(ID_REG_4_6), + ID_IDX(ID_REG_4_7), + + /* CRm=5 */ + ID_IDX(ID_AA64DFR0), + ID_IDX(ID_AA64DFR1), + ID_IDX(ID_REG_5_2), + ID_IDX(ID_REG_5_3), + ID_IDX(ID_AA64AFR0), + ID_IDX(ID_AA64AFR1), + ID_IDX(ID_REG_5_6), + ID_IDX(ID_REG_5_7), + + /* CRm=6 */ + ID_IDX(ID_AA64ISAR0), + ID_IDX(ID_AA64ISAR1), + ID_IDX(ID_REG_6_2), + ID_IDX(ID_REG_6_3), + ID_IDX(ID_REG_6_4), + ID_IDX(ID_REG_6_5), + ID_IDX(ID_REG_6_6), + ID_IDX(ID_REG_6_7), + + /* CRm=7 */ + ID_IDX(ID_AA64MMFR0), + ID_IDX(ID_AA64MMFR1), + ID_IDX(ID_AA64MMFR2), + ID_IDX(ID_REG_7_3), + ID_IDX(ID_REG_7_4), + ID_IDX(ID_REG_7_5), + ID_IDX(ID_REG_7_6), + ID_IDX(ID_REG_7_7), +}; + +struct id_reg_test_info { + char *name; + uint32_t id; + /* Indicates the register can be set to 0 */ + bool can_clear; + uint64_t initial_value; + uint64_t current_value; + uint64_t (*read_reg)(void); +}; + +#define ID_REG_INFO(name) (&id_reg_list[ID_IDX(name)]) +static struct id_reg_test_info id_reg_list[] = { + /* CRm=1 */ + ID_REG_ENT(ID_PFR0), + ID_REG_ENT(ID_PFR1), + ID_REG_ENT(ID_DFR0), + ID_REG_ENT(ID_AFR0), + ID_REG_ENT(ID_MMFR0), + ID_REG_ENT(ID_MMFR1), + ID_REG_ENT(ID_MMFR2), + ID_REG_ENT(ID_MMFR3), + + /* CRm=2 */ + ID_REG_ENT(ID_ISAR0), + ID_REG_ENT(ID_ISAR1), + ID_REG_ENT(ID_ISAR2), + ID_REG_ENT(ID_ISAR3), + ID_REG_ENT(ID_ISAR4), + ID_REG_ENT(ID_ISAR5), + ID_REG_ENT(ID_MMFR4), + ID_REG_ENT(ID_ISAR6), + + /* CRm=3 */ + ID_REG_ENT(MVFR0), + ID_REG_ENT(MVFR1), + ID_REG_ENT(MVFR2), + ID_REG_ENT(ID_REG_3_3), + ID_REG_ENT(ID_PFR2), + ID_REG_ENT(ID_DFR1), + ID_REG_ENT(ID_MMFR5), + ID_REG_ENT(ID_REG_3_7), + + /* CRm=4 */ + ID_REG_ENT(ID_AA64PFR0), + ID_REG_ENT(ID_AA64PFR1), + ID_REG_ENT(ID_REG_4_2), + ID_REG_ENT(ID_REG_4_3), + ID_REG_ENT(ID_AA64ZFR0), + ID_REG_ENT(ID_REG_4_5), + ID_REG_ENT(ID_REG_4_6), + ID_REG_ENT(ID_REG_4_7), + + /* CRm=5 */ + ID_REG_ENT(ID_AA64DFR0), + ID_REG_ENT(ID_AA64DFR1), + ID_REG_ENT(ID_REG_5_2), + ID_REG_ENT(ID_REG_5_3), + ID_REG_ENT(ID_AA64AFR0), + ID_REG_ENT(ID_AA64AFR1), + ID_REG_ENT(ID_REG_5_6), + ID_REG_ENT(ID_REG_5_7), + + /* CRm=6 */ + ID_REG_ENT(ID_AA64ISAR0), + ID_REG_ENT(ID_AA64ISAR1), + ID_REG_ENT(ID_REG_6_2), + ID_REG_ENT(ID_REG_6_3), + ID_REG_ENT(ID_REG_6_4), + ID_REG_ENT(ID_REG_6_5), + ID_REG_ENT(ID_REG_6_6), + ID_REG_ENT(ID_REG_6_7), + + /* CRm=7 */ + ID_REG_ENT(ID_AA64MMFR0), + ID_REG_ENT(ID_AA64MMFR1), + ID_REG_ENT(ID_AA64MMFR2), + ID_REG_ENT(ID_REG_7_3), + ID_REG_ENT(ID_REG_7_4), + ID_REG_ENT(ID_REG_7_5), + ID_REG_ENT(ID_REG_7_6), + ID_REG_ENT(ID_REG_7_7), +}; + +static bool aarch32_support = true; + +#define is_id_reg(id) \ + (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && \ + sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 0 && \ + sys_reg_CRm(id) < 8) + +#define UPDATE_ID_UFIELD(regval, shift, fval) \ + (((regval) & ~(0xfULL << (shift))) | \ + (((uint64_t)((fval) & 0xf)) << (shift))) + +void *pmu_init(struct kvm_vm *vm, uint32_t vcpu) +{ + struct kvm_device_attr attr = { + .group = KVM_ARM_VCPU_PMU_V3_CTRL, + .attr = KVM_ARM_VCPU_PMU_V3_INIT, + }; + + vcpu_ioctl(vm, vcpu, KVM_SET_DEVICE_ATTR, &attr); + return NULL; +} + +void *sve_init(struct kvm_vm *vm, uint32_t vcpu) +{ + int feature = KVM_ARM_VCPU_SVE; + + vcpu_ioctl(vm, vcpu, KVM_ARM_VCPU_FINALIZE, &feature); + return NULL; +} + +#define GICD_BASE_GPA 0x8000000ULL +#define GICR_BASE_GPA 0x80A0000ULL + +void *vgic_init(struct kvm_vm *vm, uint32_t vcpu) +{ + /* We jsut need to configure gic v3 (we don't use it though) */ + int gic_fd = vgic_v3_setup(vm, 1, 64, GICD_BASE_GPA, GICR_BASE_GPA); + + return (void *)(intptr_t)gic_fd; +} + +void vgic_fini(struct kvm_vm *vm, uint32_t vcpu, void *data) +{ + close((int)(intptr_t)data); +} + + +static bool is_aarch32_id_reg(uint32_t id) +{ + uint32_t crm, op2; + + if (!is_id_reg(id)) + return false; + + crm = sys_reg_CRm(id); + op2 = sys_reg_Op2(id); + if (crm == 1 || crm == 2 || (crm == 3 && (op2 != 3 && op2 != 7))) + /* AArch32 ID register */ + return true; + + return false; +} + +#define MAX_CAPS 2 +struct feature_test_info { + char *name; /* Feature Name (Debug information) */ + + /* ID register that identifies the presence of the feature */ + struct id_reg_test_info *sreg; + + /* + * Bit position of the ID register field that identifies + * the presence of the feature. + */ + int shift; + + /* Min value of the field that indicates the presence of the feature. */ + int min; + bool is_sign; /* Is the field signed or unsigned ? */ + int ncaps; /* Number of valid Capabilities in caps[] */ + + /* KVM_CAP_* Capabilities to indicates that KVM supports this feature */ + long caps[MAX_CAPS]; + + /* struct kvm_enable_cap to use the capability if needed */ + struct kvm_enable_cap *opt_in_cap; + + /* Should the guest check the ID register for this feature ? */ + bool run_test; + + /* + * Extra initialization function to enable the feature if needed. + * (e.g. KVM_ARM_VCPU_FINALIZE for SVE) + * The return value of this function will be passed to fini_feature(). + */ + void *(*init_feature)(struct kvm_vm *vm, uint32_t vcpuid); + + /* + * Clean up anything that init_feature() initialized or allocated + * as needed. The 'data' is the return value from init_feature(). + */ + void (*fini_feature)(struct kvm_vm *vm, uint32_t vcpuid, void *data); + + /* struct kvm_vcpu_init to opt-in the feature if needed */ + struct kvm_vcpu_init *vcpu_init; + + /* Extra feature specific tests */ + void (*test_feature)(struct feature_test_info *finfo); +}; + +static void pmu_test(struct feature_test_info *finfo); + +/* Information for opt-in CPU features */ +static struct feature_test_info feature_test_info_table[] = { + { + .name = "SVE", + .sreg = ID_REG_INFO(ID_AA64PFR0), + .shift = ID_AA64PFR0_SVE_SHIFT, + .min = 1, + .caps = {KVM_CAP_ARM_SVE}, + .ncaps = 1, + .init_feature = sve_init, + .vcpu_init = &(struct kvm_vcpu_init) { + .features = {1ULL << KVM_ARM_VCPU_SVE}, + }, + }, + { + .name = "GIC", + .sreg = ID_REG_INFO(ID_AA64PFR0), + .shift = ID_AA64PFR0_GIC_SHIFT, + .min = 1, + .caps = {KVM_CAP_IRQCHIP}, + .ncaps = 1, + .init_feature = vgic_init, + .fini_feature = vgic_fini, + }, + { + .name = "MTE", + .sreg = ID_REG_INFO(ID_AA64PFR1), + .shift = ID_AA64PFR1_MTE_SHIFT, + .min = 2, + .caps = {KVM_CAP_ARM_MTE}, + .ncaps = 1, + .opt_in_cap = &(struct kvm_enable_cap) { + .cap = KVM_CAP_ARM_MTE, + }, + }, + { + .name = "PMUV3", + .sreg = ID_REG_INFO(ID_AA64DFR0), + .shift = ID_AA64DFR0_PMUVER_SHIFT, + .min = 1, + .init_feature = pmu_init, + .test_feature = pmu_test, + .caps = {KVM_CAP_ARM_PMU_V3}, + .ncaps = 1, + .vcpu_init = &(struct kvm_vcpu_init) { + .features = {1ULL << KVM_ARM_VCPU_PMU_V3}, + }, + }, + { + .name = "PERFMON", + .sreg = ID_REG_INFO(ID_DFR0), + .shift = ID_DFR0_PERFMON_SHIFT, + .min = 3, + .init_feature = pmu_init, + .test_feature = pmu_test, + .caps = {KVM_CAP_ARM_PMU_V3}, + .ncaps = 1, + .vcpu_init = &(struct kvm_vcpu_init) { + .features = {1ULL << KVM_ARM_VCPU_PMU_V3}, + }, + }, +}; + +static void walk_id_reg_list(void (*fn)(struct id_reg_test_info *r, void *arg), + void *arg) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(id_reg_list); i++) + fn(&id_reg_list[i], arg); +} + +static void guest_code_id_reg_check_one(struct id_reg_test_info *idr, void *arg) +{ + uint64_t v = idr->read_reg(); + + GUEST_ASSERT_2(v == idr->current_value, idr->name, idr->current_value); +} + +static void guest_code_id_reg_check_all(uint32_t cpu) +{ + walk_id_reg_list(guest_code_id_reg_check_one, NULL); + GUEST_DONE(); +} + +static void guest_code_do_nothing(uint32_t cpu) +{ + GUEST_DONE(); +} + +static void guest_code_feature_check(uint32_t cpu) +{ + int i; + struct feature_test_info *finfo; + + for (i = 0; i < ARRAY_SIZE(feature_test_info_table); i++) { + finfo = &feature_test_info_table[i]; + if (finfo->run_test) + guest_code_id_reg_check_one(finfo->sreg, NULL); + } + + GUEST_DONE(); +} + +static void guest_code_ptrauth_check(uint32_t cpuid) +{ + struct id_reg_test_info *sreg = ID_REG_INFO(ID_AA64ISAR1); + uint64_t val = sreg->read_reg(); + + GUEST_ASSERT_2(val == sreg->current_value, "PTRAUTH", val); + GUEST_DONE(); +} + +static void reset_id_reg_info_current_value(struct id_reg_test_info *info, + void *arg) +{ + info->current_value = info->initial_value; +} + +/* Reset current_value field of each id_reg_test_info */ +static void reset_id_reg_info(void) +{ + walk_id_reg_list(reset_id_reg_info_current_value, NULL); +} + +static struct kvm_vm *test_vm_create(uint32_t nvcpus, + void (*guest_code)(uint32_t), struct kvm_vcpu_init *init, + struct kvm_enable_cap *cap) +{ + struct kvm_vm *vm; + uint32_t cpuid; + uint64_t mem_pages; + + mem_pages = DEFAULT_GUEST_PHY_PAGES + DEFAULT_STACK_PGS * nvcpus; + mem_pages += mem_pages / (PTES_PER_MIN_PAGE * 2); + mem_pages = vm_adjust_num_guest_pages(VM_MODE_DEFAULT, mem_pages); + + vm = vm_create(VM_MODE_DEFAULT, mem_pages, O_RDWR); + if (cap) + vm_enable_cap(vm, cap); + + kvm_vm_elf_load(vm, program_invocation_name); + + if (init && init->target == -1) { + struct kvm_vcpu_init preferred; + + vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &preferred); + init->target = preferred.target; + } + + vm_init_descriptor_tables(vm); + for (cpuid = 0; cpuid < nvcpus; cpuid++) { + aarch64_vcpu_add_default(vm, cpuid, init, guest_code); + vcpu_init_descriptor_tables(vm, cpuid); + } + + ucall_init(vm, NULL); + return vm; +} + +static void test_vm_free(struct kvm_vm *vm) +{ + ucall_uninit(vm); + kvm_vm_free(vm); +} + +#define TEST_RUN(vm, cpu) \ + (test_vcpu_run(__func__, __LINE__, vm, cpu, true)) + +#define TEST_RUN_NO_SYNC_DATA(vm, cpu) \ + (test_vcpu_run(__func__, __LINE__, vm, cpu, false)) + +static int test_vcpu_run(const char *test_name, int line, + struct kvm_vm *vm, uint32_t vcpuid, bool sync_data) +{ + struct ucall uc; + int ret; + + if (sync_data) { + sync_global_to_guest(vm, id_reg_list); + sync_global_to_guest(vm, feature_test_info_table); + } + + vcpu_args_set(vm, vcpuid, 1, vcpuid); + + ret = _vcpu_run(vm, vcpuid); + if (ret) { + ret = errno; + goto sync_exit; + } + + switch (get_ucall(vm, vcpuid, &uc)) { + case UCALL_SYNC: + case UCALL_DONE: + ret = 0; + break; + case UCALL_ABORT: + TEST_FAIL( + "%s (%s) at line %d (user %s at line %d), args[3]=0x%lx", + (char *)uc.args[0], (char *)uc.args[2], (int)uc.args[1], + test_name, line, uc.args[3]); + break; + default: + TEST_FAIL("Unexpected guest exit\n"); + } + +sync_exit: + if (sync_data) { + sync_global_from_guest(vm, id_reg_list); + sync_global_from_guest(vm, feature_test_info_table); + } + return ret; +} + +/* + * Test KVM's special handling for ID_AA64DFR0.PMUVER/DFR0.PERFMON, which + * is ignoring userspace's request to set the fields to 0xf (IMPLEMENTATION + * DEFINED PMU) and setting the field to 0 instead. This KVM's implementation + * is to make live migration work from the older KVM, which erroneously sets + * those fields to 0xf for the guest when their host sanitized value are + * 0xf (it should have been set to 0x0 as the KVM doesn't support + * IMPLEMENTATION DEFINED PMU for the guest). + */ +static void pmu_test(struct feature_test_info *finfo) +{ + struct id_reg_test_info *sreg = finfo->sreg; + struct kvm_one_reg one_reg; + struct kvm_vm *vm; + int64_t fval, reg_val; + uint32_t vcpu = 0; + int ret; + + reset_id_reg_info(); + finfo->run_test = 1; + + vm = test_vm_create(1, guest_code_feature_check, NULL, NULL); + + /* Make sure that ID_AA64DFR0.PMUVER/DFR0.PERFMON is 0. */ + one_reg.addr = (uint64_t)®_val; + one_reg.id = KVM_ARM64_SYS_REG(sreg->id); + vcpu_ioctl(vm, vcpu, KVM_GET_ONE_REG, &one_reg); + fval = cpuid_extract_ftr(reg_val, finfo->shift, finfo->is_sign); + TEST_ASSERT(fval == 0, "%s field of %s should be initially 0 but %ld", + finfo->name, sreg->name, fval); + + /* Try to set ID_AA64DFR0.PMUVER/DFR0.PERFMON to -1 (0xf). */ + fval = -1; + reg_val = UPDATE_ID_UFIELD(reg_val, finfo->shift, fval); + ret = _vcpu_ioctl(vm, vcpu, KVM_SET_ONE_REG, &one_reg); + TEST_ASSERT(ret == 0, "Setting %s field of %s to %ld failed (%d)\n", + finfo->name, sreg->name, fval, ret); + + /* Check if ID_AA64DFR0.PMUVER/DFR0.PERFMON is still 0. */ + vcpu_ioctl(vm, vcpu, KVM_GET_ONE_REG, &one_reg); + fval = cpuid_extract_ftr(reg_val, finfo->shift, finfo->is_sign); + TEST_ASSERT(fval == 0, "%s field of %s should be 0 but %ld", + finfo->name, sreg->name, fval); + + sreg->current_value = reg_val; + ret = TEST_RUN(vm, vcpu); + finfo->run_test = 0; + test_vm_free(vm); +} + +struct vm_vcpu_arg { + struct kvm_vm *vm; + uint32_t vcpuid; + bool after_run; +}; + +/* + * Test if KVM_SET_ONE_REG can work with the value KVM_GET_ONE_REG returns, + * KVM_SET_ONE_REG with zero works before KVM_RUN (and fails after KVM_RUN), + * and KVM_GET_ONE_REG returns the value KVM_SET_ONE_REG sets. + */ +static void test_get_set_id_reg(struct id_reg_test_info *sreg, void *arg) +{ + struct kvm_vm *vm = ((struct vm_vcpu_arg *)arg)->vm; + uint32_t vcpuid = ((struct vm_vcpu_arg *)arg)->vcpuid; + bool after_run = ((struct vm_vcpu_arg *)arg)->after_run; + struct kvm_one_reg one_reg; + uint64_t reg_val, tval; + int ret; + + one_reg.addr = (uint64_t)®_val; + one_reg.id = KVM_ARM64_SYS_REG(sreg->id); + + /* Check the current register value */ + vcpu_ioctl(vm, vcpuid, KVM_GET_ONE_REG, &one_reg); + TEST_ASSERT(reg_val == sreg->current_value, + "GET(%s) didn't return 0x%lx but 0x%lx", + sreg->name, sreg->current_value, reg_val); + tval = reg_val; + + /* Try to clear the register that should be able to be cleared. */ + if ((reg_val != 0) && (sreg->can_clear)) { + reg_val = 0; + ret = _vcpu_ioctl(vm, vcpuid, KVM_SET_ONE_REG, &one_reg); + if (after_run) { + /* Expect an error after KVM_RUN */ + TEST_ASSERT(ret, + "Clearing %s unexpectedly worked\n", + sreg->name); + } else { + TEST_ASSERT(!ret, + "Clearing %s didn't work\n", sreg->name); + /* + * Make sure that KVM_GET_ONE_REG provides the value + * we set. + */ + vcpu_ioctl(vm, vcpuid, KVM_GET_ONE_REG, &one_reg); + TEST_ASSERT(reg_val == 0, + "GET(%s) didn't return 0x%lx but 0x%lx", + sreg->name, (uint64_t)0, reg_val); + } + } + + /* Check if KVM_SET_ONE_REG works with the original value. */ + reg_val = tval; + ret = _vcpu_ioctl(vm, vcpuid, KVM_SET_ONE_REG, &one_reg); + TEST_ASSERT(ret == 0, "Setting the same ID reg value should work\n"); + + /* Make sure that KVM_GET_ONE_REG provides the value we set. */ + vcpu_ioctl(vm, vcpuid, KVM_GET_ONE_REG, &one_reg); + TEST_ASSERT(reg_val == tval, + "GET(%s) didn't return 0x%lx but 0x%lx", + sreg->name, sreg->current_value, reg_val); +} + +/* + * Test if KVM_SET_ONE_REG with the current value works before KVM_RUN, + * values of ID registers the guest sees are consistent with the ones + * userspace sees, and KVM_SET_ONE_REG after KVM_RUN works when the + * specified value is the same as the current one (fails otherwise). + */ +static void test_id_regs_basic(void) +{ + struct kvm_vm *vm; + struct vm_vcpu_arg arg = { .vcpuid = 0 }; + int ret; + + reset_id_reg_info(); + + vm = test_vm_create(1, guest_code_id_reg_check_all, NULL, NULL); + + arg.vm = vm; + walk_id_reg_list(test_get_set_id_reg, &arg); + + ret = TEST_RUN(vm, 0); + assert(!ret); + + arg.after_run = true; + walk_id_reg_list(test_get_set_id_reg, &arg); + + test_vm_free(vm); +} + +static bool caps_are_supported(long *caps, int ncaps) +{ + int i; + + for (i = 0; i < ncaps; i++) { + if (kvm_check_cap(caps[i]) <= 0) + return false; + } + return true; +} + +#define NCAPS_PTRAUTH 2 + +/* + * Test if the ID register value reflects the ptrauth feature configuration. + * KVM_SET_ONE_REG should work as long as the requested value is consistent + * with the ptrauth feature configuration. + */ +static void test_feature_ptrauth(void) +{ + struct kvm_one_reg one_reg; + struct kvm_vcpu_init init; + struct kvm_vm *vm = NULL; + struct id_reg_test_info *sreg = ID_REG_INFO(ID_AA64ISAR1); + uint32_t vcpu = 0; + int64_t rval; + int ret; + int apa, api, gpa, gpi; + char *name = "PTRAUTH"; + long caps[NCAPS_PTRAUTH] = {KVM_CAP_ARM_PTRAUTH_ADDRESS, + KVM_CAP_ARM_PTRAUTH_GENERIC}; + + reset_id_reg_info(); + one_reg.addr = (uint64_t)&rval; + one_reg.id = KVM_ARM64_SYS_REG(sreg->id); + + if (caps_are_supported(caps, NCAPS_PTRAUTH)) { + + /* Test with feature enabled */ + memset(&init, 0, sizeof(init)); + init.target = -1; + init.features[0] = (1ULL << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1ULL << KVM_ARM_VCPU_PTRAUTH_GENERIC); + vm = test_vm_create(1, guest_code_ptrauth_check, &init, NULL); + vcpu_ioctl(vm, vcpu, KVM_GET_ONE_REG, &one_reg); + + /* Make sure values of apa/api/gpa/gpi fields are expected */ + apa = cpuid_extract_uftr(rval, ID_AA64ISAR1_APA_SHIFT); + api = cpuid_extract_uftr(rval, ID_AA64ISAR1_API_SHIFT); + gpa = cpuid_extract_uftr(rval, ID_AA64ISAR1_GPA_SHIFT); + gpi = cpuid_extract_uftr(rval, ID_AA64ISAR1_GPI_SHIFT); + + TEST_ASSERT((apa > 0) || (api > 0), + "Either apa(0x%x) or api(0x%x) must be available", + apa, gpa); + TEST_ASSERT((gpa > 0) || (gpi > 0), + "Either gpa(0x%x) or gpi(0x%x) must be available", + gpa, gpi); + + TEST_ASSERT((apa > 0) ^ (api > 0), + "Both apa(0x%x) and api(0x%x) must not be available", + apa, api); + TEST_ASSERT((gpa > 0) ^ (gpi > 0), + "Both gpa(0x%x) and gpi(0x%x) must not be available", + gpa, gpi); + + sreg->current_value = rval; + + pr_debug("%s: Test with %s enabled (%s: 0x%lx)\n", + __func__, name, sreg->name, sreg->current_value); + + /* Make sure that the guest sees the same ID register value. */ + ret = TEST_RUN(vm, vcpu); + + TEST_ASSERT(!ret, "%s:KVM_RUN failed with %s enabled", + __func__, name); + test_vm_free(vm); + } + + reset_id_reg_info(); + + /* Test with feature disabled */ + vm = test_vm_create(1, guest_code_feature_check, NULL, NULL); + vcpu_ioctl(vm, vcpu, KVM_GET_ONE_REG, &one_reg); + + apa = cpuid_extract_uftr(rval, ID_AA64ISAR1_APA_SHIFT); + api = cpuid_extract_uftr(rval, ID_AA64ISAR1_API_SHIFT); + gpa = cpuid_extract_uftr(rval, ID_AA64ISAR1_GPA_SHIFT); + gpi = cpuid_extract_uftr(rval, ID_AA64ISAR1_GPI_SHIFT); + TEST_ASSERT(!apa && !api && !gpa && !gpi, + "apa(0x%x), api(0x%x), gpa(0x%x), gpi(0x%x) must be zero", + apa, api, gpa, gpi); + + pr_debug("%s: Test with %s disabled (%s: 0x%lx)\n", + __func__, name, sreg->name, sreg->current_value); + + /* Make sure that the guest sees the same ID register value. */ + ret = TEST_RUN(vm, vcpu); + TEST_ASSERT(!ret, "%s TEST_RUN failed with %s enabled, ret=0x%x", + __func__, name, ret); + + test_vm_free(vm); +} + +static bool feature_caps_are_available(struct feature_test_info *finfo) +{ + return ((finfo->ncaps > 0) && + caps_are_supported(finfo->caps, finfo->ncaps)); +} + +/* + * Test if the ID register value reflects the feature configuration. + * KVM_SET_ONE_REG should work as long as the requested value is + * consistent with the feature configuration. + */ +static void test_feature(struct feature_test_info *finfo) +{ + struct id_reg_test_info *sreg = finfo->sreg; + struct kvm_one_reg one_reg; + struct kvm_vcpu_init init, *initp = NULL; + struct kvm_vm *vm = NULL; + int64_t fval, reg_val; + uint32_t vcpu = 0; + bool is_sign = finfo->is_sign; + int min = finfo->min; + int shift = finfo->shift; + int ret; + void *data = NULL; + + pr_debug("%s: %s (reg %s)\n", __func__, finfo->name, sreg->name); + + reset_id_reg_info(); + + if (is_aarch32_id_reg(sreg->id) && !aarch32_support) + /* + * AArch32 is not supported. Skip testing with the AArch32 + * ID register. + */ + return; + + /* Indicate that guest runs the test for the feature */ + finfo->run_test = 1; + one_reg.addr = (uint64_t)®_val; + one_reg.id = KVM_ARM64_SYS_REG(sreg->id); + + /* + * Test with feature enabled if the feature is exposed in the default + * ID register value or the capabilities are supported at KVM level. + */ + if ((cpuid_extract_ftr(sreg->initial_value, shift, is_sign) >= min) || + feature_caps_are_available(finfo)) { + if (finfo->vcpu_init) { + /* Need to enable the feature via KVM_ARM_VCPU_INIT. */ + memset(&init, 0, sizeof(init)); + init = *finfo->vcpu_init; + init.target = -1; + initp = &init; + } + + vm = test_vm_create(1, guest_code_feature_check, initp, + finfo->opt_in_cap); + if (finfo->init_feature) + /* Run any required extra process to use the feature */ + data = finfo->init_feature(vm, vcpu); + + /* Check if the ID register value indicates the feature */ + vcpu_ioctl(vm, vcpu, KVM_GET_ONE_REG, &one_reg); + fval = cpuid_extract_ftr(reg_val, shift, is_sign); + TEST_ASSERT(fval >= min, "%s field of %s is too small (%ld)", + finfo->name, sreg->name, fval); + sreg->current_value = reg_val; + + pr_debug("%s: Test with %s enabled (%s: 0x%lx)\n", __func__, + finfo->name, sreg->name, sreg->current_value); + + /* Make sure that the guest sees the same ID register value. */ + ret = TEST_RUN(vm, vcpu); + TEST_ASSERT(!ret, "%s:TEST_RUN failed with %s enabled", + __func__, finfo->name); + + if (finfo->fini_feature) + finfo->fini_feature(vm, vcpu, data); + + test_vm_free(vm); + } + + reset_id_reg_info(); + + /* Test with feature disabled */ + vm = test_vm_create(1, guest_code_feature_check, NULL, NULL); + vcpu_ioctl(vm, vcpu, KVM_GET_ONE_REG, &one_reg); + fval = cpuid_extract_ftr(reg_val, shift, is_sign); + if (finfo->vcpu_init || finfo->opt_in_cap) { + /* + * If the feature needs to be enabled with KVM_ARM_VCPU_INIT + * or opt-in capabilities, the default value of the ID register + * shouldn't indicate the feature. + */ + TEST_ASSERT(fval < min, "%s field of %s is too big (%ld)", + finfo->name, sreg->name, fval); + } else { + /* Update the relevant field to hide the feature. */ + fval = is_sign ? 0xf : 0x0; + reg_val = UPDATE_ID_UFIELD(reg_val, shift, fval); + ret = _vcpu_ioctl(vm, vcpu, KVM_SET_ONE_REG, &one_reg); + TEST_ASSERT(ret == 0, "Disabling %s failed %d (err %d)\n", + finfo->name, ret, errno); + sreg->current_value = reg_val; + } + + pr_debug("%s: Test with %s disabled (%s: 0x%lx)\n", + __func__, finfo->name, sreg->name, sreg->current_value); + + /* Make sure that the guest sees the same ID register value. */ + ret = TEST_RUN(vm, vcpu); + TEST_ASSERT(!ret, "%s:TEST_RUN failed with %s disabled", + __func__, finfo->name); + finfo->run_test = 0; + test_vm_free(vm); + + /* Run extra feature specific tests, if any */ + if (finfo->test_feature) + finfo->test_feature(finfo); +} + +/* + * For each opt-in feature in feature_test_info_table[], + * test if KVM_GET_ONE_REG/KVM_SET_ONE_REG works appropriately according + * to the feature configuration. See test_feature's comment for more detail. + */ +static void test_feature_all(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(feature_test_info_table); i++) + test_feature(&feature_test_info_table[i]); +} + +int set_id_reg(struct kvm_vm *vm, uint32_t vcpu, struct id_reg_test_info *sreg, + uint64_t new_val) +{ + int ret; + uint64_t reg_val; + struct kvm_one_reg one_reg; + + one_reg.id = KVM_ARM64_SYS_REG(sreg->id); + one_reg.addr = (uint64_t)®_val; + + reg_val = new_val; + ret = _vcpu_ioctl(vm, vcpu, KVM_SET_ONE_REG, &one_reg); + if (!ret) + sreg->current_value = new_val; + + return ret; +} + + +/* + * Create a new VM with one vCPU, set the ID register to @new_val. + */ +int set_id_reg_vm(struct id_reg_test_info *sreg, uint64_t new_val) +{ + struct kvm_vm *vm; + int ret; + uint32_t vcpu = 0; + + reset_id_reg_info(); + + vm = test_vm_create(1, guest_code_id_reg_check_all, NULL, NULL); + ret = set_id_reg(vm, vcpu, sreg, new_val); + test_vm_free(vm); + + return ret; +} + +struct frac_info { + char *name; + struct id_reg_test_info *sreg; + struct id_reg_test_info *frac_sreg; + int shift; + int frac_shift; +}; + +struct frac_info frac_info_table[] = { + { + .name = "RAS", + .sreg = ID_REG_INFO(ID_AA64PFR0), + .shift = ID_AA64PFR0_RAS_SHIFT, + .frac_sreg = ID_REG_INFO(ID_AA64PFR1), + .frac_shift = ID_AA64PFR1_RASFRAC_SHIFT, + }, + { + .name = "MPAM", + .sreg = ID_REG_INFO(ID_AA64PFR0), + .shift = ID_AA64PFR0_MPAM_SHIFT, + .frac_sreg = ID_REG_INFO(ID_AA64PFR1), + .frac_shift = ID_AA64PFR1_MPAMFRAC_SHIFT, + }, + { + .name = "CSV2", + .sreg = ID_REG_INFO(ID_AA64PFR0), + .shift = ID_AA64PFR0_CSV2_SHIFT, + .frac_sreg = ID_REG_INFO(ID_AA64PFR1), + .frac_shift = ID_AA64PFR1_CSV2FRAC_SHIFT, + }, +}; + + +/* + * Make sure that we can set the fractional reg field even before setting + * the feature reg field. + */ +int test_feature_frac_vm(struct frac_info *frac, uint64_t new_val, + uint64_t frac_new_val) +{ + struct kvm_vm *vm; + uint32_t vcpu = 0; + struct id_reg_test_info *sreg, *frac_sreg; + int ret; + + sreg = frac->sreg; + frac_sreg = frac->frac_sreg; + reset_id_reg_info(); + + vm = test_vm_create(1, guest_code_id_reg_check_all, NULL, NULL); + + /* Set fractional reg field */ + ret = set_id_reg(vm, vcpu, frac_sreg, frac_new_val); + TEST_ASSERT(!ret, "SET_REG(%s=0x%lx) failed, ret=0x%x", + frac_sreg->name, frac_new_val, ret); + + /* Set feature reg field */ + ret = set_id_reg(vm, vcpu, sreg, new_val); + TEST_ASSERT(!ret, "SET_REG(%s=0x%lx) failed, ret=0x%x", + sreg->name, new_val, ret); + + ret = TEST_RUN(vm, vcpu); + test_vm_free(vm); + + return ret; +} + +/* + * Test for setting the feature fractional field of the ID register. + * When the (main) feature field of the ID register is the same as the host's, + * the fractional field value cannot be larger than the host's. + * (KVM_SET_ONE_REG should work but KVM_RUN with the larger value will fail) + * When the (main) feature field of the ID register is smaler than the host's, + * the fractional field can be any values. + * The function tests those behaviors. + */ +void test_feature_frac_one(struct frac_info *frac) +{ + uint64_t ftr_val, ftr_fval, frac_val, frac_fval; + int ret, shift, frac_shift; + struct id_reg_test_info *sreg, *frac_sreg; + + reset_id_reg_info(); + + sreg = frac->sreg; + shift = frac->shift; + frac_sreg = frac->frac_sreg; + frac_shift = frac->frac_shift; + + pr_debug("%s(%s Frac) reg:%s(shift:%d) frac reg:%s(shift:%d)\n", + __func__, frac->name, sreg->name, shift, frac_sreg->name, + frac_shift); + + /* + * Use the host's feature value for the guest. + * KVM_RUN with a larger frac value than the host's should fail. + * Otherwise, it should work. + */ + + frac_fval = cpuid_extract_uftr(frac_sreg->initial_value, frac_shift); + if (frac_fval > 0) { + /* Test with smaller frac value */ + frac_val = UPDATE_ID_UFIELD(frac_sreg->initial_value, + frac_shift, frac_fval - 1); + ret = test_feature_frac_vm(frac, sreg->initial_value, frac_val); + TEST_ASSERT(!ret, "Test smaller %s frac (val:%lx) failed(%d)", + frac->name, frac_val, ret); + } + + reset_id_reg_info(); + + if (frac_fval != 0xf) { + /* Test with larger frac value */ + frac_val = UPDATE_ID_UFIELD(frac_sreg->initial_value, + frac_shift, frac_fval + 1); + + /* Setting larger frac shouldn't fail at ioctl */ + ret = set_id_reg_vm(frac_sreg, frac_val); + TEST_ASSERT(!ret, + "SET larger %s frac (%s org:%lx, val:%lx) failed(%d)", + frac->name, frac_sreg->name, frac_sreg->initial_value, + frac_val, ret); + + /* KVM_RUN with larger frac should fail */ + ret = test_feature_frac_vm(frac, sreg->initial_value, frac_val); + TEST_ASSERT(ret, + "Test with larger %s frac (%s org:%lx, val:%lx) worked", + frac->name, frac_sreg->name, frac_sreg->initial_value, + frac_val); + } + + reset_id_reg_info(); + + /* + * Test with a smaller (main) feature value than the host's. + */ + ftr_fval = cpuid_extract_uftr(sreg->initial_value, shift); + if (ftr_fval == 0) + /* Cannot set it to the smaller value */ + return; + + ftr_val = UPDATE_ID_UFIELD(sreg->initial_value, shift, ftr_fval - 1); + ret = test_feature_frac_vm(frac, ftr_val, frac_sreg->initial_value); + TEST_ASSERT(!ret, "Test with smaller %s (val:%lx) failed(%d)", + frac->name, ftr_val, ret); + + if (frac_fval > 0) { + /* Test with smaller frac value */ + frac_val = UPDATE_ID_UFIELD(frac_sreg->initial_value, + frac_shift, frac_fval - 1); + ret = test_feature_frac_vm(frac, ftr_val, frac_val); + TEST_ASSERT(!ret, + "Test with smaller %s and frac (val:%lx) failed(%d)", + frac->name, ftr_val, ret); + } + + if (frac_fval != 0xf) { + /* Test with larger frac value */ + frac_val = UPDATE_ID_UFIELD(frac_sreg->initial_value, + frac_shift, frac_fval + 1); + ret = test_feature_frac_vm(frac, ftr_val, frac_val); + TEST_ASSERT(!ret, + "Test with smaller %s and larger frac (val:%lx) failed(%d)", + frac->name, ftr_val, ret); + } +} + +/* + * Test for setting feature fractional fields of ID registers. + * See test_feature_frac_one's comments for more detail. + */ +void test_feature_frac_all(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(frac_info_table); i++) + test_feature_frac_one(&frac_info_table[i]); +} + +void run_test(void) +{ + test_id_regs_basic(); + test_feature_all(); + test_feature_ptrauth(); + test_feature_frac_all(); +} + +static void init_id_reg_info_one(struct id_reg_test_info *sreg, void *arg) +{ + struct kvm_one_reg one_reg; + uint64_t reg_val; + struct kvm_vm *vm = ((struct vm_vcpu_arg *)arg)->vm; + uint32_t vcpuid = ((struct vm_vcpu_arg *)arg)->vcpuid; + int ret; + + one_reg.addr = (uint64_t)®_val; + one_reg.id = KVM_ARM64_SYS_REG(sreg->id); + vcpu_ioctl(vm, vcpuid, KVM_GET_ONE_REG, &one_reg); + sreg->current_value = reg_val; + + /* Keep the initial value to reset the register value later */ + sreg->initial_value = reg_val; + + /* Check if the register can be set to 0 */ + reg_val = 0; + ret = _vcpu_ioctl(vm, vcpuid, KVM_SET_ONE_REG, &one_reg); + if (!ret) + sreg->can_clear = true; + + pr_debug("%s (0x%x): 0x%lx%s\n", sreg->name, sreg->id, + sreg->initial_value, sreg->can_clear ? ", can clear" : ""); +} + +/* + * Check if aarch32 is supported, and initialize id_reg_test_info for all + * the ID registers. Loop over the idreg list and populates each id_reg + * info with the initial value, current value, and can_clear value. + */ +static void init_test_info(void) +{ + uint64_t reg_val; + int fval; + struct kvm_vm *vm; + struct kvm_one_reg one_reg; + struct vm_vcpu_arg arg = { .vcpuid = 0 }; + + vm = test_vm_create(1, guest_code_do_nothing, NULL, NULL); + + /* Get ID_AA64PFR0_EL1 to check if AArch32 is supported */ + one_reg.addr = (uint64_t)®_val; + one_reg.id = KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1); + vcpu_ioctl(vm, 0, KVM_GET_ONE_REG, &one_reg); + fval = cpuid_extract_uftr(reg_val, ID_AA64PFR0_EL0_SHIFT); + if (fval == 0x1) + /* No AArch32 support */ + aarch32_support = false; + + /* Initialize id_reg_test_info */ + arg.vm = vm; + walk_id_reg_list(init_id_reg_info_one, &arg); + test_vm_free(vm); +} + +int main(void) +{ + + setbuf(stdout, NULL); + + if (kvm_check_cap(KVM_CAP_ARM_ID_REG_CONFIGURABLE) <= 0) { + print_skip("KVM_CAP_ARM_ID_REG_CONFIGURABLE is not supported"); + exit(KSFT_SKIP); + } + + init_test_info(); + run_test(); + return 0; +} From patchwork Tue Apr 19 06:55:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACCB5C433F5 for ; Tue, 19 Apr 2022 07:23:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=dgWji4HavBUEVt1g1cf/rl1Ah6FeRIg3kpLF5iWrQlQ=; b=tXIg1zUmVxFch8H0sw7fY7C+up hdc0bXZDwtss9ZV3RI60b16DEVeSKDZ3F4w2/JfEEKMtG4VDyNftSNyo0q6V4/ijcmrupegZGEkn8 +eFomC5QSgDciuXUpLV92ik4z75LO3vPjVn2coC2bqph+9g88b4WFx0NJNj6NLET5Xt6tmbW1ZlMg zTlm1bOd9eHe6BHRve2VnQM2wwa63s5VkeV57vzovnuDLjkWnnOZ+LDZsQdujnphw5dFT8fBiibx/ wvDlMeqxbyOuqk78/yLWJTwRUwf3TR2zN19yyQVuuRaWnFrvyuw4c39+4+80+fjQue6YzA+LyZ01a HuY+y69Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiBm-001wt0-1S; Tue, 19 Apr 2022 07:22:19 +0000 Received: from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoJ-001noJ-Ks for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:58:07 +0000 Received: by mail-pj1-x104a.google.com with SMTP id b16-20020a17090ae39000b001ce8478ea2dso1211689pjz.0 for ; Mon, 18 Apr 2022 23:58:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=kXAUMCFpJ2FSikaWOMOMMVh2xgNlrGhggw5TBv+ypng=; b=dOXWqp1IXFvQ5hWm0ELCzHEX1gpvRgjeGAdThxRYIpfqfc997MFB1zkZG8YL59ZBoC d9UsOo1qalRiDg7DNheF9RwXIoUFeHGOwj/Znu7oLMD3aUa1QaHsLM5PGGLm/wR3YJIr 7d+lsvxH8RnTuzg/WbsaWxhNWGFYEsnqv7BDkcxKT60lE1xtPu5pxeGqagUv7J0X8qNU 6AMv7blXuYpbths6WG0B+OCavNULycBsv3CCgSpipHK543TcXxlzFw+AT0aGIaJPXl/P 4kokSIXPT3jlr8tRVwnID4hq/n82/sJTZf+LBLYVpLvAvayWrCidsh2fSRoi0n0qwku9 DuqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=kXAUMCFpJ2FSikaWOMOMMVh2xgNlrGhggw5TBv+ypng=; b=nCEmt7Q3Zc0T5RyXm9Gakk8HfJSaqCl73+VIDr7pQLth2N+7gnPmZ7NXwufHv8bxCE gzj+uVTptGZXUrrNihYjcGCrvTqhXWWaas1LsP33c1PgFBQm89rnUNxq0G1ZcaROvTEa qqUyBU+xxVajNebi8iuYXsfGXsK8I6zRP385Mngwvk3oH9a9nKsqpjQjAKyK2F6Sdmrw hoxV4QbtPCyWP+RkdWANJ3xOdjapZZAIYCdgEtRTN1c1Ls/dihPjhq86OKdmpFBAO0qt HPLJzuKT3vegQ6tMKdqOzbrNyQ9RaFchwXIMirypiQ1IrVTw5YhgXdKCMubfwTKtVbWI iYAQ== X-Gm-Message-State: AOAM532cAankBPv149U0vGaL5ca8UmhtNQcEDWqFSiJ+CdpQNzvQLj/D hvW02naSsIAyuZXIpngjyjjIU01jknI= X-Google-Smtp-Source: ABdhPJxa5Wc/c0aBN0VsTih5eeSbcaDGz7OargYMgM2VlUR4Aihe2pGWd+HYKfruhi+RJtilemTj8wdlm8w= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:902:ab43:b0:156:6f38:52b3 with SMTP id ij3-20020a170902ab4300b001566f3852b3mr14255343plb.135.1650351482084; Mon, 18 Apr 2022 23:58:02 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:41 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-36-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 35/38] KVM: arm64: selftests: Test linked breakpoint and watchpoint From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235803_763694_7ADD8599 X-CRM114-Status: GOOD ( 17.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add test cases for a linkted breakpoint and watchpoint to the debug-exceptions test. Signed-off-by: Reiji Watanabe --- .../selftests/kvm/aarch64/debug-exceptions.c | 225 +++++++++++++++--- 1 file changed, 197 insertions(+), 28 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c index 63b2178210c4..876257be5960 100644 --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c @@ -13,25 +13,99 @@ #define DBGBCR_EXEC (0x0 << 3) #define DBGBCR_EL1 (0x1 << 1) #define DBGBCR_E (0x1 << 0) +#define DBGBCR_LBN_SHIFT 16 +#define DBGBCR_BT_SHIFT 20 +#define DBGBCR_BT_ADDR_LINK_CTX (0x1 << DBGBCR_BT_SHIFT) +#define DBGBCR_BT_CTX_LINK (0x3 << DBGBCR_BT_SHIFT) #define DBGWCR_LEN8 (0xff << 5) #define DBGWCR_RD (0x1 << 3) #define DBGWCR_WR (0x2 << 3) #define DBGWCR_EL1 (0x1 << 1) #define DBGWCR_E (0x1 << 0) +#define DBGWCR_LBN_SHIFT 16 +#define DBGWCR_WT_SHIFT 20 +#define DBGWCR_WT_LINK (0x1 << DBGWCR_WT_SHIFT) #define SPSR_D (1 << 9) #define SPSR_SS (1 << 21) -extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start; +extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start, hw_bp_ctx; static volatile uint64_t sw_bp_addr, hw_bp_addr; static volatile uint64_t wp_addr, wp_data_addr; static volatile uint64_t svc_addr; static volatile uint64_t ss_addr[4], ss_idx; #define PC(v) ((uint64_t)&(v)) +#define GEN_DEBUG_WRITE_REG(reg_name) \ +static void write_##reg_name(int num, uint64_t val) \ +{ \ + switch (num) { \ + case 0: \ + write_sysreg(val, reg_name##0_el1); \ + break; \ + case 1: \ + write_sysreg(val, reg_name##1_el1); \ + break; \ + case 2: \ + write_sysreg(val, reg_name##2_el1); \ + break; \ + case 3: \ + write_sysreg(val, reg_name##3_el1); \ + break; \ + case 4: \ + write_sysreg(val, reg_name##4_el1); \ + break; \ + case 5: \ + write_sysreg(val, reg_name##5_el1); \ + break; \ + case 6: \ + write_sysreg(val, reg_name##6_el1); \ + break; \ + case 7: \ + write_sysreg(val, reg_name##7_el1); \ + break; \ + case 8: \ + write_sysreg(val, reg_name##8_el1); \ + break; \ + case 9: \ + write_sysreg(val, reg_name##9_el1); \ + break; \ + case 10: \ + write_sysreg(val, reg_name##10_el1); \ + break; \ + case 11: \ + write_sysreg(val, reg_name##11_el1); \ + break; \ + case 12: \ + write_sysreg(val, reg_name##12_el1); \ + break; \ + case 13: \ + write_sysreg(val, reg_name##13_el1); \ + break; \ + case 14: \ + write_sysreg(val, reg_name##14_el1); \ + break; \ + case 15: \ + write_sysreg(val, reg_name##15_el1); \ + break; \ + default: \ + GUEST_ASSERT(0); \ + } \ +} + +/* Define write_dbgbcr()/write_dbgbvr()/write_dbgwcr()/write_dbgwvr() */ +GEN_DEBUG_WRITE_REG(dbgbcr) +GEN_DEBUG_WRITE_REG(dbgbvr) +GEN_DEBUG_WRITE_REG(dbgwcr) +GEN_DEBUG_WRITE_REG(dbgwvr) + + static void reset_debug_state(void) { + uint64_t dfr0 = read_sysreg(id_aa64dfr0_el1); + uint8_t brps, wrps, i; + asm volatile("msr daifset, #8"); write_sysreg(0, osdlr_el1); @@ -39,11 +113,19 @@ static void reset_debug_state(void) isb(); write_sysreg(0, mdscr_el1); - /* This test only uses the first bp and wp slot. */ - write_sysreg(0, dbgbvr0_el1); - write_sysreg(0, dbgbcr0_el1); - write_sysreg(0, dbgwcr0_el1); - write_sysreg(0, dbgwvr0_el1); + write_sysreg(0, contextidr_el1); + + /* Reset bcr/bvr/wcr/wvr registers */ + brps = cpuid_extract_uftr(dfr0, ID_AA64DFR0_BRPS_SHIFT); + wrps = cpuid_extract_uftr(dfr0, ID_AA64DFR0_WRPS_SHIFT); + for (i = 0; i <= brps; i++) { + write_dbgbcr(i, 0); + write_dbgbvr(i, 0); + } + for (i = 0; i <= wrps; i++) { + write_dbgwcr(i, 0); + write_dbgwvr(i, 0); + } isb(); } @@ -55,14 +137,15 @@ static void enable_os_lock(void) GUEST_ASSERT(read_sysreg(oslsr_el1) & 2); } -static void install_wp(uint64_t addr) +static void install_wp(uint8_t wpn, uint64_t addr) { uint32_t wcr; uint32_t mdscr; wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E; - write_sysreg(wcr, dbgwcr0_el1); - write_sysreg(addr, dbgwvr0_el1); + write_dbgwcr(wpn, wcr); + write_dbgwvr(wpn, addr); + isb(); asm volatile("msr daifclr, #8"); @@ -72,14 +155,69 @@ static void install_wp(uint64_t addr) isb(); } -static void install_hw_bp(uint64_t addr) +static void install_hw_bp(uint8_t bpn, uint64_t addr) { uint32_t bcr; uint32_t mdscr; bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E; - write_sysreg(bcr, dbgbcr0_el1); - write_sysreg(addr, dbgbvr0_el1); + write_dbgbcr(bpn, bcr); + write_dbgbvr(bpn, addr); + isb(); + + asm volatile("msr daifclr, #8"); + + mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE; + write_sysreg(mdscr, mdscr_el1); + isb(); +} + +static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr, + uint64_t ctx) +{ + uint32_t wcr; + uint64_t ctx_bcr; + uint32_t mdscr; + + /* Setup a context-aware breakpoint to be linked by watchpoint */ + ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E | + DBGBCR_BT_CTX_LINK; + write_dbgbcr(ctx_bp, ctx_bcr); + write_dbgbvr(ctx_bp, ctx); + + /* Setup a linked watchpoint */ + wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E | + DBGWCR_WT_LINK | ((uint32_t)ctx_bp << DBGWCR_LBN_SHIFT); + write_dbgwcr(addr_wp, wcr); + write_dbgwvr(addr_wp, addr); + + isb(); + + asm volatile("msr daifclr, #8"); + + mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE; + write_sysreg(mdscr, mdscr_el1); + isb(); +} + +void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr, + uint64_t ctx) +{ + uint32_t addr_bcr, ctx_bcr; + uint32_t mdscr; + + /* Setup a context-aware breakpoint to be linked by breakpoint */ + ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E | + DBGBCR_BT_CTX_LINK; + write_dbgbcr(ctx_bp, ctx_bcr); + write_dbgbvr(ctx_bp, ctx); + + /* Setup a linked breakpoint */ + addr_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E | + DBGBCR_BT_ADDR_LINK_CTX | + ((uint32_t)ctx_bp << DBGBCR_LBN_SHIFT); + write_dbgbcr(addr_bp, addr_bcr); + write_dbgbvr(addr_bp, addr); isb(); asm volatile("msr daifclr, #8"); @@ -102,8 +240,10 @@ static void install_ss(void) static volatile char write_data; -static void guest_code(void) +static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) { + uint64_t ctx = 0xc; /* a random context number */ + GUEST_SYNC(0); /* Software-breakpoint */ @@ -115,7 +255,7 @@ static void guest_code(void) /* Hardware-breakpoint */ reset_debug_state(); - install_hw_bp(PC(hw_bp)); + install_hw_bp(bpn, PC(hw_bp)); asm volatile("hw_bp: nop"); GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp)); @@ -123,7 +263,7 @@ static void guest_code(void) /* Hardware-breakpoint + svc */ reset_debug_state(); - install_hw_bp(PC(bp_svc)); + install_hw_bp(bpn, PC(bp_svc)); asm volatile("bp_svc: svc #0"); GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_svc)); GUEST_ASSERT_EQ(svc_addr, PC(bp_svc) + 4); @@ -132,7 +272,7 @@ static void guest_code(void) /* Hardware-breakpoint + software-breakpoint */ reset_debug_state(); - install_hw_bp(PC(bp_brk)); + install_hw_bp(bpn, PC(bp_brk)); asm volatile("bp_brk: brk #0"); GUEST_ASSERT_EQ(sw_bp_addr, PC(bp_brk)); GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_brk)); @@ -141,7 +281,7 @@ static void guest_code(void) /* Watchpoint */ reset_debug_state(); - install_wp(PC(write_data)); + install_wp(wpn, PC(write_data)); write_data = 'x'; GUEST_ASSERT_EQ(write_data, 'x'); GUEST_ASSERT_EQ(wp_data_addr, PC(write_data)); @@ -175,7 +315,7 @@ static void guest_code(void) /* OS Lock blocking hardware-breakpoint */ reset_debug_state(); enable_os_lock(); - install_hw_bp(PC(hw_bp2)); + install_hw_bp(bpn, PC(hw_bp2)); hw_bp_addr = 0; asm volatile("hw_bp2: nop"); GUEST_ASSERT_EQ(hw_bp_addr, 0); @@ -187,7 +327,7 @@ static void guest_code(void) enable_os_lock(); write_data = '\0'; wp_data_addr = 0; - install_wp(PC(write_data)); + install_wp(wpn, PC(write_data)); write_data = 'x'; GUEST_ASSERT_EQ(write_data, 'x'); GUEST_ASSERT_EQ(wp_data_addr, 0); @@ -206,6 +346,28 @@ static void guest_code(void) : : : "x0"); GUEST_ASSERT_EQ(ss_addr[0], 0); + /* Linked hardware-breakpoint */ + hw_bp_addr = 0; + reset_debug_state(); + install_hw_bp_ctx(bpn, ctx_bpn, PC(hw_bp_ctx), ctx); + /* Set context id */ + write_sysreg(ctx, contextidr_el1); + isb(); + asm volatile("hw_bp_ctx: nop"); + write_sysreg(0, contextidr_el1); + GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp_ctx)); + GUEST_SYNC(10); + + /* Linked watchpoint */ + reset_debug_state(); + install_wp_ctx(wpn, ctx_bpn, PC(write_data), ctx); + /* Set context id */ + write_sysreg(ctx, contextidr_el1); + isb(); + write_data = 'x'; + GUEST_ASSERT_EQ(write_data, 'x'); + GUEST_ASSERT_EQ(wp_data_addr, PC(write_data)); + GUEST_DONE(); } @@ -240,19 +402,13 @@ static void guest_svc_handler(struct ex_regs *regs) svc_addr = regs->pc; } -static int debug_version(struct kvm_vm *vm) -{ - uint64_t id_aa64dfr0; - - get_reg(vm, VCPU_ID, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &id_aa64dfr0); - return id_aa64dfr0 & 0xf; -} - int main(int argc, char *argv[]) { struct kvm_vm *vm; struct ucall uc; int stage; + uint64_t aa64dfr0; + uint8_t max_brps; vm = vm_create_default(VCPU_ID, 0, guest_code); ucall_init(vm, NULL); @@ -260,7 +416,8 @@ int main(int argc, char *argv[]) vm_init_descriptor_tables(vm); vcpu_init_descriptor_tables(vm, VCPU_ID); - if (debug_version(vm) < 6) { + get_reg(vm, VCPU_ID, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0); + if (cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_DEBUGVER_SHIFT) < 6) { print_skip("Armv8 debug architecture not supported."); kvm_vm_free(vm); exit(KSFT_SKIP); @@ -277,6 +434,18 @@ int main(int argc, char *argv[]) vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, ESR_EC_SVC64, guest_svc_handler); + /* Number of breakpoints, minus 1 */ + max_brps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_BRPS_SHIFT); + + /* The value of 0x0 is reserved */ + TEST_ASSERT(max_brps > 0, "ID_AA64DFR0_EL1.BRPS must be > 0"); + + /* + * Test with breakpoint#0 and watchpoint#0, and the higiest + * numbered breakpoint (the context aware breakpoint). + */ + vcpu_args_set(vm, VCPU_ID, 3, 0, 0, max_brps); + for (stage = 0; stage < 11; stage++) { vcpu_run(vm, VCPU_ID); From patchwork Tue Apr 19 06:55:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9BF8C433EF for ; Tue, 19 Apr 2022 07:26:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=5cFcJS3UtOy70cn2XIR9TES9L9XRnE8wbYNB8q7jSX4=; b=qgAeOF5h1g+NJdRAavHmBP1RPY 7qlXqk/lFozWgdOLT9W9ZKu4lAUzgAOaXYKitx+B7UP6Cp7gG+pmH6h9NYxtFm/g/1p75K1d6PGRb j3tZqAQ3+GOJiQmedSahBjY/Ft53PyPFujTCUA9R5k3WgoQXpvppJ2MFTAIgf+WWq7jFOwxrb867o jlc/4xrnZNWslTPY8NBruAOxiT8VlWs4/FVHU8hAyZpoblE8P7DZiu/9eNkmJhzHFWDbPisNgsJ8u S/tJ2X3+VQULuaNQz36cwC6/ze4b8LPz4UYu8SBqnYg6oKlITLbuW2ZECn6CQSMar28pEHWElogTX 0k3JuURg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiEW-001y54-A2; Tue, 19 Apr 2022 07:25:08 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoL-001npW-2L for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:58:12 +0000 Received: by mail-pl1-x649.google.com with SMTP id i10-20020a1709026aca00b00158f14b4f2fso3812636plt.2 for ; Mon, 18 Apr 2022 23:58:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=3muW+LT8OOUV4To4u5OSB2G3zDFllVWSkyBrKzdGUG8=; b=oR9T7BXixT6xBgn18g1Hh/jt8urIrga4TxVi78S7u28dehEkOk1mrCxUQe4utw6eIt 9TgGCVWg8ZTXowkSt0MNQ4IF/Dl79v3kcNbRFZVmDrYnKV5Kjjw1837LrBsq8ZpZpXS1 S8Wn5eiMXb3vpuAAUWZF5rNiIQLT1B0bNHwHZI2/3+IRj88wO+nbgm1lxQG4nxW0XD5m wzOvLFfFvYx63UYcmNsfWATEALrBFcenk1BudVZzACBqRxe4v6y6PvSXHfZXb5eme5yG LkNUefaksu27K0dMkNDrFOTYMCjScbfyMMlZzg7PfWW7SbJ8s/R0hrpvpbVLWOIg6ets zzGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=3muW+LT8OOUV4To4u5OSB2G3zDFllVWSkyBrKzdGUG8=; b=ZSqOiEr98vrcAAW9D0q7I7+2pjucw59ZdZD7Dmoo7YP5lY+IxJ0MQvawWZyCgz1shg nFMoCFsv6xKHfyzwmpji63YG8/HNoiDB5Tw0EdJBgeyxVw8PQzPDGAPX1l/y7l/LXeDa sR701UjJBdxIGZpqH8PN/eZV/KaVqt1c6BqCj2ZKlfOYnQPLzjL5hHyuEa0MR3cCXiIF nTOHXex7kDmlE2g0aZtRNdF91KLpG7Ik3FCUZevye4AxODP89MvOWCVF8TcAeNjGQ39p MqoNa0nth8nIlr8aqJ8HtzMVj2yTG1onb1oD0rXN7fQxlUdGH/xlRleS6anu3IBovT84 smsw== X-Gm-Message-State: AOAM533868hhfRFxR6rdfE211Scq39gy3vFWiYCxX4wAFe6UchO/HHEl yBX+lFYNialQwtOIqrD8W65g463IMys= X-Google-Smtp-Source: ABdhPJyB77yq+//pE7CNExrz84DDPN2e34z9v6NwPrrLkqA2BQkYhti1e7qLBpn39CuPKY5bMokIj7ORtPY= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a05:6a00:1a8f:b0:50a:8c2d:2ee8 with SMTP id e15-20020a056a001a8f00b0050a8c2d2ee8mr5029299pfv.46.1650351483684; Mon, 18 Apr 2022 23:58:03 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:42 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-37-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 36/38] KVM: arm64: selftests: Test breakpoint/watchpoint register access From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235805_236639_2F58471C X-CRM114-Status: GOOD ( 19.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add test cases for reading and writing of dbgbcr/dbgbvr/dbgwcr/dbgwvr registers from userspace and the guest. Signed-off-by: Reiji Watanabe --- .../selftests/kvm/aarch64/debug-exceptions.c | 350 +++++++++++++++++- 1 file changed, 332 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c index 876257be5960..4e00100b9aa1 100644 --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c @@ -37,6 +37,26 @@ static volatile uint64_t svc_addr; static volatile uint64_t ss_addr[4], ss_idx; #define PC(v) ((uint64_t)&(v)) +struct kvm_guest_debug_arch debug_regs; + +static uint64_t update_bcr_lbn(uint64_t val, uint8_t lbn) +{ + uint64_t new; + + new = val & ~((uint64_t)0xf << DBGBCR_LBN_SHIFT); + new |= (uint64_t)((lbn & 0xf) << DBGBCR_LBN_SHIFT); + return new; +} + +static uint64_t update_wcr_lbn(uint64_t val, uint8_t lbn) +{ + uint64_t new; + + new = val & ~((uint64_t)0xf << DBGWCR_LBN_SHIFT); + new |= (uint64_t)((lbn & 0xf) << DBGWCR_LBN_SHIFT); + return new; +} + #define GEN_DEBUG_WRITE_REG(reg_name) \ static void write_##reg_name(int num, uint64_t val) \ { \ @@ -94,12 +114,77 @@ static void write_##reg_name(int num, uint64_t val) \ } \ } +#define GEN_DEBUG_READ_REG(reg_name) \ +u64 read_##reg_name(int num) \ +{ \ + u64 val = 0; \ + \ + switch (num) { \ + case 0: \ + val = read_sysreg(reg_name##0_el1); \ + break; \ + case 1: \ + val = read_sysreg(reg_name##1_el1); \ + break; \ + case 2: \ + val = read_sysreg(reg_name##2_el1); \ + break; \ + case 3: \ + val = read_sysreg(reg_name##3_el1); \ + break; \ + case 4: \ + val = read_sysreg(reg_name##4_el1); \ + break; \ + case 5: \ + val = read_sysreg(reg_name##5_el1); \ + break; \ + case 6: \ + val = read_sysreg(reg_name##6_el1); \ + break; \ + case 7: \ + val = read_sysreg(reg_name##7_el1); \ + break; \ + case 8: \ + val = read_sysreg(reg_name##8_el1); \ + break; \ + case 9: \ + val = read_sysreg(reg_name##9_el1); \ + break; \ + case 10: \ + val = read_sysreg(reg_name##10_el1); \ + break; \ + case 11: \ + val = read_sysreg(reg_name##11_el1); \ + break; \ + case 12: \ + val = read_sysreg(reg_name##12_el1); \ + break; \ + case 13: \ + val = read_sysreg(reg_name##13_el1); \ + break; \ + case 14: \ + val = read_sysreg(reg_name##14_el1); \ + break; \ + case 15: \ + val = read_sysreg(reg_name##15_el1); \ + break; \ + default: \ + GUEST_ASSERT(0); \ + } \ + return val; \ +} + /* Define write_dbgbcr()/write_dbgbvr()/write_dbgwcr()/write_dbgwvr() */ GEN_DEBUG_WRITE_REG(dbgbcr) GEN_DEBUG_WRITE_REG(dbgbvr) GEN_DEBUG_WRITE_REG(dbgwcr) GEN_DEBUG_WRITE_REG(dbgwvr) +/* Define read_dbgbcr()/read_dbgbvr()/read_dbgwcr()/read_dbgwvr() */ +GEN_DEBUG_READ_REG(dbgbcr) +GEN_DEBUG_READ_REG(dbgbvr) +GEN_DEBUG_READ_REG(dbgwcr) +GEN_DEBUG_READ_REG(dbgwvr) static void reset_debug_state(void) { @@ -238,20 +323,126 @@ static void install_ss(void) isb(); } +/* + * Check if the guest sees bcr/bvr/wcr/wvr register values that userspace + * set (by set_debug_regs()), and update them for userspace to verify + * the same. + */ +static void guest_code_bwp_reg_test(struct kvm_guest_debug_arch *dregs) +{ + uint64_t dfr0 = read_sysreg(id_aa64dfr0_el1); + uint8_t nbps, nwps; + int i; + u64 val, rval; + + /* Set nbps/nwps to the number of breakpoints/watchpoints. */ + nbps = cpuid_extract_uftr(dfr0, ID_AA64DFR0_BRPS_SHIFT) + 1; + nwps = cpuid_extract_uftr(dfr0, ID_AA64DFR0_WRPS_SHIFT) + 1; + + for (i = 0; i < nbps; i++) { + /* + * Check if the dbgbcr value is the same as the one set by + * userspace. + */ + val = read_dbgbcr(i); + GUEST_ASSERT_EQ(val, dregs->dbg_bcr[i]); + + /* Set dbgbcr to some value for userspace to read later */ + val = update_bcr_lbn(0, (i + 1) % nbps); + write_dbgbcr(i, val); + rval = read_dbgbcr(i); + + /* Make sure written value could be read */ + GUEST_ASSERT_EQ(val, rval); + + /* Save the written value for userspace to refer later */ + dregs->dbg_bcr[i] = val; + + /* + * Check if the dbgbvr value is the same as the one set by + * userspace. + */ + val = read_dbgbvr(i); + GUEST_ASSERT_EQ(val, dregs->dbg_bvr[i]); + + /* Set dbgbvr to some value for userspace to read later */ + val = (uint64_t)(nbps - i - 1) << 32; + write_dbgbvr(i, val); + + /* Make sure written value could be read */ + rval = read_dbgbvr(i); + GUEST_ASSERT_EQ(val, rval); + + /* Save the written value for userspace to refer later */ + dregs->dbg_bvr[i] = val; + } + + for (i = 0; i < nwps; i++) { + /* + * Check if the dbgwcr value is the same as the one set by + * userspace. + */ + val = read_dbgwcr(i); + GUEST_ASSERT_EQ(val, dregs->dbg_wcr[i]); + + /* Set dbgwcr to some value for userspace to read later */ + val = update_wcr_lbn(0, (i + 1) % nbps); + write_dbgwcr(i, val); + + /* Make sure written value could be read */ + rval = read_dbgwcr(i); + GUEST_ASSERT_EQ(val, rval); + + /* Save the written value for userspace to refer later */ + dregs->dbg_wcr[i] = val; + + /* + * Check if the dbgwvr value is the same as the one set by + * userspace. + */ + val = read_dbgwvr(i); + GUEST_ASSERT_EQ(val, dregs->dbg_wvr[i]); + + /* Set dbgwvr to some value for userspace to read later */ + val = (uint64_t)(nbps - i - 1) << 32; + write_dbgwvr(i, val); + + /* Make sure written value could be read */ + rval = read_dbgwvr(i); + GUEST_ASSERT_EQ(val, rval); + + /* Save the written value for userspace to refer later */ + dregs->dbg_wvr[i] = val; + } +} + static volatile char write_data; -static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) +static void guest_code(struct kvm_guest_debug_arch *dregs, + uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) { uint64_t ctx = 0xc; /* a random context number */ + /* + * Check if the guest sees bcr/bvr/wcr/wvr register values that + * userspace set before the first KVM_RUN. + */ + guest_code_bwp_reg_test(dregs); GUEST_SYNC(0); + /* + * Check if the guest sees bcr/bvr/wcr/wvr register values that + * userspace set after the first KVM_RUN. + */ + guest_code_bwp_reg_test(dregs); + GUEST_SYNC(1); + /* Software-breakpoint */ reset_debug_state(); asm volatile("sw_bp: brk #0"); GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp)); - GUEST_SYNC(1); + GUEST_SYNC(2); /* Hardware-breakpoint */ reset_debug_state(); @@ -259,7 +450,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) asm volatile("hw_bp: nop"); GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp)); - GUEST_SYNC(2); + GUEST_SYNC(3); /* Hardware-breakpoint + svc */ reset_debug_state(); @@ -268,7 +459,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_svc)); GUEST_ASSERT_EQ(svc_addr, PC(bp_svc) + 4); - GUEST_SYNC(3); + GUEST_SYNC(4); /* Hardware-breakpoint + software-breakpoint */ reset_debug_state(); @@ -277,7 +468,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) GUEST_ASSERT_EQ(sw_bp_addr, PC(bp_brk)); GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_brk)); - GUEST_SYNC(4); + GUEST_SYNC(5); /* Watchpoint */ reset_debug_state(); @@ -286,7 +477,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) GUEST_ASSERT_EQ(write_data, 'x'); GUEST_ASSERT_EQ(wp_data_addr, PC(write_data)); - GUEST_SYNC(5); + GUEST_SYNC(6); /* Single-step */ reset_debug_state(); @@ -301,7 +492,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) GUEST_ASSERT_EQ(ss_addr[1], PC(ss_start) + 4); GUEST_ASSERT_EQ(ss_addr[2], PC(ss_start) + 8); - GUEST_SYNC(6); + GUEST_SYNC(7); /* OS Lock does not block software-breakpoint */ reset_debug_state(); @@ -310,7 +501,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) asm volatile("sw_bp2: brk #0"); GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp2)); - GUEST_SYNC(7); + GUEST_SYNC(8); /* OS Lock blocking hardware-breakpoint */ reset_debug_state(); @@ -320,7 +511,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) asm volatile("hw_bp2: nop"); GUEST_ASSERT_EQ(hw_bp_addr, 0); - GUEST_SYNC(8); + GUEST_SYNC(9); /* OS Lock blocking watchpoint */ reset_debug_state(); @@ -332,7 +523,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) GUEST_ASSERT_EQ(write_data, 'x'); GUEST_ASSERT_EQ(wp_data_addr, 0); - GUEST_SYNC(9); + GUEST_SYNC(10); /* OS Lock blocking single-step */ reset_debug_state(); @@ -356,7 +547,7 @@ static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) asm volatile("hw_bp_ctx: nop"); write_sysreg(0, contextidr_el1); GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp_ctx)); - GUEST_SYNC(10); + GUEST_SYNC(11); /* Linked watchpoint */ reset_debug_state(); @@ -402,13 +593,122 @@ static void guest_svc_handler(struct ex_regs *regs) svc_addr = regs->pc; } +/* + * Set bcr/bwr/wcr/wbr for register read/write testing. + * The values that are set by userspace are saved in dregs, which will + * be used by the guest code (guest_code_bwp_reg_test()) to make sure + * that the guest sees bcr/bvr/wcr/wvr register values that are set + * by userspace. + */ +static void set_debug_regs(struct kvm_vm *vm, uint32_t vcpu, + struct kvm_guest_debug_arch *dregs, + uint8_t nbps, uint8_t nwps) +{ + int i; + uint64_t val; + + for (i = 0; i < nbps; i++) { + /* Set dbgbcr to some value for the guest to read later */ + val = update_bcr_lbn(0, i); + set_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGBCRn_EL1(i)), val); + + /* Save the written value for the guest to refer later */ + dregs->dbg_bcr[i] = val; + + /* Make sure the written value could be read */ + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGBCRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_bcr[i], + "Unexpected bcr[%d]:0x%lx (expected:0x%llx)\n", + i, val, dregs->dbg_bcr[i]); + + /* Set dbgbvr to some value for the guest to read later */ + val = (uint64_t)i << 8; + set_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGBVRn_EL1(i)), val); + + /* Save the written value for the guest to refer later */ + dregs->dbg_bvr[i] = val; + + /* Make sure the written value could be read */ + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGBVRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_bvr[i], + "Unexpected bvr[%d]:0x%lx (expected:0x%llx)\n", + i, val, dregs->dbg_bvr[i]); + } + + for (i = 0; i < nwps; i++) { + /* Set dbgwcr to some value for the guest to read later */ + val = update_wcr_lbn(0, i % nbps); + set_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGWCRn_EL1(i)), val); + + /* Save the written value for the guest to refer later */ + dregs->dbg_wcr[i] = val; + + /* Make sure the written value could be read */ + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGWCRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_wcr[i], + "Unexpected wcr[%d]:0x%lx (expected:0x%llx)\n", + i, val, dregs->dbg_wcr[i]); + + /* Set dbgwvr to some value for the guest to read later */ + val = (uint64_t)i << 8; + set_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGWVRn_EL1(i)), val); + + /* Save the written value for the guest to refer later */ + dregs->dbg_wvr[i] = val; + + /* Make sure the written value could be read */ + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGWVRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_wvr[i], + "Unexpected wvr[%d]:0x%lx (expected:0x%llx)\n", + i, val, dregs->dbg_wvr[i]); + } +} + +/* + * Check if the userspace sees bcr/bvr/wcr/wvr register values that are + * set by the guest (guest_code_bwp_reg_test()), which are saved in the + * given dregs. + */ +static void check_debug_regs(struct kvm_vm *vm, uint32_t vcpu, + struct kvm_guest_debug_arch *dregs, + int nbps, int nwps) +{ + uint64_t val; + int i; + + for (i = 0; i < nbps; i++) { + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGBCRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_bcr[i], + "Unexpected bcr[%d]:0x%lx (Expected: 0x%llx)\n", + i, val, dregs->dbg_bcr[i]); + + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGBVRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_bvr[i], + "Unexpected bvr[%d]:0x%lx (Expected: 0x%llx)\n", + i, val, dregs->dbg_bvr[i]); + } + + for (i = 0; i < nwps; i++) { + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGWCRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_wcr[i], + "Unexpected wcr[%d]:0x%lx (Expected: 0x%llx)\n", + i, val, dregs->dbg_wcr[i]); + + get_reg(vm, vcpu, KVM_ARM64_SYS_REG(SYS_DBGWVRn_EL1(i)), &val); + TEST_ASSERT(val == dregs->dbg_wvr[i], + "Unexpected wvr[%d]:0x%lx (Expected: 0x%llx)\n", + i, val, dregs->dbg_wvr[i]); + } +} + int main(int argc, char *argv[]) { struct kvm_vm *vm; struct ucall uc; int stage; uint64_t aa64dfr0; - uint8_t max_brps; + uint8_t nbps, nwps; + bool debug_reg_test = false; vm = vm_create_default(VCPU_ID, 0, guest_code); ucall_init(vm, NULL); @@ -434,19 +734,28 @@ int main(int argc, char *argv[]) vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, ESR_EC_SVC64, guest_svc_handler); - /* Number of breakpoints, minus 1 */ - max_brps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_BRPS_SHIFT); + /* Number of breakpoints */ + nbps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_BRPS_SHIFT) + 1; + TEST_ASSERT(nbps >= 2, "Number of breakpoints must be >= 2"); - /* The value of 0x0 is reserved */ - TEST_ASSERT(max_brps > 0, "ID_AA64DFR0_EL1.BRPS must be > 0"); + /* Number of watchpoints */ + nwps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_WRPS_SHIFT) + 1; + TEST_ASSERT(nwps >= 2, "Number of watchpoints must be >= 2"); /* * Test with breakpoint#0 and watchpoint#0, and the higiest * numbered breakpoint (the context aware breakpoint). */ - vcpu_args_set(vm, VCPU_ID, 3, 0, 0, max_brps); + vcpu_args_set(vm, VCPU_ID, 4, &debug_regs, 0, 0, nbps - 1); + + for (stage = 0; stage < 13; stage++) { + /* First two stages are sanity debug regs read/write check */ + if (stage < 2) { + set_debug_regs(vm, VCPU_ID, &debug_regs, nbps, nwps); + sync_global_to_guest(vm, debug_regs); + debug_reg_test = true; + } - for (stage = 0; stage < 11; stage++) { vcpu_run(vm, VCPU_ID); switch (get_ucall(vm, VCPU_ID, &uc)) { @@ -454,6 +763,11 @@ int main(int argc, char *argv[]) TEST_ASSERT(uc.args[1] == stage, "Stage %d: Unexpected sync ucall, got %lx", stage, (ulong)uc.args[1]); + if (debug_reg_test) { + debug_reg_test = false; + sync_global_from_guest(vm, debug_regs); + check_debug_regs(vm, VCPU_ID, &debug_regs, nbps, nwps); + } break; case UCALL_ABORT: TEST_FAIL("%s at %s:%ld\n\tvalues: %#lx, %#lx", From patchwork Tue Apr 19 06:55:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CF7AC433EF for ; Tue, 19 Apr 2022 07:24:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=gmQvumar64hzc6TNod6jm3qKbJ0hPCe0j5qOOt8im+o=; b=u7npbaoOxwdaJliXwSBIBKSXUb FypwZtdH/nOfOO2kApeAi4xGbcdRjdJLK5KOaPIgVSVgh1FYPpMvdx4areb9z3fejF9/+GqRjy7EP c01XKeDvF91r20DQvdIPX9J4w/EbKNvmd7YQtD3gnZHOVMAVFAwn/DcKpngZHnCmoVsHLkRmEEHHE BWdTV7pJG3hmOnbT3nM6LwWrp5vXsnJdQOwV/vn/l0tt0fW34FoQymyYtIZSo7VjUekc5Bw6J17ke vcRh7tf3NGZpTnYMIaV4t7jI9FWZPHvA/pJAoHlzxHcJHksTI1S3TTa4y6IM9O6c20QM1cJhXlD3O 1VPlKbBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiCr-001xNh-F2; Tue, 19 Apr 2022 07:23:27 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoM-001nq0-Gt for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:58:10 +0000 Received: by mail-pj1-x1049.google.com with SMTP id s13-20020a17090a764d00b001cb896b75ffso10133600pjl.6 for ; Mon, 18 Apr 2022 23:58:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Q/YanX6EPfx+u+3OMqrYAFeJvrZlkb0TikNUTqVME1Y=; b=A9RjQxSTslkChFxxKJBdhdGh7KoE8jdKMtCpxERX/tBbu9UdykN6mkSjBGbvrYe0yp xBFHJ43ZJf4RR+MEhIlZ7ADb8RRTxk9EjoI4axpGew5mfnR/CZ+7Qc08BTxvdSIhMnEL S0VoLAtGwG0N9/MEUw8RgUNNusNRqxJ2rnhriVmUw0Daui4T115Gk7aB5kAT/K7Dy5ln Sqz+L0yKZ5Fwv8xGNj0xOmz6XDBQvxHX8WWsVY9iNm2YwZF/W72gKnWRD+fPNYWpGwuL Z7r0lVt6DSqTfiRLp6FxJ/jy9xJU8u1FN9hBZqz308wPv0h3JB04kzgRohXhz+W+dL4+ fwVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Q/YanX6EPfx+u+3OMqrYAFeJvrZlkb0TikNUTqVME1Y=; b=TorgjCDWeD8yJklERDCsGeKPI2Qb382OIMv9S5tMt2XIWffvq/4Z9Jz9b8A3PBxhHs 5/RCKDoGQjeDW8DoggzTxWTIUJqneLKGySiJZLIHKmdwOyYU2jbXcmvlEXZoti0JGQtX 5F7mGd0obyQm28lucLmyt9WJsRlqhSaYi0EMx21YQoZdy/g0lSTUsP2Z6CAMDkw59Zjs biZCgLS8OLaaywlHxZC+7VhIAvU+PGrXH6x+vVqXJm1ma2yOdX+kof97zMKo+SDHOBrm LSBHV0AbCKIhrxkK04qKb6LoGa8PQ1PGrNnquQRvIq7eMo8GhpVD6w46uHXaGVjOPJLX zr1g== X-Gm-Message-State: AOAM532UEQ0mDrzw2J8goIarSfxj06SRT6Svm+TORoqC5vwhRxXjyVHK I0d8cD7orlLc0qLD6c9Cx/kpkfpC5hI= X-Google-Smtp-Source: ABdhPJwE2z7KVThLseGHNOhepGcvcWOJLfCs0hdmn9Is1cTsX8Yz9n5jIjhtaxYpBfwuDusFcqDN9vQu4DQ= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a62:685:0:b0:50a:5870:10b1 with SMTP id 127-20020a620685000000b0050a587010b1mr13751101pfg.61.1650351485348; Mon, 18 Apr 2022 23:58:05 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:43 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-38-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 37/38] KVM: arm64: selftests: Test with every breakpoint/watchpoint From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235806_646326_42F1D4DC X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add test cases that uses every breakpoint/watchpoint to the debug-exceptions test. Signed-off-by: Reiji Watanabe --- .../selftests/kvm/aarch64/debug-exceptions.c | 70 ++++++++++++++++--- 1 file changed, 59 insertions(+), 11 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c index 4e00100b9aa1..829fad6c7d58 100644 --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c @@ -701,7 +701,7 @@ static void check_debug_regs(struct kvm_vm *vm, uint32_t vcpu, } } -int main(int argc, char *argv[]) +void run_test(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) { struct kvm_vm *vm; struct ucall uc; @@ -710,6 +710,8 @@ int main(int argc, char *argv[]) uint8_t nbps, nwps; bool debug_reg_test = false; + pr_debug("%s bpn:%d, wpn:%d, ctx_bpn:%d\n", __func__, bpn, wpn, ctx_bpn); + vm = vm_create_default(VCPU_ID, 0, guest_code); ucall_init(vm, NULL); @@ -717,11 +719,6 @@ int main(int argc, char *argv[]) vcpu_init_descriptor_tables(vm, VCPU_ID); get_reg(vm, VCPU_ID, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0); - if (cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_DEBUGVER_SHIFT) < 6) { - print_skip("Armv8 debug architecture not supported."); - kvm_vm_free(vm); - exit(KSFT_SKIP); - } vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, ESR_EC_BRK_INS, guest_sw_bp_handler); @@ -742,11 +739,7 @@ int main(int argc, char *argv[]) nwps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_WRPS_SHIFT) + 1; TEST_ASSERT(nwps >= 2, "Number of watchpoints must be >= 2"); - /* - * Test with breakpoint#0 and watchpoint#0, and the higiest - * numbered breakpoint (the context aware breakpoint). - */ - vcpu_args_set(vm, VCPU_ID, 4, &debug_regs, 0, 0, nbps - 1); + vcpu_args_set(vm, VCPU_ID, 4, &debug_regs, bpn, wpn, ctx_bpn); for (stage = 0; stage < 13; stage++) { /* First two stages are sanity debug regs read/write check */ @@ -783,5 +776,60 @@ int main(int argc, char *argv[]) done: kvm_vm_free(vm); +} + +/* + * Run debug testing using the various breakpoint#, watchpoint# and + * context-aware breakpoint# with the given ID_AA64DFR0_EL1 configuration. + */ +void test_debug(uint64_t aa64dfr0) +{ + uint8_t brps, wrps, ctx_cmps; + uint8_t normal_brp_num, wrp_num, ctx_brp_base, ctx_brp_num; + int b, w, c; + + brps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_BRPS_SHIFT); + wrps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_WRPS_SHIFT); + ctx_cmps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_CTX_CMPS_SHIFT); + + pr_debug("%s brps:%d, wrps:%d, ctx_cmps:%d\n", __func__, + brps, wrps, ctx_cmps); + + /* Number of normal (non-context aware) breakpoints */ + normal_brp_num = brps - ctx_cmps; + + /* Number of watchpoints */ + wrp_num = wrps + 1; + + /* Number of context aware breakpoints */ + ctx_brp_num = ctx_cmps + 1; + + /* Lowest context aware breakpoint number */ + ctx_brp_base = normal_brp_num; + + for (c = ctx_brp_base; c < ctx_brp_base + ctx_brp_num; c++) { + for (b = 0; b < normal_brp_num; b++) { + for (w = 0; w < wrp_num; w++) + run_test(b, w, c); + } + } +} + +int main(int argc, char *argv[]) +{ + struct kvm_vm *vm; + uint64_t aa64dfr0; + + vm = vm_create_default(VCPU_ID, 0, guest_code); + get_reg(vm, VCPU_ID, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0); + kvm_vm_free(vm); + + if (cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_DEBUGVER_SHIFT) < 6) { + print_skip("Armv8 debug architecture not supported."); + exit(KSFT_SKIP); + } + + /* Run debug tests with the default configuration */ + test_debug(aa64dfr0); return 0; } From patchwork Tue Apr 19 06:55:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 12817554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA623C433EF for ; Tue, 19 Apr 2022 07:27:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:References: Mime-Version:Message-Id:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=jck1COKNePTW0wvp7/43/UYBI6zqTp+ZKb18zdQKAEc=; b=IBN/eYbDEhIgzqszfLcKDkbihL XZKpFOFccB05m9OCE31wE7JvUYl2cTwbPd9XNoFYZ2+Kbn8p5/mSzPPhPskmN3f78U/fIR8BcUYAo URFc9LPJY402s1y5zXefUtVsNPJvunG4pMRjKwi1rwHA3rFmIq8/ZY0zsBgE9sjV7NNgGaOt/RV4r XTNsBfRV5NOgtdp3PtPvztHXhRSUw15HcOyKqE5UgdfFgWShhNd8eENEnNHT0fbmw2fHUzP1zoWSZ GafTOh3AggpaQfdiROtm4MCss4RtaB2t+KW5GkUxuQAafUWMwfgdn0fNaX/zFK7u3NZm9ntQ0O+Jr k0XdV7cQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiFd-001yTm-0k; Tue, 19 Apr 2022 07:26:18 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghoP-001nqs-1G for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 06:58:13 +0000 Received: by mail-pl1-x649.google.com with SMTP id i10-20020a1709026aca00b00158f14b4f2fso3812807plt.2 for ; Mon, 18 Apr 2022 23:58:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=mjj9/ZURjjtGQaz2LLl2krlBnNho3fyEfvR2R+fnkyk=; b=Cx/niwv6W7Y06XURKByUCxiOI2JS42u8ZRsB4Jd/xNk9tuJcTxkf6DGO2ozYf4I2US ZU5gnlaHf3BOrOeCv/etuwgapIvL2bqk3oDXaueadh0neyRo+SRUNGL8votl7vplAKIM sHEcbNzdEG1JDsorZDIsYKh0benCQF67aJbA83qbMyT0rAqvaaie74ccZbn2UKz7aKPj rdih6zJ2hBj5+wcu/NsMPytHpAWF1ZDLiIr+vMhcou+4/o0JwtMNZ0uLdoKh4FJr+/Aw 2l9wU0ZAeDtDkWgA6X6SW5F7yr+BUmvcruGK7QcRMj4E99qkjqwTBZGm703z1PFKPYWV fU1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=mjj9/ZURjjtGQaz2LLl2krlBnNho3fyEfvR2R+fnkyk=; b=3bownD854rG6z+K4Lc0I+1loMEVhJ5VYCJyrARdI2zwbdqsmE5MFqQ/4L0zi8MYoHl cEaHX2FC3N8nHr/FfWQP6LBZD6slngv6T5EO5NOYhzOXn8xyfZVEuDNbzW/Nq1LemUOy 35Q9STg8tAgCWhoQq8ArXX5kaMYjKfhSf60YrCXd7O/Rn+2oPQedNagm8rdrzr0B+UCt UF2fANmtyUgWGV/ce5WA8ph6iRPvp3U9Ls9pqU9z2hdyjz6qyzXvjEiedsMsp4i5gxKV lE8GmP7/AfUtHV8eITt9deWTZZqiDfDENlxyT6ytvUSJDETr11w1gH/NxY5kYmowVoI5 W8pg== X-Gm-Message-State: AOAM533kula4OowhfpPMv7NboMnYmJvMpl/Gpyfm14DyAXf9lquqL+qM 7MzQrK6hXsZDS4y57i9gk6SXA6EEF2k= X-Google-Smtp-Source: ABdhPJxetHGB4V+UPVW7WLQKsn2PTcz1+SOcEmT+cqxyd2F8wg7N+PKJyvCJRL8FQa0pqjwk4Zbwsa8b0eQ= X-Received: from reiji-vws-sp.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3d59]) (user=reijiw job=sendgmr) by 2002:a17:90b:2384:b0:1cb:5223:9dc4 with SMTP id mr4-20020a17090b238400b001cb52239dc4mr276931pjb.1.1650351487187; Mon, 18 Apr 2022 23:58:07 -0700 (PDT) Date: Mon, 18 Apr 2022 23:55:44 -0700 In-Reply-To: <20220419065544.3616948-1-reijiw@google.com> Message-Id: <20220419065544.3616948-39-reijiw@google.com> Mime-Version: 1.0 References: <20220419065544.3616948-1-reijiw@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH v7 38/38] KVM: arm64: selftests: Test breakpoint/watchpoint changing ID_AA64DFR0_EL1 From: Reiji Watanabe To: Marc Zyngier , kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Oliver Upton , Jing Zhang , Raghavendra Rao Anata , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220418_235809_163865_BB6C7CB8 X-CRM114-Status: GOOD ( 14.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add test cases that uses every breakpoint/watchpoint with various combination of ID_AA64DFR0_EL1.BRPs, WRPs, and CTX_CMPs configuration to the debug-exceptions test. Signed-off-by: Reiji Watanabe --- .../selftests/kvm/aarch64/debug-exceptions.c | 52 ++++++++++++++++--- 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c index 829fad6c7d58..d8ebbb7985da 100644 --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c @@ -701,18 +701,19 @@ static void check_debug_regs(struct kvm_vm *vm, uint32_t vcpu, } } -void run_test(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) +void run_test(uint64_t aa64dfr0, uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn) { struct kvm_vm *vm; struct ucall uc; int stage; - uint64_t aa64dfr0; uint8_t nbps, nwps; bool debug_reg_test = false; - pr_debug("%s bpn:%d, wpn:%d, ctx_bpn:%d\n", __func__, bpn, wpn, ctx_bpn); - + pr_debug("%s aa64dfr0:0x%lx, bpn:%d, wpn:%d, ctx_bpn:%d\n", __func__, + aa64dfr0, bpn, wpn, ctx_bpn); vm = vm_create_default(VCPU_ID, 0, guest_code); + set_reg(vm, VCPU_ID, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), aa64dfr0); + ucall_init(vm, NULL); vm_init_descriptor_tables(vm); @@ -810,15 +811,33 @@ void test_debug(uint64_t aa64dfr0) for (c = ctx_brp_base; c < ctx_brp_base + ctx_brp_num; c++) { for (b = 0; b < normal_brp_num; b++) { for (w = 0; w < wrp_num; w++) - run_test(b, w, c); + run_test(aa64dfr0, b, w, c); } } } +uint64_t update_aa64dfr0_bwrp(uint64_t dfr0, uint8_t brps, uint8_t wrps, + uint8_t ctx_brps) +{ + /* Clear brps/wrps/ctx_cmps fields */ + dfr0 &= ~(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS) | + ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS) | + ARM64_FEATURE_MASK(ID_AA64DFR0_CTX_CMPS)); + + /* Set new brps/wrps/ctx_cmps fields */ + dfr0 |= ((uint64_t)brps << ID_AA64DFR0_BRPS_SHIFT) | + ((uint64_t)wrps << ID_AA64DFR0_WRPS_SHIFT) | + ((uint64_t)ctx_brps << ID_AA64DFR0_CTX_CMPS_SHIFT); + + return dfr0; +} + int main(int argc, char *argv[]) { struct kvm_vm *vm; - uint64_t aa64dfr0; + uint64_t aa64dfr0, test_aa64dfr0; + uint8_t max_brps, max_wrps, max_ctx_brps; + int bs, ws, cs; vm = vm_create_default(VCPU_ID, 0, guest_code); get_reg(vm, VCPU_ID, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0); @@ -831,5 +850,26 @@ int main(int argc, char *argv[]) /* Run debug tests with the default configuration */ test_debug(aa64dfr0); + + if (!kvm_check_cap(KVM_CAP_ARM_ID_REG_CONFIGURABLE)) + return 0; + + /* + * Run debug tests with various number of breakpoints/watchpoints + * configuration. + */ + max_brps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_BRPS_SHIFT); + max_wrps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_WRPS_SHIFT); + max_ctx_brps = cpuid_extract_uftr(aa64dfr0, ID_AA64DFR0_CTX_CMPS_SHIFT); + for (cs = 0; cs <= max_ctx_brps; cs++) { + for (bs = cs + 1; bs <= max_brps; bs++) { + for (ws = 1; ws <= max_wrps; ws++) { + test_aa64dfr0 = update_aa64dfr0_bwrp(aa64dfr0, + bs, ws, cs); + test_debug(test_aa64dfr0); + } + } + } + return 0; }