From patchwork Wed Apr 20 13:05:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15D47C433F5 for ; Wed, 20 Apr 2022 13:06:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378780AbiDTNI4 (ORCPT ); Wed, 20 Apr 2022 09:08:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378819AbiDTNIl (ORCPT ); Wed, 20 Apr 2022 09:08:41 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E551286E1; Wed, 20 Apr 2022 06:05:45 -0700 (PDT) X-UUID: defc8dd51a014042b5d64d21727e5c0e-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:1649d3bc-bfe4-4447-bb06-76f0437c0d39,OB:-327 68,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Rele ase_Ham,ACTION:release,TS:-20 X-CID-INFO: VERSION:1.1.4,REQID:1649d3bc-bfe4-4447-bb06-76f0437c0d39,OB:-32768 ,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Releas e_Ham,ACTION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:6de286ef-06b0-4305-bfbf-554bfc9d151a,C OID:nil,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: defc8dd51a014042b5d64d21727e5c0e-20220420 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 307794123; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:28 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 01/12] clk: mediatek: reset: Fix written reset bit offset Date: Wed, 20 Apr 2022 21:05:16 +0800 Message-ID: <20220420130527.23200-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/reset.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index bcec4b89f449..834d26e9bdfd 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -25,7 +25,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4); - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, @@ -34,7 +34,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_assert(struct reset_controller_dev *rcdev, From patchwork Wed Apr 20 13:05:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 165D1C433FE for ; Wed, 20 Apr 2022 13:06:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378777AbiDTNIx (ORCPT ); Wed, 20 Apr 2022 09:08:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378832AbiDTNIr (ORCPT ); Wed, 20 Apr 2022 09:08:47 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75DC8427D6; Wed, 20 Apr 2022 06:05:47 -0700 (PDT) X-UUID: 1b40d179d0b746478f4e4c7697dcf631-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:40768c13-a39f-47a0-8041-f46edf4739bf,OB:-327 68,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Rele ase_Ham,ACTION:release,TS:-20 X-CID-INFO: VERSION:1.1.4,REQID:40768c13-a39f-47a0-8041-f46edf4739bf,OB:-32768 ,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Releas e_Ham,ACTION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:f4e55cf0-da02-41b4-b6df-58f4ccd36682,C OID:nil,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 1b40d179d0b746478f4e4c7697dcf631-20220420 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1112856766; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Apr 2022 21:05:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:29 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 02/12] clk: mediatek: reset: Use simple reset operations Date: Wed, 20 Apr 2022 21:05:17 +0800 Message-ID: <20220420130527.23200-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There are two version for clock reset register control of MediaTek SoCs. The reset operations before MT8183 can use simple reset to cover. Therefore, we replace mtk_reset_ops with reset_simple_ops. In addition, we also rename mtk_register_reset_controller to mtk_register_reset_controller_simple. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/Kconfig | 1 + drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +-- drivers/clk/mediatek/clk-mt2712.c | 4 +-- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +-- drivers/clk/mediatek/clk-mt7622.c | 4 +-- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +-- drivers/clk/mediatek/clk-mt8135.c | 4 +-- drivers/clk/mediatek/clk-mt8173.c | 4 +-- drivers/clk/mediatek/clk-mtk.h | 6 ++-- drivers/clk/mediatek/reset.c | 43 +++------------------------ 15 files changed, 27 insertions(+), 61 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 01ef02c54725..df2cdaa975e4 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -8,6 +8,7 @@ menu "Clock driver for MediaTek SoC" config COMMON_CLK_MEDIATEK tristate select RESET_CONTROLLER + select RESET_SIMPLE help MediaTek SoCs' clock support. diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 100ff6ca609e..1a6318fbcb32 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 1328c112a38f..0cd6b57657b3 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0xc); + mtk_register_reset_controller_simple(node, 1, 0xc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 61444881c539..883a23bb024d 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 1eb3e4563c3f..3f6508ff8e7f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); return 0; } @@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller_simple(node, 2, 0x0); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index ff72b9ab945b..9b4470ac7be7 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); return r; } @@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_simple(node, 2, 0); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index c9947dc7ba5a..647bf752a8af 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 628be0c9f888..1287db1e3cc2 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return r; } @@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 0e1fb30a1e98..2b744afd9233 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 1, 0x30); + mtk_register_reset_controller_simple(node, 1, 0x30); return 0; } @@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller_simple(node, 2, 0x0); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 88279d0ea1a7..0fb5780ae048 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 5c5b37207afb..6f7d013814ac 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return r; } @@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller_simple(node, 1, 0x34); return r; } diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 09ad272d51f1..476c6fb5fc5d 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_simple(node, 2, 0); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 46b7655feeaa..92beb45de8a0 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller_simple(node, 2, 0x30); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller_simple(node, 2, 0); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bf6565aa7319..f767c9585d8c 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -190,11 +190,11 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs); +void mtk_register_reset_controller_simple(struct device_node *np, + unsigned int num_regs, int regofs); void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs); + unsigned int num_regs, int regofs); struct mtk_clk_desc { const struct mtk_gate *clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 834d26e9bdfd..9110d0b4229f 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "clk-mtk.h" @@ -37,36 +38,6 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, return regmap_write(data->regmap, reg, BIT(id % 32)); } -static int mtk_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), ~0); -} - -static int mtk_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), 0); -} - -static int mtk_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - int ret; - - ret = mtk_reset_assert(rcdev, id); - if (ret) - return ret; - - return mtk_reset_deassert(rcdev, id); -} - static int mtk_reset_set_clr(struct reset_controller_dev *rcdev, unsigned long id) { @@ -78,12 +49,6 @@ static int mtk_reset_set_clr(struct reset_controller_dev *rcdev, return mtk_reset_deassert_set_clr(rcdev, id); } -static const struct reset_control_ops mtk_reset_ops = { - .assert = mtk_reset_assert, - .deassert = mtk_reset_deassert, - .reset = mtk_reset, -}; - static const struct reset_control_ops mtk_reset_ops_set_clr = { .assert = mtk_reset_assert_set_clr, .deassert = mtk_reset_deassert_set_clr, @@ -123,18 +88,18 @@ static void mtk_register_reset_controller_common(struct device_node *np, } } -void mtk_register_reset_controller(struct device_node *np, +void mtk_register_reset_controller_simple(struct device_node *np, unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops); + &reset_simple_ops); } void mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_set_clr); + &mtk_reset_ops_set_clr); } MODULE_LICENSE("GPL"); From patchwork Wed Apr 20 13:05:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D6EBC433EF for ; Wed, 20 Apr 2022 13:05:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378746AbiDTNIW (ORCPT ); Wed, 20 Apr 2022 09:08:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378730AbiDTNIW (ORCPT ); Wed, 20 Apr 2022 09:08:22 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A22C222AC; Wed, 20 Apr 2022 06:05:35 -0700 (PDT) X-UUID: 8efc8a194b904a08b4a9be22b1302d1a-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:afe8f461-0493-4026-80dd-6d9311084c55,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:f2e55cf0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 8efc8a194b904a08b4a9be22b1302d1a-20220420 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1575507492; Wed, 20 Apr 2022 21:05:31 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 20 Apr 2022 21:05:29 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:29 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 03/12] clk: mediatek: reset: Refine functions of set_clr Date: Wed, 20 Apr 2022 21:05:18 +0800 Message-ID: <20220420130527.23200-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To make driver more readable, revise functions of set_clr. - Add to_rst_data(). - Extract common code within assert and deassert to mtk_reset_update_set_clr(). Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/reset.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 9110d0b4229f..6574b19daf0f 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -20,26 +20,36 @@ struct mtk_reset { struct reset_controller_dev rcdev; }; -static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static inline struct mtk_reset *to_rst_data(struct reset_controller_dev *rcdev) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - unsigned int reg = data->regofs + ((id / 32) << 4); + return container_of(rcdev, struct mtk_reset, rcdev); +} - return regmap_write(data->regmap, reg, BIT(id % 32)); +static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev, + unsigned long id, bool deassert) +{ + struct mtk_reset *data = to_rst_data(rcdev); + unsigned int deassert_ofs = deassert ? 0x4 : 0; + + return regmap_write(data->regmap, + data->regofs + ((id / 32) << 4) + deassert_ofs, + BIT(id % 32)); } -static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, + unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; + return mtk_reset_update_set_clr(rcdev, id, false); +} - return regmap_write(data->regmap, reg, BIT(id % 32)); +static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return mtk_reset_update_set_clr(rcdev, id, true); } static int mtk_reset_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) + unsigned long id) { int ret; From patchwork Wed Apr 20 13:05:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7806C433F5 for ; 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Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:29 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 04/12] clk: mediatek: reset: Merge and revise reset register function Date: Wed, 20 Apr 2022 21:05:19 +0800 Message-ID: <20220420130527.23200-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Merge the reset register function of simple and set_clr into one function. - Input the version number to determine which version we will use. - Rename reset register function to "mtk_clk_register_rst_ctrl" Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +-- drivers/clk/mediatek/clk-mt2712.c | 4 +-- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +-- drivers/clk/mediatek/clk-mt7622.c | 4 +-- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +-- drivers/clk/mediatek/clk-mt8135.c | 4 +-- drivers/clk/mediatek/clk-mt8173.c | 4 +-- drivers/clk/mediatek/clk-mt8183.c | 3 ++- drivers/clk/mediatek/clk-mtk.h | 13 ++++++---- drivers/clk/mediatek/reset.c | 35 ++++++++++++--------------- 15 files changed, 44 insertions(+), 45 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 1a6318fbcb32..85a993279506 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 0cd6b57657b3..42b9ec1bc926 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0xc); + mtk_clk_register_rst_ctrl(node, 1, 0xc, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 883a23bb024d..f20e9b1033e7 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 3f6508ff8e7f..e6ff09b2f915 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller_simple(node, 2, 0x30); + mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); return 0; } @@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller_simple(node, 2, 0x0); + mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_SIMPLE); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 9b4470ac7be7..d337ca91de60 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller_simple(node, 2, 0x30); + mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); return r; } @@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller_simple(node, 2, 0); + mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 647bf752a8af..ac3bf5aba73b 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 1287db1e3cc2..5041126852b6 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return r; } @@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 2b744afd9233..d453a2db0da7 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller_simple(node, 1, 0x30); + mtk_clk_register_rst_ctrl(node, 1, 0x30, MTK_RST_SIMPLE); return 0; } @@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_register_reset_controller_simple(node, 2, 0x0); + mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_SIMPLE); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 0fb5780ae048..6baf515591f3 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 6f7d013814ac..2f27dac66e38 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return r; } @@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller_simple(node, 1, 0x34); + mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 476c6fb5fc5d..fa860e3b2257 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller_simple(node, 2, 0x30); + mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller_simple(node, 2, 0); + mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 92beb45de8a0..13ec0e4bdf5c 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller_simple(node, 2, 0x30); + mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller_simple(node, 2, 0); + mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 68496554dd3d..82a0a4980180 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1239,7 +1239,8 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); + mtk_clk_register_rst_ctrl(node, 4, + INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR); return r; } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f767c9585d8c..399f1b2dc7d0 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -178,6 +178,12 @@ struct mtk_clk_divider { .div_width = _width, \ } +enum mtk_reset_version { + MTK_RST_SIMPLE = 0, + MTK_RST_SET_CLR, + MTK_RST_MAX, +}; + int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); @@ -190,11 +196,8 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -void mtk_register_reset_controller_simple(struct device_node *np, - unsigned int num_regs, int regofs); - -void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs); +void mtk_clk_register_rst_ctrl(struct device_node *np, + u32 reg_num, u16 reg_ofs, u8 version); struct mtk_clk_desc { const struct mtk_gate *clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 6574b19daf0f..8e42deee80a3 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -65,14 +65,23 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { .reset = mtk_reset_set_clr, }; -static void mtk_register_reset_controller_common(struct device_node *np, - unsigned int num_regs, int regofs, - const struct reset_control_ops *reset_ops) +static const struct reset_control_ops *rst_op[MTK_RST_MAX] = { + [MTK_RST_SIMPLE] = &reset_simple_ops, + [MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr, +}; + +void mtk_clk_register_rst_ctrl(struct device_node *np, + u32 reg_num, u16 reg_ofs, u8 version) { struct mtk_reset *data; int ret; struct regmap *regmap; + if (version >= MTK_RST_MAX) { + pr_err("Error version number: %d\n", version); + return; + } + regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); @@ -84,10 +93,10 @@ static void mtk_register_reset_controller_common(struct device_node *np, return; data->regmap = regmap; - data->regofs = regofs; + data->regofs = reg_ofs; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = num_regs * 32; - data->rcdev.ops = reset_ops; + data->rcdev.nr_resets = reg_num * 32; + data->rcdev.ops = rst_op[version]; data->rcdev.of_node = np; ret = reset_controller_register(&data->rcdev); @@ -98,18 +107,4 @@ static void mtk_register_reset_controller_common(struct device_node *np, } } -void mtk_register_reset_controller_simple(struct device_node *np, - unsigned int num_regs, int regofs) -{ - mtk_register_reset_controller_common(np, num_regs, regofs, - &reset_simple_ops); -} - -void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs) -{ - mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_set_clr); -} - MODULE_LICENSE("GPL"); From patchwork Wed Apr 20 13:05:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10834C433FE for ; Wed, 20 Apr 2022 13:05:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378730AbiDTNIY (ORCPT ); Wed, 20 Apr 2022 09:08:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378768AbiDTNIX (ORCPT ); Wed, 20 Apr 2022 09:08:23 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B9206565; Wed, 20 Apr 2022 06:05:36 -0700 (PDT) X-UUID: 60bf66f04d894c8aad5d62b60bd90a51-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:9284b2f5-242d-4a42-a004-4c587fbf2626,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:2ce65cf0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 60bf66f04d894c8aad5d62b60bd90a51-20220420 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1813227716; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:29 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 05/12] clk: mediatek: reset: Add reset.h Date: Wed, 20 Apr 2022 21:05:20 +0800 Message-ID: <20220420130527.23200-6-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a new file "reset.h" to place some definitions for clock reset. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mtk.h | 11 ++--------- drivers/clk/mediatek/reset.h | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 9 deletions(-) create mode 100644 drivers/clk/mediatek/reset.h diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 399f1b2dc7d0..a6d0f24c62fa 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -13,6 +13,8 @@ #include #include +#include "reset.h" + #define MAX_MUX_GATE_BIT 31 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) @@ -178,12 +180,6 @@ struct mtk_clk_divider { .div_width = _width, \ } -enum mtk_reset_version { - MTK_RST_SIMPLE = 0, - MTK_RST_SET_CLR, - MTK_RST_MAX, -}; - int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); @@ -196,9 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -void mtk_clk_register_rst_ctrl(struct device_node *np, - u32 reg_num, u16 reg_ofs, u8 version); - struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h new file mode 100644 index 000000000000..e4081c7217e3 --- /dev/null +++ b/drivers/clk/mediatek/reset.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __DRV_CLK_MTK_RESET_H +#define __DRV_CLK_MTK_RESET_H + +#include + +enum mtk_reset_version { + MTK_RST_SIMPLE = 0, + MTK_RST_SET_CLR, + MTK_RST_MAX, +}; + +void mtk_clk_register_rst_ctrl(struct device_node *np, + u32 reg_num, u16 reg_ofs, u8 version); + +#endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 20 13:05:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5305CC433EF for ; Wed, 20 Apr 2022 13:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378787AbiDTNI1 (ORCPT ); Wed, 20 Apr 2022 09:08:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378774AbiDTNIY (ORCPT ); Wed, 20 Apr 2022 09:08:24 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28D3340E6B; Wed, 20 Apr 2022 06:05:36 -0700 (PDT) X-UUID: f040cd105bfe4368982faccdc4cf3817-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:a4f6cd21-4cfc-4b4c-a27c-f102d8c825ed,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:f5e55cf0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: f040cd105bfe4368982faccdc4cf3817-20220420 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1747573874; Wed, 20 Apr 2022 21:05:31 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 20 Apr 2022 21:05:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:29 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 06/12] clk: mediatek: reset: Revise structure to control reset register Date: Wed, 20 Apr 2022 21:05:21 +0800 Message-ID: <20220420130527.23200-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add mtk_clk_rst_desc to input the reset register data, and replace the structure "struct mtk_reset" to reset.h, and rename it as "mtk_clk_rst_data". We use them to store reset register data and store reset controller device. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt2701-eth.c | 8 +++++- drivers/clk/mediatek/clk-mt2701-g3d.c | 8 +++++- drivers/clk/mediatek/clk-mt2701-hif.c | 8 +++++- drivers/clk/mediatek/clk-mt2701.c | 19 ++++++++++++-- drivers/clk/mediatek/clk-mt2712.c | 19 ++++++++++++-- drivers/clk/mediatek/clk-mt7622-eth.c | 8 +++++- drivers/clk/mediatek/clk-mt7622-hif.c | 10 ++++++-- drivers/clk/mediatek/clk-mt7622.c | 19 ++++++++++++-- drivers/clk/mediatek/clk-mt7629-eth.c | 8 +++++- drivers/clk/mediatek/clk-mt7629-hif.c | 10 ++++++-- drivers/clk/mediatek/clk-mt8135.c | 19 ++++++++++++-- drivers/clk/mediatek/clk-mt8173.c | 19 ++++++++++++-- drivers/clk/mediatek/clk-mt8183.c | 9 +++++-- drivers/clk/mediatek/reset.c | 36 +++++++++++++-------------- drivers/clk/mediatek/reset.h | 15 ++++++++++- 15 files changed, 174 insertions(+), 41 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 85a993279506..1c83ac4ee1a9 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -36,6 +36,12 @@ static const struct mtk_gate eth_clks[] = { GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static const struct of_device_id of_match_clk_mt2701_eth[] = { { .compatible = "mediatek,mt2701-ethsys", }, {} @@ -58,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 42b9ec1bc926..8b802083642e 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -35,6 +35,12 @@ static const struct mtk_gate g3d_clks[] = { GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0xc, +}; + static int clk_mt2701_g3dsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -52,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0xc, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index f20e9b1033e7..4bf57ed948dc 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -33,6 +33,12 @@ static const struct mtk_gate hif_clks[] = { GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static const struct of_device_id of_match_clk_mt2701_hif[] = { { .compatible = "mediatek,mt2701-hifsys", }, {} @@ -57,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index e6ff09b2f915..24af9588358c 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -735,6 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x0, + }, +}; + static struct clk_onecell_data *infra_clk_data; static void __init mtk_infrasys_init_early(struct device_node *node) @@ -785,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); return 0; } @@ -908,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index d337ca91de60..4942129bdd54 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1258,6 +1258,21 @@ static const struct mtk_pll_data plls[] = { 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infra */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x30, + }, + /* peri */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x0, + }, +}; + static int clk_mt2712_apmixed_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -1361,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); return r; } @@ -1383,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index ac3bf5aba73b..f822e8538037 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -65,6 +65,12 @@ static const struct mtk_gate sgmii_clks[] = { "ssusb_cdr_fb", 5), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7622_ethsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -82,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 5041126852b6..fee784fc3468 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -76,6 +76,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -93,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } @@ -115,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index d453a2db0da7..2bcd1d95f8f9 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -610,6 +610,21 @@ static struct mtk_composite peri_muxes[] = { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x0, + }, +}; + static int mtk_topckgen_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -663,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_clk_register_rst_ctrl(node, 1, 0x30, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); return 0; } @@ -714,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_clk_register_rst_ctrl(node, 2, 0x0, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 6baf515591f3..a6e53ce1a309 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -76,6 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = { } }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7629_ethsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -92,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 2f27dac66e38..db936bdb140f 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -71,6 +71,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .reg_num = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -88,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } @@ -110,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index fa860e3b2257..1353b1695742 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -514,6 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = { MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x0, + } +}; + static void __init mtk_topckgen_init(struct device_node *node) { struct clk_onecell_data *clk_data; @@ -559,7 +574,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -587,7 +602,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 13ec0e4bdf5c..07e406459866 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -819,6 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = { GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .reg_num = 2, + .reg_ofs = 0x0, + } +}; + static struct clk_onecell_data *mt8173_top_clk_data __initdata; static struct clk_onecell_data *mt8173_pll_clk_data __initdata; @@ -882,7 +897,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -910,7 +925,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, 2, 0, MTK_RST_SIMPLE); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 82a0a4980180..0130f0b1ceac 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1153,6 +1153,12 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SET_CLR, + .reg_num = 4, + .reg_ofs = INFRA_RST0_SET_OFFSET, +}; + static int clk_mt8183_apmixed_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -1239,8 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_clk_register_rst_ctrl(node, 4, - INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR); + mtk_clk_register_rst_ctrl(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 8e42deee80a3..d67c13958458 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -14,25 +14,19 @@ #include "clk-mtk.h" -struct mtk_reset { - struct regmap *regmap; - int regofs; - struct reset_controller_dev rcdev; -}; - -static inline struct mtk_reset *to_rst_data(struct reset_controller_dev *rcdev) +static inline struct mtk_clk_rst_data *to_rst_data(struct reset_controller_dev *rcdev) { - return container_of(rcdev, struct mtk_reset, rcdev); + return container_of(rcdev, struct mtk_clk_rst_data, rcdev); } static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev, unsigned long id, bool deassert) { - struct mtk_reset *data = to_rst_data(rcdev); + struct mtk_clk_rst_data *data = to_rst_data(rcdev); unsigned int deassert_ofs = deassert ? 0x4 : 0; return regmap_write(data->regmap, - data->regofs + ((id / 32) << 4) + deassert_ofs, + data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs, BIT(id % 32)); } @@ -71,14 +65,19 @@ static const struct reset_control_ops *rst_op[MTK_RST_MAX] = { }; void mtk_clk_register_rst_ctrl(struct device_node *np, - u32 reg_num, u16 reg_ofs, u8 version) + const struct mtk_clk_rst_desc *desc) { - struct mtk_reset *data; - int ret; struct regmap *regmap; + struct mtk_clk_rst_data *data; + int ret; - if (version >= MTK_RST_MAX) { - pr_err("Error version number: %d\n", version); + if (!desc) { + pr_err("mtk clock reset desc is NULL\n"); + return; + } + + if (desc->version >= MTK_RST_MAX) { + pr_err("Error version number: %d\n", desc->version); return; } @@ -92,18 +91,17 @@ void mtk_clk_register_rst_ctrl(struct device_node *np, if (!data) return; + data->desc = desc; data->regmap = regmap; - data->regofs = reg_ofs; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = reg_num * 32; - data->rcdev.ops = rst_op[version]; + data->rcdev.nr_resets = desc->reg_num * 32; + data->rcdev.ops = rst_op[desc->version]; data->rcdev.of_node = np; ret = reset_controller_register(&data->rcdev); if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); - return; } } diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index e4081c7217e3..3a93f61e106e 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -6,6 +6,7 @@ #ifndef __DRV_CLK_MTK_RESET_H #define __DRV_CLK_MTK_RESET_H +#include #include enum mtk_reset_version { @@ -14,7 +15,19 @@ enum mtk_reset_version { MTK_RST_MAX, }; +struct mtk_clk_rst_desc { + u8 version; + u32 reg_num; + u16 reg_ofs; +}; + +struct mtk_clk_rst_data { + struct regmap *regmap; + struct reset_controller_dev rcdev; + const struct mtk_clk_rst_desc *desc; +}; + void mtk_clk_register_rst_ctrl(struct device_node *np, - u32 reg_num, u16 reg_ofs, u8 version); + const struct mtk_clk_rst_desc *desc); #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 20 13:05:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F646C433FE for ; Wed, 20 Apr 2022 13:05:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378791AbiDTNI3 (ORCPT ); Wed, 20 Apr 2022 09:08:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378776AbiDTNIZ (ORCPT ); Wed, 20 Apr 2022 09:08:25 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70A3A6565; Wed, 20 Apr 2022 06:05:38 -0700 (PDT) X-UUID: 2bc8eefb15294387ab8c5cbb2af48cc0-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:fbf3316f-3d82-48f2-8099-cb368e871edf,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:30e65cf0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 2bc8eefb15294387ab8c5cbb2af48cc0-20220420 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1538950905; Wed, 20 Apr 2022 21:05:31 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:29 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 07/12] clk: mediatek: reset: Add return for clock reset register function Date: Wed, 20 Apr 2022 21:05:22 +0800 Message-ID: <20220420130527.23200-8-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To make error handling, we add return for mtk_clk_register_rst_ctrl(). Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/reset.c | 14 ++++++++------ drivers/clk/mediatek/reset.h | 4 ++-- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index d67c13958458..b164b1da7dd3 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -64,8 +64,8 @@ static const struct reset_control_ops *rst_op[MTK_RST_MAX] = { [MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr, }; -void mtk_clk_register_rst_ctrl(struct device_node *np, - const struct mtk_clk_rst_desc *desc) +int mtk_clk_register_rst_ctrl(struct device_node *np, + const struct mtk_clk_rst_desc *desc) { struct regmap *regmap; struct mtk_clk_rst_data *data; @@ -73,23 +73,23 @@ void mtk_clk_register_rst_ctrl(struct device_node *np, if (!desc) { pr_err("mtk clock reset desc is NULL\n"); - return; + return -EINVAL; } if (desc->version >= MTK_RST_MAX) { pr_err("Error version number: %d\n", desc->version); - return; + return -EINVAL; } regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); - return; + return -EINVAL; } data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return; + return -ENOMEM; data->desc = desc; data->regmap = regmap; @@ -103,6 +103,8 @@ void mtk_clk_register_rst_ctrl(struct device_node *np, pr_err("could not register reset controller: %d\n", ret); kfree(data); } + + return ret; } MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 3a93f61e106e..d59f4b89384d 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -27,7 +27,7 @@ struct mtk_clk_rst_data { const struct mtk_clk_rst_desc *desc; }; -void mtk_clk_register_rst_ctrl(struct device_node *np, - const struct mtk_clk_rst_desc *desc); +int mtk_clk_register_rst_ctrl(struct device_node *np, + const struct mtk_clk_rst_desc *desc); #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 20 13:05:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC4D0C433FE for ; Wed, 20 Apr 2022 13:06:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378834AbiDTNJA (ORCPT ); Wed, 20 Apr 2022 09:09:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378833AbiDTNIr (ORCPT ); Wed, 20 Apr 2022 09:08:47 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E823427DF; Wed, 20 Apr 2022 06:05:48 -0700 (PDT) X-UUID: ed446005ab06441e8a7c98830d14c3bd-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:e9a0b140-6418-4b94-8520-bd93f794bc32,OB:-327 68,LOB:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Rele ase_Ham,ACTION:release,TS:-12 X-CID-INFO: VERSION:1.1.4,REQID:e9a0b140-6418-4b94-8520-bd93f794bc32,OB:-32768 ,LOB:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Releas e_Ham,ACTION:release,TS:-12 X-CID-META: VersionHash:faefae9,CLOUDID:89e286ef-06b0-4305-bfbf-554bfc9d151a,C OID:nil,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: ed446005ab06441e8a7c98830d14c3bd-20220420 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 462038439; Wed, 20 Apr 2022 21:05:31 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:30 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 08/12] clk: mediatek: reset: Add new register reset function with device Date: Wed, 20 Apr 2022 21:05:23 +0800 Message-ID: <20220420130527.23200-9-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Some clock drvier only support device_node, so we still remain register reset function with device_node and add a function to register reset controller with device. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +-- drivers/clk/mediatek/clk-mt2712.c | 4 +-- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +-- drivers/clk/mediatek/clk-mt7622.c | 4 +-- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +-- drivers/clk/mediatek/clk-mt8183.c | 2 +- drivers/clk/mediatek/reset.c | 43 +++++++++++++++++++++++++++ drivers/clk/mediatek/reset.h | 2 ++ 13 files changed, 61 insertions(+), 16 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 1c83ac4ee1a9..d63b70eda7f5 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -64,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 8b802083642e..6fd9db8e81d6 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -58,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 4bf57ed948dc..2465dd95fd24 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -63,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 24af9588358c..8cc90b1218df 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -800,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc[0]); return 0; } @@ -923,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 4942129bdd54..20a613c3651e 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1376,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc[0]); return r; } @@ -1398,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc[1]); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index f822e8538037..c68a7990e7f3 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -88,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index fee784fc3468..ecb6b3732b72 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -99,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } @@ -121,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 2bcd1d95f8f9..26bcaabb1f40 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -678,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_clk_register_rst_ctrl(node, &clk_rst_desc[0]); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc[0]); return 0; } @@ -729,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc[1]); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index a6e53ce1a309..6cf6fb4b55d1 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -98,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index db936bdb140f..975ba8ec523f 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -94,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } @@ -116,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 0130f0b1ceac..e0bb6b0d2740 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1245,7 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_clk_register_rst_ctrl(node, &clk_rst_desc); + mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index b164b1da7dd3..1173111af3ab 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -107,4 +107,47 @@ int mtk_clk_register_rst_ctrl(struct device_node *np, return ret; } +int mtk_clk_register_rst_ctrl_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc) +{ + struct device_node *np = dev->of_node; + struct regmap *regmap; + struct mtk_clk_rst_data *data; + int ret; + + if (!desc) { + dev_err(dev, "mtk clock reset desc is NULL\n"); + return -EINVAL; + } + + if (desc->version >= MTK_RST_MAX) { + dev_err(dev, "Error version number: %d\n", desc->version); + return -EINVAL; + } + + regmap = device_node_to_regmap(np); + if (IS_ERR(regmap)) { + dev_err(dev, "Cannot find regmap %pe\n", regmap); + return -EINVAL; + } + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->desc = desc; + data->regmap = regmap; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = desc->reg_num * 32; + data->rcdev.ops = rst_op[desc->version]; + data->rcdev.of_node = np; + data->rcdev.dev = dev; + + ret = devm_reset_controller_register(dev, &data->rcdev); + if (ret) + dev_err(dev, "could not register reset controller: %d\n", ret); + + return ret; +} + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index d59f4b89384d..30559bf45f7e 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -29,5 +29,7 @@ struct mtk_clk_rst_data { int mtk_clk_register_rst_ctrl(struct device_node *np, const struct mtk_clk_rst_desc *desc); +int mtk_clk_register_rst_ctrl_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc); #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 20 13:05:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2024BC433EF for ; Wed, 20 Apr 2022 13:06:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378783AbiDTNIz (ORCPT ); Wed, 20 Apr 2022 09:08:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378823AbiDTNIl (ORCPT ); Wed, 20 Apr 2022 09:08:41 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30E70427C4; Wed, 20 Apr 2022 06:05:46 -0700 (PDT) X-UUID: 9d03251d37334502ab98191096065420-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:03800ecb-71ba-4c86-ae42-8c63d2194638,OB:-327 68,LOB:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Rele ase_Ham,ACTION:release,TS:-12 X-CID-INFO: VERSION:1.1.4,REQID:03800ecb-71ba-4c86-ae42-8c63d2194638,OB:-32768 ,LOB:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Releas e_Ham,ACTION:release,TS:-12 X-CID-META: VersionHash:faefae9,CLOUDID:2be65cf0-da02-41b4-b6df-58f4ccd36682,C OID:nil,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 9d03251d37334502ab98191096065420-20220420 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 200531248; Wed, 20 Apr 2022 21:05:31 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:30 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 09/12] clk: mediatek: reset: Add support for input offset and bit from DT Date: Wed, 20 Apr 2022 21:05:24 +0800 Message-ID: <20220420130527.23200-10-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To use the clock reset function easier, we implement the of_xlate. This function is only adopted in version MTK_SET_CLR because of the method of id calculation. There is no impact for original use. If the argument number is not larger than 1, it will return original id. With this implementation if we want to set offset 0x120 and bit 16, we can just write something like "resets = <&infra_rst 0x120 16>;". Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/reset.c | 24 ++++++++++++++++++++++++ drivers/clk/mediatek/reset.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 1173111af3ab..dbe812062bf5 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -59,6 +59,20 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { .reset = mtk_reset_set_clr, }; +static int reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int offset, bit; + + if (reset_spec->args_count <= 1) + return reset_spec->args[0]; + + offset = reset_spec->args[0]; + bit = reset_spec->args[1]; + + return (offset >> 4) * 32 + bit; +} + static const struct reset_control_ops *rst_op[MTK_RST_MAX] = { [MTK_RST_SIMPLE] = &reset_simple_ops, [MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr, @@ -98,6 +112,11 @@ int mtk_clk_register_rst_ctrl(struct device_node *np, data->rcdev.ops = rst_op[desc->version]; data->rcdev.of_node = np; + if (desc->version == MTK_RST_SET_CLR) { + data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1); + data->rcdev.of_xlate = reset_xlate; + } + ret = reset_controller_register(&data->rcdev); if (ret) { pr_err("could not register reset controller: %d\n", ret); @@ -143,6 +162,11 @@ int mtk_clk_register_rst_ctrl_with_dev(struct device *dev, data->rcdev.of_node = np; data->rcdev.dev = dev; + if (desc->version == MTK_RST_SET_CLR) { + data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1); + data->rcdev.of_xlate = reset_xlate; + } + ret = devm_reset_controller_register(dev, &data->rcdev); if (ret) dev_err(dev, "could not register reset controller: %d\n", ret); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 30559bf45f7e..4cfc281fc50d 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -19,6 +19,7 @@ struct mtk_clk_rst_desc { u8 version; u32 reg_num; u16 reg_ofs; + int reset_n_cells; }; struct mtk_clk_rst_data { From patchwork Wed Apr 20 13:05:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF5ABC433F5 for ; Wed, 20 Apr 2022 13:05:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378785AbiDTNIl (ORCPT ); Wed, 20 Apr 2022 09:08:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378779AbiDTNIZ (ORCPT ); Wed, 20 Apr 2022 09:08:25 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 285AF4249F; Wed, 20 Apr 2022 06:05:39 -0700 (PDT) X-UUID: 314f765b08ed49e38d5ce56b476bdac2-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:0e7c4eae-d226-4bd9-884a-8fd55c72ac49,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:15e65cf0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 314f765b08ed49e38d5ce56b476bdac2-20220420 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1836451480; Wed, 20 Apr 2022 21:05:32 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:30 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 10/12] clk: mediatek: reset: Add reset support for simple probe Date: Wed, 20 Apr 2022 21:05:25 +0800 Message-ID: <20220420130527.23200-11-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org - Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc". - Add register reset with device function in mtk_clk_simple_probe(). Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mtk.c | 7 +++++++ drivers/clk/mediatek/clk-mtk.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4063261cf56..8d64094f51fc 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -453,6 +453,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev) platform_set_drvdata(pdev, clk_data); + if (mcd->rst_desc) { + r = mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, + mcd->rst_desc); + if (r) + goto unregister_clks; + } + return r; unregister_clks: diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index a6d0f24c62fa..2c7800bcb1a2 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -195,6 +195,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name, struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; + const struct mtk_clk_rst_desc *rst_desc; }; int mtk_clk_simple_probe(struct platform_device *pdev); From patchwork Wed Apr 20 13:05:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7611C433F5 for ; Wed, 20 Apr 2022 13:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378782AbiDTNI0 (ORCPT ); Wed, 20 Apr 2022 09:08:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378773AbiDTNIY (ORCPT ); Wed, 20 Apr 2022 09:08:24 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28AD8222AC; Wed, 20 Apr 2022 06:05:37 -0700 (PDT) X-UUID: 4a7794cfb1334ff78f2ef6ee569b40a5-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:82528a0a-2cf6-477e-a1bb-8f6a0b76cbe3,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:1ee65cf0-da02-41b4-b6df-58f4ccd36682,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 4a7794cfb1334ff78f2ef6ee569b40a5-20220420 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1192217164; Wed, 20 Apr 2022 21:05:32 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:30 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 11/12] clk: mediatek: reset: Add infra_ao reset support for MT8192 Date: Wed, 20 Apr 2022 21:05:26 +0800 Message-ID: <20220420130527.23200-12-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The infra_ao reset is needed for MT8192. Therefore, we add this patch to support it. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 11 +++++++++++ include/dt-bindings/reset/mt8192-resets.h | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index ab27cd66b866..7926b83b9035 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1114,6 +1114,13 @@ static const struct mtk_gate top_clks[] = { GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SET_CLR, + .reg_num = 4, + .reg_ofs = 0x0, + .reset_n_cells = 2, +}; + #define MT8192_PLL_FMAX (3800UL * MHZ) #define MT8192_PLL_FMIN (1500UL * MHZ) #define MT8192_INTEGER_BITS 8 @@ -1239,6 +1246,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) if (r) goto free_clk_data; + r = mtk_clk_register_rst_ctrl_with_dev(&pdev->dev, &clk_rst_desc); + if (r) + goto free_clk_data; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) goto free_clk_data; diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index be9a7ca245b9..feac1ac85906 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 +/* TOPRGU */ #define MT8192_TOPRGU_MM_SW_RST 1 #define MT8192_TOPRGU_MFG_SW_RST 2 #define MT8192_TOPRGU_VENC_SW_RST 3 @@ -27,4 +28,14 @@ #define MT8192_TOPRGU_SW_RST_NUM 23 +/* INFRA RST0 */ +#define MT8192_INFRA_RST0_LVTS_AP_RST 0 +/* INFRA RST2 */ +#define MT8192_INFRA_RST2_PCIE_PHY_RST 15 +/* INFRA RST3 */ +#define MT8192_INFRA_RST3_PTP_RST 5 +/* INFRA RST4 */ +#define MT8192_INFRA_RST4_LVTS_MCU 12 +#define MT8192_INFRA_RST4_PCIE_TOP 1 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ From patchwork Wed Apr 20 13:05:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12820198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57480C433EF for ; Wed, 20 Apr 2022 13:06:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378807AbiDTNIu (ORCPT ); Wed, 20 Apr 2022 09:08:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378657AbiDTNIq (ORCPT ); Wed, 20 Apr 2022 09:08:46 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D861427D1; Wed, 20 Apr 2022 06:05:47 -0700 (PDT) X-UUID: a832f43702ba49f3992d8f894cb6d5b3-20220420 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:d1617706-0ae9-4226-a466-0bfa4300b41d,OB:-327 68,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Rele ase_Ham,ACTION:release,TS:-20 X-CID-INFO: VERSION:1.1.4,REQID:d1617706-0ae9-4226-a466-0bfa4300b41d,OB:-32768 ,LOB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:-32768,FILE:0,RULE:Releas e_Ham,ACTION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:19e65cf0-da02-41b4-b6df-58f4ccd36682,C OID:nil,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: a832f43702ba49f3992d8f894cb6d5b3-20220420 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1398211166; Wed, 20 Apr 2022 21:05:32 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 20 Apr 2022 21:05:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Apr 2022 21:05:30 +0800 From: Rex-BC Chen To: , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V2 12/12] clk: mediatek: reset: Add infra_ao reset support for MT8195 Date: Wed, 20 Apr 2022 21:05:27 +0800 Message-ID: <20220420130527.23200-13-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220420130527.23200-1-rex-bc.chen@mediatek.com> References: <20220420130527.23200-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The infra_ao reset is needed for MT8195. Therefore, we add this patch to support it. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8195-infra_ao.c | 8 ++++++++ include/dt-bindings/reset/mt8195-resets.h | 7 +++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 8ebe3b9415c4..31d0039250dc 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -182,9 +182,17 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31), }; +static struct mtk_clk_rst_desc infra_ao_rst_desc = { + .version = MTK_RST_SET_CLR, + .reg_num = 4, + .reg_ofs = 0x0, + .reset_n_cells = 2, +}; + static const struct mtk_clk_desc infra_ao_desc = { .clks = infra_ao_clks, .num_clks = ARRAY_SIZE(infra_ao_clks), + .rst_desc = &infra_ao_rst_desc, }; static const struct of_device_id of_match_clk_mt8195_infra_ao[] = { diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..2479680616fb 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -26,4 +26,11 @@ #define MT8195_TOPRGU_SW_RST_NUM 16 +/* INFRA RST0 */ +#define MT8195_INFRA_RST0_THERMAL_AP_RST 0 +/* INFRA RST3 */ +#define MT8195_INFRA_RST3_PTP_RST 5 +/* INFRA RST4 */ +#define MT8195_INFRA_RST4_THERMAL_MCU_RST 10 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */