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* L2_1: l2-cache { * compatible = "cache"; * next-level-cache = <&L3_1>; * }; * L3_1: l3-cache { * compatible = "cache"; * }; * }; * * cpu1: cpu@001 { * next-level-cache = <&L2_1>; * }; * ... * }; cache_topology hold the pointer describing "next-level-cache", it can describe the cache topology of every level. Signed-off-by: Wang Qing Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/base/arch_topology.c | 47 ++++++++++++++++++++++++++++++++++- include/linux/arch_topology.h | 3 +++ 2 files changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index 1d6636ebaac5..46e84ce2ec0c 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -480,8 +480,10 @@ static int __init get_cpu_for_node(struct device_node *node) return -1; cpu = of_cpu_node_to_id(cpu_node); - if (cpu >= 0) + if (cpu >= 0) { topology_parse_cpu_capacity(cpu_node, cpu); + topology_parse_cpu_caches(cpu_node, cpu); + } else pr_info("CPU node for %pOF exist but the possible cpu range is :%*pbl\n", cpu_node, cpumask_pr_args(cpu_possible_mask)); @@ -647,6 +649,49 @@ static int __init parse_dt_topology(void) } #endif +/* + * cpu cache topology table + */ +#define MAX_CACHE_LEVEL 7 +staic struct device_node *cache_topology[NR_CPUS][MAX_CACHE_LEVEL]; + +void topology_parse_cpu_caches(struct device_node *cpu_node, int cpu) +{ + struct device_node *node_cache = cpu_node; + int level = 0; + + while (level < MAX_CACHE_LEVEL) { + node_cache = of_parse_phandle(node_cache, "next-level-cache", 0); + if (!node_cache) + break; + + cache_topology[cpu][level++] = node_cache; + } +} + +/* + * find the maximum level shared cache under giving mask + */ +void find_max_sub_sc(const struct cpumask *giving_mask, int cpu, + struct cpumask *sc_mask) +{ + int cache_level, cpu_id; + + for (cache_level = MAX_CACHE_LEVEL - 1; cache_level >= 0; cache_level--) { + if (!cache_topology[cpu][cache_level]) + continue; + + cpumask_clear(sc_mask); + for (cpu_id = 0; cpu_id < NR_CPUS; cpu_id++) { + if (cache_topology[cpu][cache_level] == cache_topology[cpu_id][cache_level]) + cpumask_set_cpu(cpu_id, sc_mask); + } + + if (cpumask_subset(sc_mask, giving_mask)) + break; + } +} + /* * cpu topology table */ diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h index 58cbe18d825c..c6ed727e453c 100644 --- a/include/linux/arch_topology.h +++ b/include/linux/arch_topology.h @@ -93,6 +93,9 @@ void update_siblings_masks(unsigned int cpu); void remove_cpu_topology(unsigned int cpuid); void reset_cpu_topology(void); int parse_acpi_topology(void); +void topology_parse_cpu_caches(struct device_node *cpu_node, int cpu); +void find_max_sub_sc(const struct cpumask *giving_mask, int cpu, + struct cpumask *sc_mask); #endif #endif /* _LINUX_ARCH_TOPOLOGY_H_ */ From patchwork Thu Apr 21 14:55:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?546L5pOO?= X-Patchwork-Id: 12821803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07D7FC433F5 for ; Thu, 21 Apr 2022 14:57:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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Thu, 21 Apr 2022 14:56:28 +0000 From: Qing Wang To: Catalin Marinas , Will Deacon , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Wang Qing Subject: [PATCH 2/2] arm64: Add complex scheduler level for arm64 Date: Thu, 21 Apr 2022 07:55:58 -0700 Message-Id: <1650552960-60165-3-git-send-email-wangqing@vivo.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1650552960-60165-1-git-send-email-wangqing@vivo.com> References: <1650552960-60165-1-git-send-email-wangqing@vivo.com> X-ClientProxiedBy: TY2PR02CA0005.apcprd02.prod.outlook.com (2603:1096:404:56::17) To SL2PR06MB3082.apcprd06.prod.outlook.com (2603:1096:100:37::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d957549a-c692-408a-147f-08da23a71cf5 X-MS-TrafficTypeDiagnostic: KL1PR0601MB4308:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5BGc4b8V9WEQCIIuZsR4CWKN9HNBd6EneIznDpSEEKsVKE7T4YOsvSARIIkeCO1tFxI+JXvllZnzB0FdyNnAKUVS1UZj8Wti8moFkaY83JvmTbiaOCWKLUDe3IXOh3ah/YZk11U08FguLgfyuInJXaODAEZ+Q31E4x3SD8lS4rfZ2j2TyS9KnBiLnrf7MJqXHhhZfdW9RtjbvOGn8597qCMNEkiwkej3GORVR2w7ef7lvyuTQ5csNLjrrdi9m0SThhwl96MnZebsLEmqLM+TBVvXKaec02ghoLN5K0B5rsPd2Cm3L97pLYKC1KZ5eHc7Tw/RmkwpTwmY7f+J6BkAii87kvySCQsR5tVZw3Nnsv4YPt2r4YlNUWrDqJIL5gPOFHFMy76cKIdITYKvQkVDqqAKz66WyJUFvsoVTpua1M07b0NZk141kO1wIqA4D8dChBGeYoy21ZdcxA8gXSLXxHStYYRlBXqrqVGnazNUNgt8S6PjYTiBGgbdWTV+8oPreaVImPN32Wilk8Px72EJE2vOsCUJhlsg8bkENBfUzF8+SpYF/bfeWLli9jdejYORcrt3Vf+ab2zebe2v23OLqXUrGPfzArlXxyq/qwwZ+VCXXLgWo4KrWVPDsc88s/rZBZIj5Re74yE8MsUPmgUHhW9H+HOL6dv5yuIrIsR6G0rrIQFDwiujFWmVzKVXrHbA7jaEIxkfm4b7dJT7W3emlQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Sharing some logic between the cores can make a complex area efficient. This patch adds complex level for complexs and automatically enables the load balance among complexs. It will directly benefit a lot of workload which loves more resources such as memory bandwidth, caches. Testing has been done in qcom sm8450 with Stream benchmark: 8threads stream (2 little cores * 2(complex) + 3 middle cores + 1 big core) stream stream w/o patch w/ patch MB/sec copy 37579.2 ( 0.00%) 39127.3 ( 4.12%) MB/sec scale 38261.1 ( 0.00%) 39195.4 ( 2.44%) MB/sec add 39497.0 ( 0.00%) 41101.5 ( 4.06%) MB/sec triad 39885.6 ( 0.00%) 40772.7 ( 2.22%) Signed-off-by: Wang Qing --- arch/arm64/Kconfig | 13 +++++++++++ arch/arm64/kernel/smp.c | 48 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index edbe035cb0e3..4063de8c6153 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1207,6 +1207,19 @@ config SCHED_CLUSTER by sharing mid-level caches, last-level cache tags or internal busses. +config SCHED_COMPLEX + bool "Complex scheduler support" + help + DSU supports blocks that are called complexes which contain up to + two cores of the same type and some shared logic. Sharing some logic + between the cores can make a complex area efficient. + + Complex also can be considered as a shared cache group smaller + than cluster. + + Complex scheduler support improves the CPU scheduler's decision + making when dealing with machines that have complexs of CPUs. + config SCHED_SMT bool "SMT scheduler support" help diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 3b46041f2b97..526765112146 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,10 @@ DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); EXPORT_PER_CPU_SYMBOL(cpu_number); +#ifdef SCHED_COMPLEX +DEFINE_PER_CPU_READ_MOSTLY(cpumask_t, cpu_complex_map); +#endif + /* * as from 2.5, kernels no longer have an init_tasks structure * so we need some other way of telling a new secondary core @@ -715,6 +720,47 @@ void __init smp_init_cpus(void) } } +#ifdef SCHED_COMPLEX +static int arm64_complex_flags(void) +{ + return SD_SHARE_PKG_RESOURCES; +} + +const struct cpumask *arm64_complex_mask(int cpu) +{ + const struct cpumask *core_mask = cpu_cpu_mask(cpu); + + /* Find the smaller shared cache level than clustergroup and coregroup*/ +#ifdef CONFIG_SCHED_MC + core_mask = cpu_coregroup_mask(cpu); +#endif +#ifdef CONFIG_SCHED_CLUSTER + core_mask = cpu_clustergroup_mask(cpu); +#endif + + find_max_sub_sc(core_mask, cpu, &per_cpu(cpu_complex_map, cpu)); + + return &per_cpu(cpu_complex_map, cpu); +} +#endif + +static struct sched_domain_topology_level arm64_topology[] = { +#ifdef CONFIG_SCHED_SMT + { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, +#endif +#ifdef CONFIG_SCHED_COMPLEX + { arm64_complex_mask, arm64_complex_flags, SD_INIT_NAME(CPL) }, +#endif +#ifdef CONFIG_SCHED_CLUSTER + { cpu_clustergroup_mask, cpu_cluster_flags, SD_INIT_NAME(CLS) }, +#endif +#ifdef CONFIG_SCHED_MC + { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, +#endif + { cpu_cpu_mask, SD_INIT_NAME(DIE) }, + { NULL, }, +}; + void __init smp_prepare_cpus(unsigned int max_cpus) { const struct cpu_operations *ops; @@ -723,9 +769,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) unsigned int this_cpu; init_cpu_topology(); - this_cpu = smp_processor_id(); store_cpu_topology(this_cpu); + set_sched_topology(arm64_topology); numa_store_cpu_info(this_cpu); numa_add_cpu(this_cpu);