From patchwork Fri Apr 22 18:30:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 12824098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6724EC433EF for ; Fri, 22 Apr 2022 22:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231805AbiDVWHL (ORCPT ); Fri, 22 Apr 2022 18:07:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231637AbiDVWHE (ORCPT ); Fri, 22 Apr 2022 18:07:04 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DE1F31DDC; Fri, 22 Apr 2022 13:52:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650660721; bh=nH5nbmzHe/xRwz0pWDdjzn30b813GPDvATKACfo4I6g=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=eyIq38Ti8Xyoy7E0KkA29w0DkaRlW8dP8h5wyY9BNqYn3J9bSSzUP+PiTaibG9SWW ub/Uupa1SinGBG1AycTDetvFx9E3NVW1btY5UCZ0+WtMgR2lprvv76u7jqnf9PXAlo APJT4bkv9v2gXLwuJ7IC7ZKkhZzyEIufDZb39CVI= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MGQnF-1nh6473Djx-00GnuC; Fri, 22 Apr 2022 20:31:46 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 1/7] dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks Date: Fri, 22 Apr 2022 20:30:06 +0200 Message-Id: <20220422183012.444674-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:lnBh/Tpvgmu7+wHhf+H5KmdyA2JGqflwIdExxJyori80ywRZSGg flOvQpXx/6FTotPushCAlRjkrTtc6+4Al0ktSv+PUZ0hpSYy2O5QKr8ZpiSt5c26UcjQFfW MAWFL4Hz8F9vQWjXrGC1jMgB2bGBiqgY4p203hrVJHH/jNtRhzgk4N0vl6J4PqBB2kLE79S VYINyKnXBIFnjHKOVSF+g== X-UI-Out-Filterresults: notjunk:1;V03:K0:GH6IMDgDjVk=:zwNWdBjXT58bbmqMOK1ZyH eKVkZYuRPsrGXFJR11x2HGexmFcrG5npjb3hw1G81xS9+G68DLMvyuSJV4bJk3zuLcYVJqa1M JWCQfcfDk5UKkQ1rlenE34gpA7hztwRAbHJ3iV6js3KyzuDVsz7Xo8zK/L+L4Yi0F085xgL+o PCIGn+niJIKUgnUVAwQKaQOF7iMw9eTwkXwpmnLbOjTqD5eJ5aG1UDFcRwINNWUvcvI5O4cda FQUNnGTdL7ujQZfXVbbM0ZBbIDcDFeIdagpMtfYnq0h+zFg8PJZCOlhXMwVdT6ULcVnprY1UJ n9mFbqmetOirWzDWemHEOkTuSHZQn2h6rEShW8mtcEW/nVfKJPcy4FF5BtIidgV33NM6mm8A+ HWaHmQUaszJdqIepItfxN51b9DovnEQJd8AU8r4F2m9W8TQYAMToGJq0RoC/wG+Qi+iq0q/8E 7L+7jniWOs5WQJj1+KSh+kuXBI8o60eik0JBj2P/bYnPGx6z7TzbU3u5mD1m0eknZ7YbQKvRX s6Qq7qwu3VdY3zwYawvsipVz9/hbIhNvnDjTHZIKK9021lvFY89Y3dXQ25/yJzSUyP/h6vqAC mLWNBcsefhfoCOf9EMY7Y1iHQRXaNOLMcDomv1Gyb2d+IzEBcAXNewrk7kZA4RPMlnF+ydcF0 uH9kNHGGrDq+QvsnKHjBZWQxvezef3FAaaap6IRxvIKEeoDaNWDkMUCY/5bQPd5gF45Q9Nxtq bTPPVTzxFfMC5IkLZt3dGT+Vk5g6/FZ6r2Md5bslCrwrI9K6x5mQVeWdZVfnfEaGf/iLPNVuq FHTow+h+Ja7faVEPIx8RBs0/dP7YTJttdutvqRV1pNbPZp2FRYYC8g4Yv11aWbFNKS8X82J/F AbdPHOZSjmZ2I6JKMpkNbmZ8BIU3SisXUpxy2UqgVlrc3oVBR+87o8v+DQAX2Fv2QenHhXDu3 QdDCeqGp3hOCaon8nS6Fx4843UHajRwjuzgvPIqr5Atg1Hgt07zD4FqllQMD+y/9T0Rmf/6Y0 k5EC7jZo/XUQXoyyEyQ+Mpit8AG9G6ArfHdlYaDKkfSa5ZtaKLXdUEMTQY/i3vNI1kTulkD9T DSKFokWsM0Uosw= Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 0cbc26a721514..023c999113c38 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -23,7 +23,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Fri Apr 22 18:30:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 12824258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B68BC433EF for ; Fri, 22 Apr 2022 22:40:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233777AbiDVWn2 (ORCPT ); Fri, 22 Apr 2022 18:43:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234301AbiDVWnF (ORCPT ); Fri, 22 Apr 2022 18:43:05 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.15.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F1661773D8; Fri, 22 Apr 2022 14:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650663731; bh=XAbU/WwnBQTi9/OidcyFLjRJfgJl6FaI1cL4Ta59NpE=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=F2yNof3X8y8hvi/Y8+FiTX2CnlA5T8zdkgbIAfDQXmoXufJ1VUZ41pI81mlXiMINO 4flm5ao9FuutFjMtZIDCH5n37U0YdMUGXRuI44iyVJFpJjwgQMTU3WlkAmf1ecp2mV w9OV7B5Bl8yNmQaJmg3FrKvwvt+Xi3dV6OGkjmGo= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MxlzI-1o6V013bxO-00zIaz; Fri, 22 Apr 2022 20:31:47 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 2/7] clocksource: timer-npcm7xx: Enable timer 1 clock before use Date: Fri, 22 Apr 2022 20:30:07 +0200 Message-Id: <20220422183012.444674-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:uovlBSQszsD4TcZ6IjORpDv2zAitS8WCPXKi91TdybsXvyz7lqO rC2FC41F/kJUCpFHd1VviHlqQLLBrFbdETf+eE8nbVimOfnWkBZ30HFJmtlAYF1Jwirim+1 uMWQPfc4mPu19lplwt6TaEE58ze9BYNz5EI1+XTE1tlzCw3t9XOIahvNn5e/tYf/l/wShmM vpo+JqSHVFco1wj+MDB2Q== X-UI-Out-Filterresults: notjunk:1;V03:K0:g0eDA97AGZw=:Ng7MfKtb6I8godEPVk0G2X seOnAGfWoJs+65+HIlee2xyPeWz5f0C50jvK+jtsUd0ANNNqPIYae7byOZJzrhw/P55iv2A2F P1Hr9je1/eAaBX1VPuCOTBA1kzRjTRs72oX2yTHFZYzEl2VFPkCCGuvkcqtfdcjF9sD/PyVl6 VvoxtkiaRH1IoBCthl603M32eWHgl3urURApkzqdAtLde37y6fFrqEdxaDtgRZsjrP64FxZ5M fCepuoUdV1cuZgByc3FjkUXUkRVMjVgz38GbOtizIt7txRL7aaw9bFo7I/xNNYgulEK97c6tT 11B13KqDQwIQmsSRuaVXMUkgcL2rY/W+gjpy5Dy8GQRhpkqbirxyCGMJMWn0Cs1lvOfXrznoX f0RhFAE2ak78U9ga48bwQNGQB9tPzDzj74AC18tLfB5DHqZgHUBpyyef+ru96vlSVbDtErzkb cuYvmDj7KLnj2QcaAEZKIQcLw8dg9/227oGn/S/ReCCUBYEh9G3fFLWVxKx5Os4wAsu3AKdt2 HGnX3Md10TYRJ/pujlic6Fvq2nRjbaY2kdA/u3WGTT3489sd3vUcfXN2Uy9A0r1FJCbmPan+a P0cfQNBhbmTzNUzR40OjhhK45J50yU5ZsWV0efr8kNJjM9ITixrcrIviNHwRaWCUTBPJuCReX Yz3oZ/O5Pt/ujDvI0qRz58POYsPx1rH12opNEPq+txF1b7ufi116464AFhaVHsv/3FpCmw1jf Y3tU5O9FkcXEpfWuA1KqGT/dXKNo0+IHzFfCOWtY4CnRHKA9RMaXfbghDs8j6hZcDzvsahLFD 7PM4V244nG7aLR5akwg+rkGBxz9NcKCyt0+OyOqz/fSAj/hsA5IYqm9INJTQNBm9waKiDPsmn wvxXdyKCDt8Y4V+d51d1L4qQLPjUeSiibWIiYEMK2RoLqr6Vfk0hmXzCldxIhNISVwUhYRKEg 9euzmV1wP09AFhbQTGmvGoozwj4u+nPxezt28YhzIDvcp/mnFifVrWaiHAcll7tQgIS7aKgyQ D3PvycgMCJDuUa3fejgAUbFyqOxDH9nYkKw6GlvpbbP+PziKq4+xNS3NhGbo+3gSQt7I1GaAk PxEk+FY3lJ//Mw= Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org In the WPCM450 SoC, the clocks for each timer can be gated individually. To prevent the timer 1 clock from being gated, enable it explicitly. Signed-off-by: Jonathan Neuschäfer --- drivers/clocksource/timer-npcm7xx.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c index a00520cbb660a..974269b6b0c36 100644 --- a/drivers/clocksource/timer-npcm7xx.c +++ b/drivers/clocksource/timer-npcm7xx.c @@ -188,17 +188,29 @@ static void __init npcm7xx_clocksource_init(void) static int __init npcm7xx_timer_init(struct device_node *np) { + struct clk *clk; int ret; ret = timer_of_init(np, &npcm7xx_to); - if (ret) + if (ret) { + pr_warn("timer_of_init failed: %d\n", ret); return ret; + } /* Clock input is divided by PRESCALE + 1 before it is fed */ /* to the counter */ npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate / (NPCM7XX_Tx_MIN_PRESCALE + 1); + /* Enable the clock for timer1, if it exists */ + clk = of_clk_get(np, 1); + if (clk) { + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + else + pr_warn("Failed to get clock for timer1: %pe", clk); + } + npcm7xx_clocksource_init(); npcm7xx_clockevents_init(); From patchwork Fri Apr 22 18:30:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 12824259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68EF3C433FE for ; Fri, 22 Apr 2022 22:40:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233827AbiDVWno (ORCPT ); Fri, 22 Apr 2022 18:43:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233818AbiDVWna (ORCPT ); Fri, 22 Apr 2022 18:43:30 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48F4B1765EC; Fri, 22 Apr 2022 14:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650663703; bh=8RE6J/48SaezMLYOSRQdb+dos/63a0S80cGWNaaY89M=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=bXqN0HxN/QQTsPVdZP4VwcyzjGY8iA92O8TmXTtJqtf628Jb9RnNaDSWWlVJSamfu LVrCT6xfdBwD0xHIJEtlOP+Jv7Ydwi4wxzEv/Ky+/7G3hfhkjTD4AnuF7vo6+Y4nSz pw514YWPfkzdRJHC9a/hcVUqM5zCjTCqXE6GfHq8= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MaJ3t-1nNDlI3YKj-00WIp0; Fri, 22 Apr 2022 20:31:49 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 3/7] watchdog: npcm: Enable clock if provided Date: Fri, 22 Apr 2022 20:30:08 +0200 Message-Id: <20220422183012.444674-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:DzdlIpOpxoHVmzoWSwK/nL5QieYQdzPf0cfyielup2/bHsKDAwQ N2kbPBEm068bJ2qlsUpy1PuMDBxL0Al4q+6mC29jVCwWJ/ZDGDodyr0gOx42IbCkPI7CSfx IoV+Hxjssgj5OQwTO2pN9A2e91iagZFyoIx2I3C0VnPPyceNuz2gFz1TMWf3aXtkNj8+Rde HcSt22thU4XWdRXPBq43A== X-UI-Out-Filterresults: notjunk:1;V03:K0:CBOfWkKmFVM=:FRw7nNLWbQ3bNBPv90sVik qODJZKuinuG5QGsuYOs/jvHQDVAwkxAhbrVKGyHAfejM02F1o6pXo6Y53EgqoqL+f20r/hEBO VHTj8XfmXgX0C1S8IleVp2m2obNr9mee52dRf6O88DoMm2X7FBtOo0Pbcjimat1k92swzUkZX nMRDluyneiJgxhQ2oHIpStiY8+Y8+T0JA3Hp9QNpwkrlilL9Eb1k2H6GvOslXWCtsa0Ywha6E oeBd2tfshMcuis970o4dXC6i1DSaLkmVy7b4NfUqok0BRcKmBZ4G1dLqHITq3EnmlKT4hKcOe xuSfm2VI5SKq6uJuWVMNXymlkbfSCf85jtPqgCgpyJcYZ8nGGBfcwzscooefR9lXFD3X4ia/t IXdiwBDm0SsHb8N7E1LLRHyQb8RxgfhwsRAinHUVfskP/AtdwOO2/cUqE9JdbEHVz3JioBkul Vu9x2vN/THEL2RPnVTgm/ZhxBtuI7kcRsL7BAmeL0fstcrpTqhSHrQa3YdPts2oJM7YHaah0O vqCYCffcjZtKuJvTcAlqOEhRBXvMSAdx9Ls/THjGaLt8uvKCAVk6tnJaILFfYmk52RxJUW26U sZ2hopESgei/M5uelSeRHdEx2nxxed56Mo5JNT0EdX3HogPkRJ+64+1ZmfbcjNBm3TTCtJ1pk zwSCtgn0dhhD4GEKUNiv1ruTHBAEIaS3JJYdhTHb85UYpg/CKck+bLvS1FZaZzHzEWnL78sGp XamLpO/CUQMLD4lUf71TWCNinLhqAqxRuUa2evW3aiXBlMhIuKmSXcsceXDhUzHCdCWmDQYJs 5Z8i1m+r+M0wPWu8yaRSyJ2G25MzlyuWozFVNwAVgOs7KR37f+ElSo9McLk7Z0rlbIJYB4qRh lK6tFnJS9P/S6q2p9q1vDnx2P2qwU7ijdI7Kb3ibOf5YFr6pc6EwTm6inHkK5RxgxOPfyybaP M78QedtmEKiLOJQdYwr58JVKfKkuu1kC+xgjXbjq6ZJRNg/TeMfo/O8i9o5EJ1ckbkb74RYaO RElyBVxbk3HOApjbdJHAVPnB28rD6nTZDNl5mmiFTCAFu/0R/1Y4G+teLqb8r0FJWOIoJQFoh CvWx+XXBm1Xaw0= Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral clocks are individually gated and ungated. Therefore, the watchdog driver must be able to ungate the watchdog clock. Signed-off-by: Jonathan Neuschäfer --- drivers/watchdog/npcm_wdt.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.35.1 diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index 28a24caa2627c..6d27f0e16188e 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -3,6 +3,7 @@ // Copyright (c) 2018 IBM Corp. #include +#include #include #include #include @@ -180,6 +181,7 @@ static int npcm_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct npcm_wdt *wdt; + struct clk *clk; int irq; int ret; @@ -191,6 +193,13 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); + clk = devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + if (clk) + clk_prepare_enable(clk); + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; From patchwork Fri Apr 22 18:30:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 12824097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2806CC4167D for ; Fri, 22 Apr 2022 22:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231584AbiDVWG6 (ORCPT ); Fri, 22 Apr 2022 18:06:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231448AbiDVWGt (ORCPT ); Fri, 22 Apr 2022 18:06:49 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45848208225; Fri, 22 Apr 2022 13:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650660663; bh=Cymelfm0dfRc/xEvMKwoybWU1kDdiYfz3b2fHT5KUdI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=HwCRogHH7SWrMLArbABWdkNz9fT6p7rcGoBcLx+u0005kKgylL4dxLQGgWTo1Iacv dRBl4e6l4+Wf4aFTLFHnE0rBn2/WY6x4yukN5yrbSoGO6sI05HEbW7VuiVmC1TBKIX E4htHAAfiFIpafJYnSc4LXiIirwpyR4fE0cwIzNc= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MaJ3t-1nNDlX1HTp-00WIyP; Fri, 22 Apr 2022 20:31:54 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 4/7] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 22 Apr 2022 20:30:09 +0200 Message-Id: <20220422183012.444674-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:vVjrm1cK8AXlnpuGK08RSnmA6OQJ45C2q8UnLt+ebe9CliGV0GN Ti2LnJqA3CI0GUJriFLVzIgrC/GGhXhNMKKv5axP3W5W5BC44FV5INXkhXh9NVzreAFDXxf hYXaumjri/r402YVm6eqffixmakJCzbvAgc+taVHDAyxrjDdf0CQZBv5XXpMOXqvZrkmJI7 35zbHFwBeKYBTxHW9dkrg== X-UI-Out-Filterresults: notjunk:1;V03:K0:AQbNhO89mNA=:MLaOVMQJPve9D6gl13SY/6 x8dcmv0TrOwv0Dt9s/OHQeDH+TS4WpahFEojBRnVKjA0QTtUw9/5BS1Q+9M8eB+kl2Sjpwr91 WfjgcDxVlCnoqeH8gdoSLC5spPNpj0y+6rlPXXRgd6aXGPCkWA2bxhs3H9UrGBEKJ3BZ02k6f t0fIT6LypHwcmRM/wU/N3mTMXDAGQ/KKmp8ndmWYnn2a4khJTds02H4xTy/3ELG6FVo2OaAI2 DPMoqgGiRuURMcpM3zAAmbG6LslC0SZSikMZQeLBWxvdLG5cMWBKl9X82oaaeKvgJJd2/3qjs HeegIG4YCVpyVZ0B1SAAYWSE1OHspveo+GFscRINf5Mm5Y1w+INy6Sr8r8syauCif31k2ekI9 8YUn1zACpgCsrfLfiIn6xVI+rXKtuxEyZdgUufWw+mSIO74TBzcap3W2hH5CVEU4D5duvcQOW fI2mqGEvWAzfAvy+Mdf/Yyl+8NvQ6jLI51cYWGVSHwdkARttm2IOR7QZg1CQRYXQSmVEFPdDh wDsCYwMQCrYW77UTgwE/acBO0rqBSJpf4NuY0QOKb1sjV5v+V3uM2k5Votzjcy8n2U5WMtHNf H/kJhGOCDr0y8Ab8k9HfW6dIWxBhUYqcfudxkAQUlrzPCdzT6oPXrK7YeXhTKON67TbUoKg3f u35H//9VxDbAzjxbESXvZzSWdDtp3o2excOpCWvEqFfXR8OHIudXDSgTTp5ViIevS0qbf8r1Z Q638FC4SAjmNt+Ulv8gWs/xPCmsiFpWKrOWtx8bXgWbWlM3LiBRza3kSAXy5jA/nPElUIe43G RTC3mgFDpwfOF2inXuLNEIhFw1FEe1+9nq3LycJFFrutTjSOiuOlpc1KWCl0QixV11MgkdZKs wJEOHUHFPnU1VhOkKE1bJH2g9fPfyV/xa+2zW2U1UAnHfOwPeQf9CsPeKHcrO+lNtXB58mGyc NqZ2XX7y72Twtb0TtY0P8/71imq+/JAUlwhzh4a2EWxlNEEx7jPLKL/cXtGAATPBI8gjVzszw xCbS8HIhZVYaGHjKRI0/g0XvN1iD2AaO8pOj1iOu8SQjOQNC0TdEJzR9IFHZRZwAtu/zH5K4m SCxdsoE7MH07PM= Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 74 +++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..0fffa8a68dee4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller binding + +maintainers: + - Jonathan Neuschäfer + +description: + This binding describes the clock controller of the Nuvoton WPCM450 SoC, which + supplies clocks and resets to the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: refclk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "refclk"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "refclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + serial@b8000000 { + compatible = "nuvoton,wpcm450-uart"; + reg = <0xb8000000 0x20>; + reg-shift = <2>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk WPCM450_CLK_UART0>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ From patchwork Fri Apr 22 18:30:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 12824217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 514E1C43219 for ; Fri, 22 Apr 2022 22:36:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233816AbiDVWjN (ORCPT ); Fri, 22 Apr 2022 18:39:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234437AbiDVWiR (ORCPT ); Fri, 22 Apr 2022 18:38:17 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E67C200389; Fri, 22 Apr 2022 14:30:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650663022; bh=BHUkq4qIz1dh922+/iqR/+zEXRIaC4ZyZF4Bphn8Po8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=EXay7kgGE8SkMAk7JaTrpqsmjmE+KTqTL3U60OahfcTP4a0uhZGt1TALutDYVF3im M/dCpgzDLEepZkFvF89gCdMzhB7ac4NIR/nuWleWMud/8uWT2N1OdDKDdZ24UdzTND Agi3x+W+yvHXOI3DRqZbvc1rgIezKKwRa4KtuWPs= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N8ofO-1nvSO519eg-015ujL; Fri, 22 Apr 2022 20:31:55 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 5/7] ARM: dts: wpcm450: Add clock controller node Date: Fri, 22 Apr 2022 20:30:10 +0200 Message-Id: <20220422183012.444674-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:Fag6c+9a1Pz3T5xG3Pe4SmIRM1zshVKs/bhtGtFRhEqmEKmvImL mQiew5bwtAn5jmH7DaPyUusvR9/woaryKVpQFAXUKgw39r3F9k9/a1u2LQItUrXdsy7diry CBT1J59AfeqO/3Z6yii0UgOL51/2BFCdmCC74iM+zjFRl7g/SRd0Lu5Q5I0YJ4tANpkLGDo PYSdA+hdkEp96fsM9/7sw== X-UI-Out-Filterresults: notjunk:1;V03:K0:IHgVYjueDIk=:s19Olf0VBPcmGPERNqaAVP TIOWAFRCJ8h1zX3LmbH8ZStBHDP6P9A5eQhP0ofSiugsP6jIVRCLO8XSlS6TkrTZNKvhaLg+Y l3o2Uw5FF+BiEH4ITCaIkibSAAw3yYvsmBeEVhI968R+qU+j9jemDR8uiXPckM6NFLlFG3MAA //3Vkn/yzDI+S/DuzZwc4m/fSRP+2u+UhapM3X/x049NPxHSkiKu7Fh0mueR1t73aFB3MqSeU GJMIl3QD9eYoPieeluQDBN3OK/0o5YTLLeJyOrFJLmOGPVANCkGgqyuiY8kxs0yUAo3CYH310 YISle7JZrIyFsKumD7yMJwq1DCcT9+BKojeTsB1kLGIfNIrhpEj9bJAEYZrMi4yFhfIr+MuuI oGC7OW38CccejsUeblq3l6NtVKZZGEAk3UXxla3VXvcEOrzM816Y/3YHc18+YQFLVwfym/Rs6 HpfcVHsbxMIRnekokDxudI2DP2FZbSsMA7xtr7SkkFrZowFAwaTQ8p2TOBmk0zC/iq5KbO5Y2 B91g/xGxfwmhLJJlfHpUjcoIij9CJrmWE0jOPVVktEgdGEoXFbA1ac67XnVeR/SrX/4uFZrob M199YNDpY5+S2cDOf0LRmhL6spD/JnMzvcfaEu2Sg3Fp8Fa+uul9rFFDhAeaNT/23jcmtjwMW Zo1zEe9o8swvO7N3pQTF1PZ2R6K4gxjYouhqdV7DJLsyauGhM7Mq+wdRH8rTk610Aso3QbTiQ HwSYs628upNHfP0XUwISxTcddajIdD53mgG8fgFZBKzt21QSfEDTI9swvdN2Oz4WWaElbqF6E L9fbql54Lgwr8/NXZiYsyHbZDTRoY4Bv1c7TE7ZvHo1RSPL5/Pfp1Y25wggRhQ8r+J3i26fe9 Vv+YrLmcvWdfZrrSlui3Z1+SOYosJuorgnTGoBDmJLf2J6TVA8hXRNBVx7L0dWxh0yyGqKvhD QDvvT0otLfKlDfcTjrwYS9Nm73804oL+q7n4v+JhNmqdDbG2O1rdGJj+qDuyTokLdmwVCoi9S RSWbkjlIiwj7PvZR83cBPpgFFVTjIFdAVO36ZXoSfQbHbtQJeMDAM+IwJ/uSrTbWysAcEpG4d J+80VCwdWTBYn4= Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neuschäfer --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 1c63ab14c4383..62d70fda7b520 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -39,6 +39,14 @@ clk24m: clock-24mhz { #clock-cells = <0>; }; + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "refclk"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -51,6 +59,15 @@ gcr: syscon@b0000000 { reg = <0xb0000000 0x200>; }; + clk: clock-controller@b0000200 { + compatible = "nuvoton,wpcm450-clk"; + reg = <0xb0000200 0x100>; + clocks = <&refclk>; + clock-names = "refclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From patchwork Fri Apr 22 18:30:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 12824096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D797C4167B for ; Fri, 22 Apr 2022 22:04:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231479AbiDVWG5 (ORCPT ); Fri, 22 Apr 2022 18:06:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231588AbiDVWGs (ORCPT ); Fri, 22 Apr 2022 18:06:48 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 783D5206C03; Fri, 22 Apr 2022 13:51:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650660659; bh=Z7teJIYqUSq12c5uTIxh9gTwy/vvO4uUbKqt8v51mdE=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=OvWLtOOBjfujeEkSJis3vOOdwDTmnKoNv2hn1HSvvaH9OQBGSdC4nStXSjLqOTEov b+/R2tEEwKWiuDhEUOwjOnh8wC37LzF1qY//4TLt8Y+3rhq3SplQLpsUJ7NTSe0ino xuoQqdLf3yTnn3+JAeb6zBMHMsbGnh/2UVKch/Hs= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MBUm7-1ncANu1Qv1-00Cxwe; Fri, 22 Apr 2022 20:31:57 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 6/7] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Date: Fri, 22 Apr 2022 20:30:11 +0200 Message-Id: <20220422183012.444674-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:gaCx0O9WDw+rwOFW3kkbLxaWxszoxkpE9hactbEFpdSE8StJcBX NsHfbRfFTuk6t2QdKLJXiFocCpwubMjU/Hfmb/gVwljXLT+BVvvVan3Snsh4sB7B0ZOf5Z6 RmVpMVnQ/aPMoGqQqb4yhNelNZTqSt88FZjFUuGMFq3ghJmbYFBr55CPSoOdSB1xh3+z+5p q528vyuc6nBZ3/yyf3mQw== X-UI-Out-Filterresults: notjunk:1;V03:K0:roVyZI3Q6bc=:JHaqzL3zaUv4ZKeLDNSFop /tX4cz6NQ//MHcpIODoNdVGttiHfINLZzgZERabeiEWzHtzel+Vv65h+6qjICMcH2pSYfB5sx iaScmhLdYKJ0AsJPrYFisc6jlKtENh8OBVw1yKlJD/lBMyU8JcoTCHwUXcz9BA3E6sJu2neZl XL6lYei50oJDqLf8WNCruMqqgT1vDLQ4WULtaN7D6a32DMIGOHFAXnTMbDNbd3zrmUDW1aJAf qmUOCL82JtmBJGKaRCvB5SNDCpD9Y1nsZbdBavzZbV3s90VuWWsLhgKgc7XDZjZr36QJvnNWD BQU37Ky6MpaRq9dkpmASTrseBRNdpxyGbsFqivlNhrmblJ2Ep1/zkhpcl71yFM0yRbvA5s2Oo MTFO8mzI/cHM1JnGxVljG1Fe5EvFLiJ1s1udQkq0+OQihZP39veRiA1hfuJ7ciUacSuFey2tx blfbUvHKaPQ108DfztVXcNUBNhOmr69GDWhjm315KaXUr4fu4qj3/3pdWCA8h2P4eCl4Z7c8c UjdjYTA1GFmIrz0pbqNnxikgsSAJVuPiblhDjs3uOfvCeV/w1kEBz+Z0CprUHNxeQwWy5P1lr L7R8N3DG70nzrDLVDjjLwElLJt5fH0cYw2sbICLwDlvJVhmQcYDKuEHmrYcCKZm/J+RNNZF38 YbX4iP/ixzznVzJU9Msm/8g/3KR7dzJlp6FQzffALpG2rkCU3fY8Ukppra7/69TbcqPO4oFiM 53+TM/vbPMrtXkiwAmJQ0ZFmj3e+o8AKstSHaOZk7nnrvi2Za/zcopoSHI58fxsBSbGtkCuAc 0XFIV4tJh9rUYguVX69Y3bF63coASzxlnzea5XvLj+SzwW0SAZQY1gwxUm+WxRpK/fBViY5Qt V3l/Lh1qQXZIxq8zmpDKbY3qIUZJbAWdM3CtdbbIJH/UcqgzczT0W4aaD11ziV4AfUkXWd0+I hspe8niDNccnIIxSiPylb5GPIAeTkkHWzQzKFXZM2QM80d461JjFgYFkAv1/0BjXJnHQ8scRe qa4upSZXRRk7+OO4jNylNOpIxe629erTiehJ5HR1kbBT63X4qBNtcPVHpYYGUluAX6S5j71jP DKVY4iW+7O4voI= Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neuschäfer --- drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 378 ++++++++++++++++++++++++++++++++++++++ drivers/reset/Kconfig | 2 +- 3 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/clk-wpcm450.c -- 2.35.1 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2bd5ffd595bf3..07edb0f4ba8ba 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o +obj-$(CONFIG_ARCH_WPCM450) += clk-wpcm450.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name diff --git a/drivers/clk/clk-wpcm450.c b/drivers/clk/clk-wpcm450.c new file mode 100644 index 0000000000000..3b62b5961d5f0 --- /dev/null +++ b/drivers/clk/clk-wpcm450.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2022 Jonathan Neuschäfer + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero", __func__); + return 0; + } + + pllcon = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate = (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + pllcon |= PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops = { + .recalc_rate = wpcm450_clk_pll_recalc_rate, + .is_enabled = wpcm450_clk_pll_is_enabled, + .disable = wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &wpcm450_clk_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + ret = clk_hw_register(NULL, &pll->hw); + if (ret) { + kfree(pll); + hw = ERR_PTR(ret); + } + + return &pll->hw; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + const char *parent_name; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] = { + { "pll0", "refclk", REG_PLLCON0, 0 }, + { "pll1", "refclk", REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + const char *const *parent_names; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + int index; + unsigned long flags; +}; + +static const u32 parent_table[] = { 0, 1, 2 }; +static const char *const default_parents[] = { "pll0", "pll1", "refclk" }; +static const char *const huart_parents[] = { "refclk", "refdiv2" }; + +static const struct wpcm450_clksel_data clksel_data[] = { + { "cpusel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, -1, CLK_IS_CRITICAL }, + { "clkout", default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, -1, 0 }, + { "usbphy", default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, -1, 0 }, + { "uartsel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, WPCM450_CLK_USBPHY, 0 }, + { "huartsel", huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, -1, 0 }, +}; + +static const struct clk_div_table div_default[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 4, }, + { .val = 3, .div = 8, }, + { } +}; + +static const struct clk_div_table div_ahb[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { } +}; + +static const struct clk_div_table div_fixed2[] = { + { .val = 0, .div = 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + const char *parent_name; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] = { + { "refdiv2", "refclk", 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] = { + { "cpu", "cpusel", 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", "refclk", CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "apb", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "ahb", "cpu", CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "uart", "uartsel", 0, NULL, 16, 4, 0 }, + { "ahb3", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + const char *parent_name; + int bitnum; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] = { + { "fiu", "ahb3", WPCM450_CLK_FIU, 0 }, + { "xbus", "ahb3", WPCM450_CLK_XBUS, 0 }, + { "kcs", "apb", WPCM450_CLK_KCS, 0 }, + { "shm", "ahb3", WPCM450_CLK_SHM, 0 }, + { "usb1", "ahb", WPCM450_CLK_USB1, 0 }, + { "emc0", "ahb", WPCM450_CLK_EMC0, 0 }, + { "emc1", "ahb", WPCM450_CLK_EMC1, 0 }, + { "usb0", "ahb", WPCM450_CLK_USB0, 0 }, + { "peci", "apb", WPCM450_CLK_PECI, 0 }, + { "aes", "apb", WPCM450_CLK_AES, 0 }, + { "uart0", "uart", WPCM450_CLK_UART0, 0 }, + { "uart1", "uart", WPCM450_CLK_UART1, 0 }, + { "smb2", "apb", WPCM450_CLK_SMB2, 0 }, + { "smb3", "apb", WPCM450_CLK_SMB3, 0 }, + { "smb4", "apb", WPCM450_CLK_SMB4, 0 }, + { "smb5", "apb", WPCM450_CLK_SMB5, 0 }, + { "huart", "huartsel", WPCM450_CLK_HUART, 0 }, + { "pwm", "apb", WPCM450_CLK_PWM, 0 }, + { "timer0", "refdiv2", WPCM450_CLK_TIMER0, 0 }, + { "timer1", "refdiv2", WPCM450_CLK_TIMER1, 0 }, + { "timer2", "refdiv2", WPCM450_CLK_TIMER2, 0 }, + { "timer3", "refdiv2", WPCM450_CLK_TIMER3, 0 }, + { "timer4", "refdiv2", WPCM450_CLK_TIMER4, 0 }, + { "mft0", "apb", WPCM450_CLK_MFT0, 0 }, + { "mft1", "apb", WPCM450_CLK_MFT1, 0 }, + { "wdt", "refdiv2", WPCM450_CLK_WDT, 0 }, + { "adc", "adcdiv", WPCM450_CLK_ADC, 0 }, + { "sdio", "ahb", WPCM450_CLK_SDIO, 0 }, + { "sspi", "apb", WPCM450_CLK_SSPI, 0 }, + { "smb0", "apb", WPCM450_CLK_SMB0, 0 }, + { "smb1", "apb", WPCM450_CLK_SMB1, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +static void __init wpcm450_clk_init(struct device_node *clk_np) +{ + struct clk_hw_onecell_data *clk_data; + static struct clk_hw **hws; + static struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + struct reset_controller_dev *rcdev; + + clk_base = of_iomap(clk_np, 0); + if (!clk_base) { + pr_err("%pOFP: failed to map registers\n", clk_np); + of_node_put(clk_np); + return; + } + of_node_put(clk_np); + + clk_data = kzalloc(struct_size(clk_data, hws, WPCM450_NUM_CLKS), GFP_KERNEL); + if (!clk_data) + goto err_unmap; + + clk_data->num = WPCM450_NUM_CLKS; + hws = clk_data->hws; + + for (i = 0; i < WPCM450_NUM_CLKS; i++) + hws[i] = ERR_PTR(-ENOENT); + + // PLLs + for (i = 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data = &pll_data[i]; + + hw = wpcm450_clk_register_pll(clk_base + data->reg, data->name, + data->parent_name, data->flags); + if (IS_ERR(hw)) { + pr_info("Failed to register PLL: %pe", hw); + goto err_free; + } + } + + // Early divisors (REF/2) + for (i = 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data_early[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register div table: %pe\n", hw); + goto err_free; + } + } + + // Selects/muxes + for (i = 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data = &clksel_data[i]; + + hw = clk_hw_register_mux_table(NULL, data->name, data->parent_names, + data->num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + BIT(data->width) - 1, 0, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register mux: %pe\n", hw); + goto err_free; + } + if (data->index >= 0) + clk_data->hws[data->index] = hw; + } + + // Divisors + for (i = 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register divider: %pe\n", hw); + goto err_free; + } + } + + // Enables/gates + for (i = 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data = &clken_data[i]; + + hw = clk_hw_register_gate(NULL, data->name, data->parent_name, data->flags, + clk_base + REG_CLKEN, data->bitnum, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register gate: %pe\n", hw); + goto err_free; + } + clk_data->hws[data->bitnum] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, clk_data); + if (ret) + pr_err("Failed to add DT provider: %d\n", ret); + + // Reset controller + rcdev = kzalloc(sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + goto err_free; + rcdev->owner = THIS_MODULE; + rcdev->nr_resets = WPCM450_NUM_RESETS; + rcdev->ops = &reset_simple_ops; + rcdev->of_node = clk_np; + ret = reset_controller_register(rcdev); + if (ret) + pr_err("Failed to register reset controller: %d\n", ret); + + of_node_put(clk_np); + return; + +err_free: + kfree(clk_data->hws); +err_unmap: + iounmap(clk_base); + of_node_put(clk_np); +} + +CLK_OF_DECLARE(wpcm450_clk_init, "nuvoton,wpcm450-clk", wpcm450_clk_init); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index b496028b6bfaf..50a3c1403c335 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -201,7 +201,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC || ARCH_NPCM help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, From patchwork Fri Apr 22 18:30:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 12824099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C929C433F5 for ; Fri, 22 Apr 2022 22:04:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231566AbiDVWHU (ORCPT ); Fri, 22 Apr 2022 18:07:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231610AbiDVWGt (ORCPT ); Fri, 22 Apr 2022 18:06:49 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B7A3291D43; Fri, 22 Apr 2022 13:51:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650660666; bh=6YuxGgl4dOw9oAtmXhuC816ahBzK2oYrigEc+RKljBI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=XxhBYpwAnx3F5Ph7nOBaJLmzsaLZSn+4zGEk6qhibQNcRk6iUdL274+4s46A+aa5Y FcslNcjFsN1f+l2DFOOE2vyzsbqVjHBHBBVWrV0BClGmAgUDAHFakIh36pg9/pzF7B 9m+nYfQmn4LS/NGC6VbtvJZTIqVpgRlegxW9OiO4= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N7iCg-1nuMSS1S6M-014olk; Fri, 22 Apr 2022 20:31:58 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 7/7] ARM: dts: wpcm450: Switch clocks to clock controller Date: Fri, 22 Apr 2022 20:30:12 +0200 Message-Id: <20220422183012.444674-8-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:I67tF9Nlj04Phq6/V+ryuFf0Cliytuu3Zmf4FI2sPERSmiXM3XH R2sSgG7ktBlSjy9OdFQrd6Ec/8zwv1ZLrWy6vGPGRzJYTJArz+9bFEhqtpLtcF+CTwEUHq6 BpWfwBxU2AxUAF5JBamEAauV775wUODEbE6nCW1yOWZPbsvznU4uZmjcPzjJRpLIujUNFFB ooGmDpfMZ9LxJkCORbk5A== X-UI-Out-Filterresults: notjunk:1;V03:K0:L/wYOIf+TCA=:O9jlzwuzaT5O84sv+JhEb3 n7UoJQmivTypW6lqZMUajZkMH5cIpkYh2X7I1jFEMRyeOwGVt9LvAB75zDMXe4VZthpsLKMAf 2Oyfx8yNboNPrO75lUVFKE8yLa5CLOluD+9Q6NSDZqDzjH9wtzRNRVINyXsSDpYishXuQKfUr 67DgSvfHQKZ47T856eNBTTtvClNXJHdSlKAdJqO0K9jgk56XerPMjTwuyvaBpBpMRW3rIgi6K dZfzktDblXHY3Qsv2/r4XGUTcJuOMaZE5LK/pZk3kjaJoGAwOiIrdxGkPAeIufA9BiyeuGP0J /nlrg5yGP0pLmqQtS16l4oJN4VyVubeZ+HkgSnfge51Tmfd6WRv11Y41ViBtDepbSy3suFUpN 9Ncr4QRwHTAcSm7J9l4MxMwNw1B/7TzoFkpI7rH/VGfXlEIMi83MHwFVmc/7WNPZxCV5kesIK eZMArqMVgkhgF33RU7VuV+mxAkkpt3vxvCvYX7+plEN+XwndGYcU7p/anBQYUTz9oDf3Tzyey pvi9vk94efqSK2K3RwlKpTLPb8qKrN4ThJG5qEtzQh+CNZJzFMwMadjXA1Aj+ydLRTzieycMO 4YeCDv4nQA4yfFTF4+8Wl2sxYP0cBzk782qhv7IlV9wU8oXmmj+PTkOYspzOmjRKnQ9ou127D sobBjdkrXJt2tFvrysENSGpbg5JETizRMn2jtyhj/znXoMx6cubBKXo0NskDhZpUF6SSvIrL/ 4JFQHbzXkuS5zMfZUNzq8TJBYrm+wujpJiVtXvhtm916VUyZVI8SULPBklyyGzipYy+901Zbd FXP736xj2vHhd4ZgwFoiaNTEKHfeNk0nDFRHvKQcfS7hMRsH2HD2NDBkvfdKvSiy+a5FozRo+ 23jVLruDR/JWKj+PlsYQyniXVdMUz223zNH+lEkg112Jt+0ku1uzCaFPGsanLb7+IsGEqHko+ mX4fmaW07+22sfz+V1wqlVMQRAd04qNo82rMd+79dlmpuHnopitj0C0MfHw/o/WjRAqfiwbR0 csayr8UkZEbI8u47Xj9ZHLUxfVzpxF4Qt2eMA0thzMJzmyNBYSz9V+/HtLj3fTd7d4Ys9/ZFF fiLcUPDqkLb11o= Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 62d70fda7b520..f868bd7db009a 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -32,13 +33,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -73,7 +67,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -84,7 +78,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -92,14 +86,18 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 {