From patchwork Wed Apr 27 03:09:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2830C433EF for ; Wed, 27 Apr 2022 03:12:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353996AbiD0DP3 (ORCPT ); Tue, 26 Apr 2022 23:15:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346423AbiD0DP2 (ORCPT ); Tue, 26 Apr 2022 23:15:28 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7145B120B3; Tue, 26 Apr 2022 20:12:18 -0700 (PDT) X-UUID: 3be7f0f1650143e2be50c0f2079b59f1-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:8bce5474-d1c5-41d6-96ea-e4402a10e93c,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:6e01d42e-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 3be7f0f1650143e2be50c0f2079b59f1-20220427 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 842767396; Wed, 27 Apr 2022 11:12:13 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:13 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 01/15] clk: mediatek: reset: Add reset.h Date: Wed, 27 Apr 2022 11:09:36 +0800 Message-ID: <20220427030950.23395-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a new file "reset.h" to place some definitions for clock reset. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mtk.h | 8 ++------ drivers/clk/mediatek/reset.c | 9 +-------- drivers/clk/mediatek/reset.h | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 14 deletions(-) create mode 100644 drivers/clk/mediatek/reset.h diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bf6565aa7319..a6d0f24c62fa 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -13,6 +13,8 @@ #include #include +#include "reset.h" + #define MAX_MUX_GATE_BIT 31 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) @@ -190,12 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); -void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs); - -void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs); - struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index bcec4b89f449..9f3cb22aea1b 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -8,16 +8,9 @@ #include #include #include -#include #include -#include "clk-mtk.h" - -struct mtk_reset { - struct regmap *regmap; - int regofs; - struct reset_controller_dev rcdev; -}; +#include "reset.h" static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, unsigned long id) diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h new file mode 100644 index 000000000000..764a8affe206 --- /dev/null +++ b/drivers/clk/mediatek/reset.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __DRV_CLK_MTK_RESET_H +#define __DRV_CLK_MTK_RESET_H + +#include +#include + +struct mtk_reset { + struct regmap *regmap; + int regofs; + struct reset_controller_dev rcdev; +}; + +void mtk_register_reset_controller(struct device_node *np, + unsigned int num_regs, int regofs); + +void mtk_register_reset_controller_set_clr(struct device_node *np, + unsigned int num_regs, int regofs); + +#endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 27 03:09:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED208C433FE for ; Wed, 27 Apr 2022 03:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357493AbiD0DP4 (ORCPT ); Tue, 26 Apr 2022 23:15:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357433AbiD0DPo (ORCPT ); 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Wed, 27 Apr 2022 11:12:20 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:20 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:13 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 02/15] clk: mediatek: reset: Fix written reset bit offset Date: Wed, 27 Apr 2022 11:09:37 +0800 Message-ID: <20220427030950.23395-3-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/reset.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 9f3cb22aea1b..5191becb45dd 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -18,7 +18,7 @@ static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4); - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, @@ -27,7 +27,7 @@ static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; - return regmap_write(data->regmap, reg, 1); + return regmap_write(data->regmap, reg, BIT(id % 32)); } static int mtk_reset_assert(struct reset_controller_dev *rcdev, From patchwork Wed Apr 27 03:09:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3AD4C433FE for ; Wed, 27 Apr 2022 03:12:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346423AbiD0DPc (ORCPT ); Tue, 26 Apr 2022 23:15:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357301AbiD0DPb (ORCPT ); Tue, 26 Apr 2022 23:15:31 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5058F1208E; Tue, 26 Apr 2022 20:12:21 -0700 (PDT) X-UUID: 78fd13edaf394cd5b454027b6ec5460b-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:6a2e8c5e-37c9-4796-8700-12f31713791a,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:6a2e8c5e-37c9-4796-8700-12f31713791a,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:f501d42e-6199-437e-8ab4-9920b4bc5b76,C OID:1263bd427694,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 78fd13edaf394cd5b454027b6ec5460b-20220427 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 907694312; Wed, 27 Apr 2022 11:12:15 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:14 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 03/15] clk: mediatek: reset: Refine and reorder functions in reset.c Date: Wed, 27 Apr 2022 11:09:38 +0800 Message-ID: <20220427030950.23395-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To make drivers more readable, we modify the indentation of the drivers and reorder the location of functions. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/reset.c | 68 +++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 5191becb45dd..5cbbcc22a4fc 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -12,56 +12,59 @@ #include "reset.h" -static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - unsigned int reg = data->regofs + ((id / 32) << 4); - return regmap_write(data->regmap, reg, BIT(id % 32)); + return regmap_update_bits(data->regmap, + data->regofs + ((id / 32) << 2), + BIT(id % 32), ~0); } -static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; - return regmap_write(data->regmap, reg, BIT(id % 32)); + return regmap_update_bits(data->regmap, + data->regofs + ((id / 32) << 2), + BIT(id % 32), 0); } -static int mtk_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + int ret; + + ret = mtk_reset_assert(rcdev, id); + if (ret) + return ret; - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), ~0); + return mtk_reset_deassert(rcdev, id); } -static int mtk_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, + unsigned long id) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), 0); + return regmap_write(data->regmap, + data->regofs + ((id / 32) << 4), + BIT(id % 32)); } -static int mtk_reset(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, + unsigned long id) { - int ret; - - ret = mtk_reset_assert(rcdev, id); - if (ret) - return ret; + struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - return mtk_reset_deassert(rcdev, id); + return regmap_write(data->regmap, + data->regofs + ((id / 32) << 4) + 0x4, + BIT(id % 32)); } static int mtk_reset_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) + unsigned long id) { int ret; @@ -84,8 +87,9 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { }; static void mtk_register_reset_controller_common(struct device_node *np, - unsigned int num_regs, int regofs, - const struct reset_control_ops *reset_ops) + unsigned int num_regs, + int regofs, + const struct reset_control_ops *reset_ops) { struct mtk_reset *data; int ret; @@ -117,17 +121,17 @@ static void mtk_register_reset_controller_common(struct device_node *np, } void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs) + unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops); + &mtk_reset_ops); } void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs) + unsigned int num_regs, int regofs) { mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_set_clr); + &mtk_reset_ops_set_clr); } MODULE_LICENSE("GPL"); From patchwork Wed Apr 27 03:09:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828216 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACD95C4167B for ; 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Wed, 27 Apr 2022 11:12:16 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 27 Apr 2022 11:12:16 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:14 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 04/15] clk: mediatek: reset: Extract common drivers to update function Date: Wed, 27 Apr 2022 11:09:39 +0800 Message-ID: <20220427030950.23395-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To make drivers more clear and readable, we extract common code within assert and deassert to mtk_reset_update_set_clr() and mtk_reset_update(). Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/reset.c | 38 +++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 5cbbcc22a4fc..22fa9f09752c 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -12,24 +12,27 @@ #include "reset.h" -static int mtk_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool deassert) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + unsigned int val = deassert ? 0 : ~0; return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), - BIT(id % 32), ~0); + BIT(id % 32), val); +} + +static int mtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return mtk_reset_update(rcdev, id, false); } static int mtk_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - - return regmap_update_bits(data->regmap, - data->regofs + ((id / 32) << 2), - BIT(id % 32), 0); + return mtk_reset_update(rcdev, id, true); } static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id) @@ -43,24 +46,27 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id) return mtk_reset_deassert(rcdev, id); } -static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, - unsigned long id) +static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev, + unsigned long id, bool deassert) { struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + unsigned int deassert_ofs = deassert ? 0x4 : 0; return regmap_write(data->regmap, - data->regofs + ((id / 32) << 4), + data->regofs + ((id / 32) << 4) + deassert_ofs, BIT(id % 32)); } +static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return mtk_reset_update_set_clr(rcdev, id, false); +} + static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev, unsigned long id) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); - - return regmap_write(data->regmap, - data->regofs + ((id / 32) << 4) + 0x4, - BIT(id % 32)); + return mtk_reset_update_set_clr(rcdev, id, true); } static int mtk_reset_set_clr(struct reset_controller_dev *rcdev, From patchwork Wed Apr 27 03:09:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34C75C433FE for ; Wed, 27 Apr 2022 03:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357436AbiD0DPo (ORCPT ); Tue, 26 Apr 2022 23:15:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357416AbiD0DPk (ORCPT ); Tue, 26 Apr 2022 23:15:40 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B43512A88; Tue, 26 Apr 2022 20:12:28 -0700 (PDT) X-UUID: 3f502fc15881466b9a4400d5505579f4-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:17244ee9-80ad-49b2-9a59-cd4aac1ae91a,OB:20,L OB:10,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham ,ACTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:17244ee9-80ad-49b2-9a59-cd4aac1ae91a,OB:20,LOB :10,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:2903d42e-6199-437e-8ab4-9920b4bc5b76,C OID:c943d8bcd364,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 3f502fc15881466b9a4400d5505579f4-20220427 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 920324095; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:20 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:15 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:15 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 05/15] clk: mediatek: reset: Merge and revise reset register function Date: Wed, 27 Apr 2022 11:09:40 +0800 Message-ID: <20220427030950.23395-6-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org There are two versions for clock reset register control of MediaTek SoCs. The old hardware is one bit per reset control, and does not have separate registers for bit set, clear and read-back operations. This matches the scheme supported by the simple reset driver. However, because we need to use different data structure from reset_simple_data, we can not use the operation of simple reset driver. For this reason, we keep the original functions and name this version as "MTK_RST_SIMPLE". In this patch: - Add a version enumeration to separate different reset hardware. - Merge the reset register function of simple and set_clr into one function "mtk_register_reset_controller". - Rename input variable "num_regs" to "rst_bank_nr" to avoid confusion. This variable is used to define the quantity of reset bank. - Document mtk_reset_version and mtk_register_reset_controller. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +-- drivers/clk/mediatek/clk-mt2712.c | 4 +-- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +-- drivers/clk/mediatek/clk-mt7622.c | 4 +-- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +-- drivers/clk/mediatek/clk-mt8135.c | 4 +-- drivers/clk/mediatek/clk-mt8173.c | 4 +-- drivers/clk/mediatek/clk-mt8183.c | 3 +- drivers/clk/mediatek/reset.c | 40 ++++++++++++--------------- drivers/clk/mediatek/reset.h | 24 +++++++++++++--- 15 files changed, 59 insertions(+), 46 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 100ff6ca609e..0270979ccc20 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 1328c112a38f..e406f863dcf0 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0xc); + mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 61444881c539..352ca7a646c3 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 1eb3e4563c3f..591479222e75 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -785,7 +785,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); return 0; } @@ -908,7 +908,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index ff72b9ab945b..b311b43fbbd3 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); return r; } @@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index c9947dc7ba5a..bfdd09f3b72d 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 628be0c9f888..892da27f6077 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return r; } @@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 0e1fb30a1e98..5bb3757f4217 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -663,7 +663,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 1, 0x30); + mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE); return 0; } @@ -714,7 +714,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_register_reset_controller(node, 2, 0x0); + mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 88279d0ea1a7..1c57589b39fd 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -92,7 +92,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 5c5b37207afb..6761151ca839 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return r; } @@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34); + mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); return r; } diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 09ad272d51f1..d95b5dfa580c 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -559,7 +559,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -587,7 +587,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 46b7655feeaa..56120b148761 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -882,7 +882,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30); + mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -910,7 +910,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0); + mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 68496554dd3d..9b27f1ffc600 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1239,7 +1239,8 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET); + mtk_register_reset_controller(node, 4, + INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR); return r; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 22fa9f09752c..a54a835c1d47 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -92,14 +92,25 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { .reset = mtk_reset_set_clr, }; -static void mtk_register_reset_controller_common(struct device_node *np, - unsigned int num_regs, - int regofs, - const struct reset_control_ops *reset_ops) +void mtk_register_reset_controller(struct device_node *np, + u32 rst_bank_nr, u16 reg_ofs, u8 version) { struct mtk_reset *data; int ret; struct regmap *regmap; + const struct reset_control_ops *rcops = NULL; + + switch (version) { + case MTK_RST_SIMPLE: + rcops = &mtk_reset_ops; + break; + case MTK_RST_SET_CLR: + rcops = &mtk_reset_ops_set_clr; + break; + default: + pr_err("Unknown reset version %d\n", version); + return; + } regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { @@ -112,32 +123,17 @@ static void mtk_register_reset_controller_common(struct device_node *np, return; data->regmap = regmap; - data->regofs = regofs; + data->regofs = reg_ofs; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = num_regs * 32; - data->rcdev.ops = reset_ops; + data->rcdev.nr_resets = rst_bank_nr * 32; + data->rcdev.ops = rcops; data->rcdev.of_node = np; ret = reset_controller_register(&data->rcdev); if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); - return; } } -void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs) -{ - mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops); -} - -void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs) -{ - mtk_register_reset_controller_common(np, num_regs, regofs, - &mtk_reset_ops_set_clr); -} - MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 764a8affe206..2a39eec9cff7 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -9,16 +9,32 @@ #include #include +/** + * enum mtk_reset_version - Version of MediaTek clock reset controller. + * @MTK_RST_SIMPLE: Use the same registers for bit set and clear. + * @MTK_RST_SET_CLR: Use separate registers for bit set and clear. + * @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller. + */ +enum mtk_reset_version { + MTK_RST_SIMPLE = 0, + MTK_RST_SET_CLR, + MTK_RST_MAX, +}; + struct mtk_reset { struct regmap *regmap; int regofs; struct reset_controller_dev rcdev; }; +/** + * mtk_register_reset_controller - Register MediaTek clock reset controller + * @np: Pointer to device node. + * @rst_bank_nr: Quantity of reset bank. + * @reg_ofs: Base offset of the reset register. + * @version: Version of MediaTek clock reset controller. + */ void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs); - -void mtk_register_reset_controller_set_clr(struct device_node *np, - unsigned int num_regs, int regofs); + u32 rst_bank_nr, u16 reg_ofs, u8 version); #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 27 03:09:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828220 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7C68C43219 for ; Wed, 27 Apr 2022 03:12:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357420AbiD0DPm (ORCPT ); Tue, 26 Apr 2022 23:15:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357401AbiD0DPh (ORCPT ); Tue, 26 Apr 2022 23:15:37 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F79A12A8C; Tue, 26 Apr 2022 20:12:25 -0700 (PDT) X-UUID: 1b5f3de80a6947658c225ee5bfb89870-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:00f801c3-a65b-46f9-8759-2df83c82e3e2,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:2cf59bc6-85ee-4ac1-ac05-bd3f1e72e732,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 1b5f3de80a6947658c225ee5bfb89870-20220427 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 687051225; Wed, 27 Apr 2022 11:12:18 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:17 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 06/15] clk: mediatek: reset: Revise structure to control reset register Date: Wed, 27 Apr 2022 11:09:41 +0800 Message-ID: <20220427030950.23395-7-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To declare the reset data easier, we add a strucure to do this instead of using many input variables to mtk_register_reset_controller(). - Add mtk_clk_rst_desc to define the reset description when registering the reset controller. - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store data of reset controller. - Document mtk_clk_rst_desc and mtk_clk_rst_data. - Modify the documentation of mtk_register_reset_controller. - Extract container_of in update functions to to_mtk_clk_rst_data(). Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-eth.c | 8 ++++++- drivers/clk/mediatek/clk-mt2701-g3d.c | 8 ++++++- drivers/clk/mediatek/clk-mt2701-hif.c | 8 ++++++- drivers/clk/mediatek/clk-mt2701.c | 19 ++++++++++++++-- drivers/clk/mediatek/clk-mt2712.c | 19 ++++++++++++++-- drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++++- drivers/clk/mediatek/clk-mt7622-hif.c | 10 +++++++-- drivers/clk/mediatek/clk-mt7622.c | 19 ++++++++++++++-- drivers/clk/mediatek/clk-mt7629-eth.c | 8 ++++++- drivers/clk/mediatek/clk-mt7629-hif.c | 10 +++++++-- drivers/clk/mediatek/clk-mt8135.c | 19 ++++++++++++++-- drivers/clk/mediatek/clk-mt8173.c | 19 ++++++++++++++-- drivers/clk/mediatek/clk-mt8183.c | 9 ++++++-- drivers/clk/mediatek/reset.c | 32 ++++++++++++++++++--------- drivers/clk/mediatek/reset.h | 28 ++++++++++++++++++----- 15 files changed, 186 insertions(+), 38 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 0270979ccc20..2cc35dfdbca7 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -36,6 +36,12 @@ static const struct mtk_gate eth_clks[] = { GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0x34, +}; + static const struct of_device_id of_match_clk_mt2701_eth[] = { { .compatible = "mediatek,mt2701-ethsys", }, {} @@ -58,7 +64,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index e406f863dcf0..0905d5c12691 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -35,6 +35,12 @@ static const struct mtk_gate g3d_clks[] = { GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0xc, +}; + static int clk_mt2701_g3dsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -52,7 +58,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 352ca7a646c3..24d5bac1bb9b 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -33,6 +33,12 @@ static const struct mtk_gate hif_clks[] = { GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0x34, +}; + static const struct of_device_id of_match_clk_mt2701_hif[] = { { .compatible = "mediatek,mt2701-hifsys", }, {} @@ -57,7 +63,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 591479222e75..70a934faa529 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -735,6 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x0, + }, +}; + static struct clk_onecell_data *infra_clk_data; static void __init mtk_infrasys_init_early(struct device_node *node) @@ -785,7 +800,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[0]); return 0; } @@ -908,7 +923,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index b311b43fbbd3..cef7c79788ec 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1258,6 +1258,21 @@ static const struct mtk_pll_data plls[] = { 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infra */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x30, + }, + /* peri */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x0, + }, +}; + static int clk_mt2712_apmixed_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -1361,7 +1376,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[0]); return r; } @@ -1383,7 +1398,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[1]); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index bfdd09f3b72d..b6da1871a1f9 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -65,6 +65,12 @@ static const struct mtk_gate sgmii_clks[] = { "ssusb_cdr_fb", 5), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7622_ethsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -82,7 +88,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 892da27f6077..c2841deb52a5 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -76,6 +76,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -93,7 +99,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } @@ -115,7 +121,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 5bb3757f4217..880e752527a9 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -610,6 +610,21 @@ static struct mtk_composite peri_muxes[] = { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x0, + }, +}; + static int mtk_topckgen_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -663,7 +678,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, 1, 0x30, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[0]); return 0; } @@ -714,7 +729,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 1c57589b39fd..e054aa1e1479 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -76,6 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = { } }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7629_ethsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -92,7 +98,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 6761151ca839..ab085092041e 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -71,6 +71,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 1, + .reg_ofs = 0x34, +}; + static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -88,7 +94,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } @@ -110,7 +116,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index d95b5dfa580c..a4cfc094895c 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -514,6 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = { MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x0, + } +}; + static void __init mtk_topckgen_init(struct device_node *node) { struct clk_onecell_data *clk_data; @@ -559,7 +574,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[0]); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); @@ -587,7 +602,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[1]); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 56120b148761..cba1495b2a67 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -819,6 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = { GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; +static const struct mtk_clk_rst_desc clk_rst_desc[] = { + /* infrasys */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x30, + }, + /* pericfg */ + { + .version = MTK_RST_SIMPLE, + .rst_bank_nr = 2, + .reg_ofs = 0x0, + } +}; + static struct clk_onecell_data *mt8173_top_clk_data __initdata; static struct clk_onecell_data *mt8173_pll_clk_data __initdata; @@ -882,7 +897,7 @@ static void __init mtk_infrasys_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[0]); } CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); @@ -910,7 +925,7 @@ static void __init mtk_pericfg_init(struct device_node *node) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE); + mtk_register_reset_controller(node, &clk_rst_desc[1]); } CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 9b27f1ffc600..3517eca5ee83 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1153,6 +1153,12 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), }; +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_nr = 4, + .reg_ofs = INFRA_RST0_SET_OFFSET, +}; + static int clk_mt8183_apmixed_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; @@ -1239,8 +1245,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller(node, 4, - INFRA_RST0_SET_OFFSET, MTK_RST_SET_CLR); + mtk_register_reset_controller(node, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index a54a835c1d47..47bc6b1842fd 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -12,14 +12,19 @@ #include "reset.h" +static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct mtk_clk_rst_data, rcdev); +} + static int mtk_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool deassert) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev); unsigned int val = deassert ? 0 : ~0; return regmap_update_bits(data->regmap, - data->regofs + ((id / 32) << 2), + data->desc->reg_ofs + ((id / 32) << 2), BIT(id % 32), val); } @@ -49,11 +54,11 @@ static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id) static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev, unsigned long id, bool deassert) { - struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); + struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev); unsigned int deassert_ofs = deassert ? 0x4 : 0; return regmap_write(data->regmap, - data->regofs + ((id / 32) << 4) + deassert_ofs, + data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs, BIT(id % 32)); } @@ -93,14 +98,19 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { }; void mtk_register_reset_controller(struct device_node *np, - u32 rst_bank_nr, u16 reg_ofs, u8 version) + const struct mtk_clk_rst_desc *desc) { - struct mtk_reset *data; - int ret; struct regmap *regmap; const struct reset_control_ops *rcops = NULL; + struct mtk_clk_rst_data *data; + int ret; + + if (!desc) { + pr_err("mtk clock reset desc is NULL\n"); + return; + } - switch (version) { + switch (desc->version) { case MTK_RST_SIMPLE: rcops = &mtk_reset_ops; break; @@ -108,7 +118,7 @@ void mtk_register_reset_controller(struct device_node *np, rcops = &mtk_reset_ops_set_clr; break; default: - pr_err("Unknown reset version %d\n", version); + pr_err("Unknown reset version %d\n", desc->version); return; } @@ -122,10 +132,10 @@ void mtk_register_reset_controller(struct device_node *np, if (!data) return; + data->desc = desc; data->regmap = regmap; - data->regofs = reg_ofs; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = rst_bank_nr * 32; + data->rcdev.nr_resets = desc->rst_bank_nr * 32; data->rcdev.ops = rcops; data->rcdev.of_node = np; diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 2a39eec9cff7..91358e8cb851 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -21,20 +21,36 @@ enum mtk_reset_version { MTK_RST_MAX, }; -struct mtk_reset { +/** + * struct mtk_clk_rst_desc - Description of MediaTek clock reset. + * @version: Reset version which is defined in enum mtk_reset_version. + * @reg_ofs: Base offset of the reset register. + * @rst_bank_nr: Quantity of reset bank. + */ +struct mtk_clk_rst_desc { + u8 version; + u16 reg_ofs; + u32 rst_bank_nr; +}; + +/** + * struct mtk_clk_rst_data - Data of MediaTek clock reset controller. + * @regmap: Pointer to base address of reset register address. + * @rcdev: Reset controller device. + * @desc: Pointer to description of the reset controller. + */ +struct mtk_clk_rst_data { struct regmap *regmap; - int regofs; struct reset_controller_dev rcdev; + const struct mtk_clk_rst_desc *desc; }; /** * mtk_register_reset_controller - Register MediaTek clock reset controller * @np: Pointer to device node. - * @rst_bank_nr: Quantity of reset bank. - * @reg_ofs: Base offset of the reset register. - * @version: Version of MediaTek clock reset controller. + * @desc: Constant pointer to description of clock reset. */ void mtk_register_reset_controller(struct device_node *np, - u32 rst_bank_nr, u16 reg_ofs, u8 version); + const struct mtk_clk_rst_desc *desc); #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 27 03:09:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CE71C4332F for ; Wed, 27 Apr 2022 03:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357440AbiD0DPz (ORCPT ); Tue, 26 Apr 2022 23:15:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357442AbiD0DPo (ORCPT ); Tue, 26 Apr 2022 23:15:44 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77EAF12A8C; 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Wed, 27 Apr 2022 11:12:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:17 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 07/15] clk: mediatek: reset: Support nonsequence base offsets of reset registers Date: Wed, 27 Apr 2022 11:09:42 +0800 Message-ID: <20220427030950.23395-8-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt2701-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701-g3d.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701.c | 11 +++++++---- drivers/clk/mediatek/clk-mt2712.c | 15 +++++++++------ drivers/clk/mediatek/clk-mt7622-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt7622-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt7622.c | 11 +++++++---- drivers/clk/mediatek/clk-mt7629-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt7629-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt8135.c | 11 +++++++---- drivers/clk/mediatek/clk-mt8173.c | 11 +++++++---- drivers/clk/mediatek/clk-mt8183.c | 14 ++++++++++++-- drivers/clk/mediatek/reset.c | 11 ++++++----- drivers/clk/mediatek/reset.h | 6 ++++-- 15 files changed, 87 insertions(+), 45 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 2cc35dfdbca7..0ae4bce3bb37 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -36,10 +36,12 @@ static const struct mtk_gate eth_clks[] = { GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static const struct of_device_id of_match_clk_mt2701_eth[] = { diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 0905d5c12691..8d2053517ddc 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -35,10 +35,12 @@ static const struct mtk_gate g3d_clks[] = { GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; +static u16 rst_ofs[] = { 0xC, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0xc, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt2701_g3dsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 24d5bac1bb9b..e40865a6f45e 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -33,10 +33,12 @@ static const struct mtk_gate hif_clks[] = { GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static const struct of_device_id of_match_clk_mt2701_hif[] = { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 70a934faa529..ebb1b9975ab0 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = perfcfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(perfcfg_rst_ofs), }, }; diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index cef7c79788ec..2a9d70dd97d6 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] = { 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { - /* infra */ + /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, - /* peri */ + /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = perfcfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(perfcfg_rst_ofs), }, }; diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index b6da1871a1f9..b58fe61a8443 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -65,10 +65,12 @@ static const struct mtk_gate sgmii_clks[] = { "ssusb_cdr_fb", 5), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7622_ethsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index c2841deb52a5..1ee79d4837a4 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -76,10 +76,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 880e752527a9..d6e7c9dd54e6 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -610,18 +610,21 @@ static struct mtk_composite peri_muxes[] = { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; +static u16 infrasys_rst_ofs[] = { 0x30, }; +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = perfcfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(perfcfg_rst_ofs), }, }; diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index e054aa1e1479..56ff7c1f6ec1 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -76,10 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] = { } }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7629_ethsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index ab085092041e..fc12110b04fc 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -71,10 +71,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index a4cfc094895c..6c8a9485e960 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -514,18 +514,21 @@ static const struct mtk_composite peri_clks[] __initconst = { MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = perfcfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(perfcfg_rst_ofs), } }; diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index cba1495b2a67..df388edfb12d 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -819,18 +819,21 @@ static const struct mtk_gate venclt_clks[] __initconst = { GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] = { /* infrasys */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x30, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 2, - .reg_ofs = 0x0, + .rst_bank_ofs = perfcfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(perfcfg_rst_ofs), } }; diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 3517eca5ee83..de4ba5e055ca 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -20,6 +20,9 @@ /* Infra global controller reset set register */ #define INFRA_RST0_SET_OFFSET 0x120 +#define INFRA_RST1_SET_OFFSET 0x130 +#define INFRA_RST2_SET_OFFSET 0x140 +#define INFRA_RST3_SET_OFFSET 0x150 static DEFINE_SPINLOCK(mt8183_clk_lock); @@ -1153,10 +1156,17 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), }; +static u16 infra_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, +}; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SET_CLR, - .rst_bank_nr = 4, - .reg_ofs = INFRA_RST0_SET_OFFSET, + .rst_bank_ofs = infra_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), }; static int clk_mt8183_apmixed_probe(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 47bc6b1842fd..11b2f74f121d 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -24,8 +24,8 @@ static int mtk_reset_update(struct reset_controller_dev *rcdev, unsigned int val = deassert ? 0 : ~0; return regmap_update_bits(data->regmap, - data->desc->reg_ofs + ((id / 32) << 2), - BIT(id % 32), val); + data->desc->rst_bank_ofs[id / RST_NR_PER_BANK], + BIT(id % RST_NR_PER_BANK), val); } static int mtk_reset_assert(struct reset_controller_dev *rcdev, @@ -58,8 +58,9 @@ static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev, unsigned int deassert_ofs = deassert ? 0x4 : 0; return regmap_write(data->regmap, - data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs, - BIT(id % 32)); + data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] + + deassert_ofs, + BIT(id % RST_NR_PER_BANK)); } static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, @@ -135,7 +136,7 @@ void mtk_register_reset_controller(struct device_node *np, data->desc = desc; data->regmap = regmap; data->rcdev.owner = THIS_MODULE; - data->rcdev.nr_resets = desc->rst_bank_nr * 32; + data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; data->rcdev.ops = rcops; data->rcdev.of_node = np; diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 91358e8cb851..83840ecf8b27 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -9,6 +9,8 @@ #include #include +#define RST_NR_PER_BANK 32 + /** * enum mtk_reset_version - Version of MediaTek clock reset controller. * @MTK_RST_SIMPLE: Use the same registers for bit set and clear. @@ -24,12 +26,12 @@ enum mtk_reset_version { /** * struct mtk_clk_rst_desc - Description of MediaTek clock reset. * @version: Reset version which is defined in enum mtk_reset_version. - * @reg_ofs: Base offset of the reset register. + * @rst_bank_ofs: Pointer to base offsets of the reset register. * @rst_bank_nr: Quantity of reset bank. */ struct mtk_clk_rst_desc { u8 version; - u16 reg_ofs; + u16 *rst_bank_ofs; u32 rst_bank_nr; }; From patchwork Wed Apr 27 03:09:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45588C4167E for ; Wed, 27 Apr 2022 03:12:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357397AbiD0DPg (ORCPT ); Tue, 26 Apr 2022 23:15:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357387AbiD0DPf (ORCPT ); Tue, 26 Apr 2022 23:15:35 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F1EA12A88; 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Wed, 27 Apr 2022 11:12:18 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 08/15] clk: mediatek: reset: Change return type for clock reset register function Date: Wed, 27 Apr 2022 11:09:43 +0800 Message-ID: <20220427030950.23395-9-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To deal with error handling, we change the function return type from void to int for mtk_clk_register_rst_ctrl(). Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/reset.c | 15 +++++++++------ drivers/clk/mediatek/reset.h | 6 ++++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 11b2f74f121d..a1d281d2a2d5 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -98,8 +98,8 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = { .reset = mtk_reset_set_clr, }; -void mtk_register_reset_controller(struct device_node *np, - const struct mtk_clk_rst_desc *desc) +int mtk_register_reset_controller(struct device_node *np, + const struct mtk_clk_rst_desc *desc) { struct regmap *regmap; const struct reset_control_ops *rcops = NULL; @@ -108,7 +108,7 @@ void mtk_register_reset_controller(struct device_node *np, if (!desc) { pr_err("mtk clock reset desc is NULL\n"); - return; + return -EINVAL; } switch (desc->version) { @@ -120,18 +120,18 @@ void mtk_register_reset_controller(struct device_node *np, break; default: pr_err("Unknown reset version %d\n", desc->version); - return; + return -EINVAL; } regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); - return; + return -EINVAL; } data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return; + return -ENOMEM; data->desc = desc; data->regmap = regmap; @@ -144,7 +144,10 @@ void mtk_register_reset_controller(struct device_node *np, if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); + return ret; } + + return 0; } MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 83840ecf8b27..2135da877826 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -51,8 +51,10 @@ struct mtk_clk_rst_data { * mtk_register_reset_controller - Register MediaTek clock reset controller * @np: Pointer to device node. * @desc: Constant pointer to description of clock reset. + * + * Return: 0 on success and errorno otherwise. */ -void mtk_register_reset_controller(struct device_node *np, - const struct mtk_clk_rst_desc *desc); +int mtk_register_reset_controller(struct device_node *np, + const struct mtk_clk_rst_desc *desc); #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 27 03:09:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6DE4C35274 for ; Wed, 27 Apr 2022 03:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357444AbiD0DPq (ORCPT ); Tue, 26 Apr 2022 23:15:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357415AbiD0DPk (ORCPT ); Tue, 26 Apr 2022 23:15:40 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 889D012626; 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Wed, 27 Apr 2022 11:12:18 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:18 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 09/15] clk: mediatek: reset: Add new register reset function with device Date: Wed, 27 Apr 2022 11:09:44 +0800 Message-ID: <20220427030950.23395-10-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Using device to register reset controller is a better implementation in current drivers. Howerver, some clock drviers of MediaTek only provide device_node. Therefore, we still remain the register reset function with device_node and add a new function with device to register reset controller. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +- drivers/clk/mediatek/clk-mt2712.c | 4 +- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +- drivers/clk/mediatek/clk-mt7622.c | 4 +- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +- drivers/clk/mediatek/clk-mt8183.c | 2 +- drivers/clk/mediatek/reset.c | 53 +++++++++++++++++++++++++++ drivers/clk/mediatek/reset.h | 10 +++++ 13 files changed, 79 insertions(+), 16 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 0ae4bce3bb37..38fd15c8f6f6 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -66,7 +66,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 8d2053517ddc..d5ff16e02d0e 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -60,7 +60,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index e40865a6f45e..b642109e7fa8 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -65,7 +65,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index ebb1b9975ab0..f75dcd8db9d8 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -803,7 +803,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); return 0; } @@ -926,7 +926,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 2a9d70dd97d6..1174db8d5be5 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1379,7 +1379,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); return r; } @@ -1401,7 +1401,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index b58fe61a8443..ecaf0717947d 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -90,7 +90,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 1ee79d4837a4..98aac2b5b504 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -101,7 +101,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } @@ -123,7 +123,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index d6e7c9dd54e6..cbe91d16a518 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -681,7 +681,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (r) return r; - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); return 0; } @@ -732,7 +732,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 56ff7c1f6ec1..69b9682f9ceb 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -100,7 +100,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index fc12110b04fc..9b80b771a62b 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -96,7 +96,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } @@ -118,7 +118,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index de4ba5e055ca..c7d5ffacbd1d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1255,7 +1255,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) return r; } - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); return r; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index a1d281d2a2d5..de3e2ccef4e8 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -150,4 +150,57 @@ int mtk_register_reset_controller(struct device_node *np, return 0; } +int mtk_register_reset_controller_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc) +{ + struct device_node *np = dev->of_node; + struct regmap *regmap; + const struct reset_control_ops *rcops = NULL; + struct mtk_clk_rst_data *data; + int ret; + + if (!desc) { + dev_err(dev, "mtk clock reset desc is NULL\n"); + return -EINVAL; + } + + switch (desc->version) { + case MTK_RST_SIMPLE: + rcops = &mtk_reset_ops; + break; + case MTK_RST_SET_CLR: + rcops = &mtk_reset_ops_set_clr; + break; + default: + dev_err(dev, "Unknown reset version %d\n", desc->version); + return -EINVAL; + } + + regmap = device_node_to_regmap(np); + if (IS_ERR(regmap)) { + dev_err(dev, "Cannot find regmap %pe\n", regmap); + return -EINVAL; + } + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->desc = desc; + data->regmap = regmap; + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; + data->rcdev.ops = rcops; + data->rcdev.of_node = np; + data->rcdev.dev = dev; + + ret = devm_reset_controller_register(dev, &data->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller: %d\n", ret); + return ret; + } + + return 0; +} + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 2135da877826..470588b82418 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -57,4 +57,14 @@ struct mtk_clk_rst_data { int mtk_register_reset_controller(struct device_node *np, const struct mtk_clk_rst_desc *desc); +/** + * mtk_register_reset_controller - Register MediaTek clock reset controller with device + * @np: Pointer to device. + * @desc: Constant pointer to description of clock reset. + * + * Return: 0 on success and errorno otherwise. + */ +int mtk_register_reset_controller_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc); + #endif /* __DRV_CLK_MTK_RESET_H */ From patchwork Wed Apr 27 03:09:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828217 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2308C41535 for ; Wed, 27 Apr 2022 03:12:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357402AbiD0DPh (ORCPT ); Tue, 26 Apr 2022 23:15:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357390AbiD0DPf (ORCPT ); Tue, 26 Apr 2022 23:15:35 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6969812AAC; Tue, 26 Apr 2022 20:12:25 -0700 (PDT) X-UUID: c5c152612542461c92ba54b9d3e43d81-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:ccf2d204-e1c6-48c0-a58a-7e8f6ab11c1c,OB:20,L OB:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:ccf2d204-e1c6-48c0-a58a-7e8f6ab11c1c,OB:20,LOB :0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:9102d42e-6199-437e-8ab4-9920b4bc5b76,C OID:1263bd427694,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: c5c152612542461c92ba54b9d3e43d81-20220427 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2075285688; Wed, 27 Apr 2022 11:12:21 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 27 Apr 2022 11:12:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:19 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 10/15] clk: mediatek: reset: Add reset support for simple probe Date: Wed, 27 Apr 2022 11:09:45 +0800 Message-ID: <20220427030950.23395-11-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org - Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc". - Add register reset with device function in mtk_clk_simple_probe(). Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mtk.c | 7 +++++++ drivers/clk/mediatek/clk-mtk.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4063261cf56..2c72e5839d50 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -453,6 +453,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev) platform_set_drvdata(pdev, clk_data); + if (mcd->rst_desc) { + r = mtk_register_reset_controller_with_dev(&pdev->dev, + mcd->rst_desc); + if (r) + goto unregister_clks; + } + return r; unregister_clks: diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index a6d0f24c62fa..2c7800bcb1a2 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -195,6 +195,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name, struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; + const struct mtk_clk_rst_desc *rst_desc; }; int mtk_clk_simple_probe(struct platform_device *pdev); From patchwork Wed Apr 27 03:09:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6058EC433F5 for ; Wed, 27 Apr 2022 03:12:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357475AbiD0DPs (ORCPT ); Tue, 26 Apr 2022 23:15:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357428AbiD0DPn (ORCPT ); Tue, 26 Apr 2022 23:15:43 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FAE612ADB; Tue, 26 Apr 2022 20:12:29 -0700 (PDT) X-UUID: 9a3202d1494542a5af9d767aef04e3cf-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:0ca216eb-4440-42f2-9aae-cfa38e7b9951,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:b5f59bc6-85ee-4ac1-ac05-bd3f1e72e732,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 9a3202d1494542a5af9d767aef04e3cf-20220427 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1457098443; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 27 Apr 2022 11:12:21 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:19 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 11/15] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Date: Wed, 27 Apr 2022 11:09:46 +0800 Message-ID: <20220427030950.23395-12-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We will use the infra_ao reset which is defined in mt8192-sys-clock and mt8195-sys-clock. The value of reset-cells is always equal to 1. Signed-off-by: Rex-BC Chen Acked-by: Krzysztof Kozlowski --- .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml | 3 +++ .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml | 3 +++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml index 5705bcf1fe47..27f79175c678 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml @@ -29,6 +29,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml index 57a1503d95fe..95b6bdf99936 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml @@ -37,6 +37,9 @@ properties: '#clock-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg From patchwork Wed Apr 27 03:09:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828219 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3C79C4332F for ; Wed, 27 Apr 2022 03:12:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357418AbiD0DPk (ORCPT ); Tue, 26 Apr 2022 23:15:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357372AbiD0DPg (ORCPT ); Tue, 26 Apr 2022 23:15:36 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3688112AB1; Tue, 26 Apr 2022 20:12:26 -0700 (PDT) X-UUID: 66b716581ac54497bb89dc9a0819c794-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:a2da5397-fdc2-4111-aee8-ba475d7bcf6e,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:a2da5397-fdc2-4111-aee8-ba475d7bcf6e,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:2303d42e-6199-437e-8ab4-9920b4bc5b76,C OID:c943d8bcd364,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 66b716581ac54497bb89dc9a0819c794-20220427 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 220203164; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:20 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 12/15] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192/MT8195 Date: Wed, 27 Apr 2022 11:09:47 +0800 Message-ID: <20220427030950.23395-13-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org - To support reset of infra_ao, add the bit definition of thermal/PCIe/SVS for MT8192. - To support reset of infra_ao, add the bit definition of thermal/SVS for MT8195. - Add the driver comment to separate the reset index for TOPRGU and INFRA. Signed-off-by: Rex-BC Chen --- include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++ include/dt-bindings/reset/mt8195-resets.h | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index be9a7ca245b9..ee0ca02a39bf 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 +/* TOPRGU resets */ #define MT8192_TOPRGU_MM_SW_RST 1 #define MT8192_TOPRGU_MFG_SW_RST 2 #define MT8192_TOPRGU_VENC_SW_RST 3 @@ -27,4 +28,11 @@ #define MT8192_TOPRGU_SW_RST_NUM 23 +/* INFRA resets */ +#define MT8192_INFRA_THERMAL_CTRL_RST 0 +#define MT8192_INFRA_PEXTP_PHY_RST 79 +#define MT8192_INFRA_PTP_RST 101 +#define MT8192_INFRA_RST4_PCIE_TOP 129 +#define MT8192_INFRA_THERMAL_CTRL_MCU_RST 140 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..a3226f40779c 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 #define _DT_BINDINGS_RESET_CONTROLLER_MT8195 +/* TOPRGU resets */ #define MT8195_TOPRGU_CONN_MCU_SW_RST 0 #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 #define MT8195_TOPRGU_APU_SW_RST 2 @@ -26,4 +27,9 @@ #define MT8195_TOPRGU_SW_RST_NUM 16 +/* INFRA resets */ +#define MT8195_INFRA_THERMAL_AP_RST 0 +#define MT8195_INFRA_PTP_RST 101 +#define MT8195_INFRA_THERMAL_MCU_RST 138 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ From patchwork Wed Apr 27 03:09:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA1A5C46467 for ; Wed, 27 Apr 2022 03:12:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357470AbiD0DPr (ORCPT ); Tue, 26 Apr 2022 23:15:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357426AbiD0DPn (ORCPT ); Tue, 26 Apr 2022 23:15:43 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F35B12771; Tue, 26 Apr 2022 20:12:29 -0700 (PDT) X-UUID: 670b02f807454e78a3addee14d718625-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:e8db2691-5d7e-4359-bf93-645c08a05a7e,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:1703d42e-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 670b02f807454e78a3addee14d718625-20220427 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 609843609; Wed, 27 Apr 2022 11:12:23 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:21 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 13/15] clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 Date: Wed, 27 Apr 2022 11:09:48 +0800 Message-ID: <20220427030950.23395-14-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The infra_ao reset is needed for MT8192 and MT8195. - Add mtk_clk_rst_desc for MT8192 and MT8195. - Add register reset controller function for MT8192 infra_ao. - Move definition of infra reset from cl-mt8183.c to reset.h because it's the same definition with MT8192 and MT8195. - Add new definition of infra reset_4 for MT8192 and MT8195. Signed-off-by: Rex-BC Chen --- drivers/clk/mediatek/clk-mt8183.c | 6 ------ drivers/clk/mediatek/clk-mt8192.c | 18 ++++++++++++++++++ drivers/clk/mediatek/clk-mt8195-infra_ao.c | 15 +++++++++++++++ drivers/clk/mediatek/reset.h | 7 +++++++ 4 files changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index c7d5ffacbd1d..40b53e15411d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -18,12 +18,6 @@ #include -/* Infra global controller reset set register */ -#define INFRA_RST0_SET_OFFSET 0x120 -#define INFRA_RST1_SET_OFFSET 0x130 -#define INFRA_RST2_SET_OFFSET 0x140 -#define INFRA_RST3_SET_OFFSET 0x150 - static DEFINE_SPINLOCK(mt8183_clk_lock); static const struct mtk_fixed_clk top_fixed_clks[] = { diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index ab27cd66b866..add177eb17d2 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1114,6 +1114,20 @@ static const struct mtk_gate top_clks[] = { GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), }; +static u16 infra_ao_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_ao_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), +}; + #define MT8192_PLL_FMAX (3800UL * MHZ) #define MT8192_PLL_FMIN (1500UL * MHZ) #define MT8192_INTEGER_BITS 8 @@ -1239,6 +1253,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) if (r) goto free_clk_data; + r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); + if (r) + goto free_clk_data; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 8ebe3b9415c4..4b7f21a6b93c 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -182,9 +182,24 @@ static const struct mtk_gate infra_ao_clks[] = { GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31), }; +static u16 infra_ao_rst_ofs[] = { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static struct mtk_clk_rst_desc infra_ao_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_ao_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), +}; + static const struct mtk_clk_desc infra_ao_desc = { .clks = infra_ao_clks, .num_clks = ARRAY_SIZE(infra_ao_clks), + .rst_desc = &infra_ao_rst_desc, }; static const struct of_device_id of_match_clk_mt8195_infra_ao[] = { diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 470588b82418..aebfb0ceabbe 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -11,6 +11,13 @@ #define RST_NR_PER_BANK 32 +/* Infra global controller reset set register */ +#define INFRA_RST0_SET_OFFSET 0x120 +#define INFRA_RST1_SET_OFFSET 0x130 +#define INFRA_RST2_SET_OFFSET 0x140 +#define INFRA_RST3_SET_OFFSET 0x150 +#define INFRA_RST4_SET_OFFSET 0x730 + /** * enum mtk_reset_version - Version of MediaTek clock reset controller. * @MTK_RST_SIMPLE: Use the same registers for bit set and clear. From patchwork Wed Apr 27 03:09:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D0FBC43219 for ; Wed, 27 Apr 2022 03:12:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357501AbiD0DP5 (ORCPT ); Tue, 26 Apr 2022 23:15:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357432AbiD0DPo (ORCPT ); Tue, 26 Apr 2022 23:15:44 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CB3613CD5; Tue, 26 Apr 2022 20:12:30 -0700 (PDT) X-UUID: d377541ec60c43f1a3606cb13c7a6263-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:fb67f833-c5b4-45b8-867a-22d8b6c1787b,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:5bf69bc6-85ee-4ac1-ac05-bd3f1e72e732,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: d377541ec60c43f1a3606cb13c7a6263-20220427 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 249225688; Wed, 27 Apr 2022 11:12:24 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:23 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:21 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 14/15] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Date: Wed, 27 Apr 2022 11:09:49 +0800 Message-ID: <20220427030950.23395-15-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org To support reset of infra, we add the property of #reset-cells. Signed-off-by: Rex-BC Chen --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 411feb294613..79803420d8ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -269,6 +269,7 @@ compatible = "mediatek,mt8192-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; pericfg: syscon@10003000 { From patchwork Wed Apr 27 03:09:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 12828223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8490C4167D for ; Wed, 27 Apr 2022 03:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357449AbiD0DPq (ORCPT ); Tue, 26 Apr 2022 23:15:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357417AbiD0DPk (ORCPT ); Tue, 26 Apr 2022 23:15:40 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59D3A12AAC; Tue, 26 Apr 2022 20:12:28 -0700 (PDT) X-UUID: 50b315ba0c3a4f0d8444d5f4245ccad8-20220427 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:3d699a84-c96e-4296-9868-db596b0b36fb,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:1603d42e-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 50b315ba0c3a4f0d8444d5f4245ccad8-20220427 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1804241659; Wed, 27 Apr 2022 11:12:23 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 27 Apr 2022 11:12:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 27 Apr 2022 11:12:22 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH V4 15/15] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Date: Wed, 27 Apr 2022 11:09:50 +0800 Message-ID: <20220427030950.23395-16-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220427030950.23395-1-rex-bc.chen@mediatek.com> References: <20220427030950.23395-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org We will use mediatek clock reset as infracfg_ao reset instead of ti-syscon. To support this, remove the property of ti reset and add the property of #reset-cells for mediatek clock reset. Fixes: 4c78814a1f46ac0 (arm64: dts: Add mediatek SoC mt8195 and evaluation board) Signed-off-by: Rex-BC Chen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index b57e620c2c72..8e5ac11b19f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,7 +10,6 @@ #include #include #include -#include / { compatible = "mediatek,mt8195"; @@ -295,17 +294,7 @@ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; - - infracfg_rst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ - >; - }; + #reset-cells = <1>; }; pericfg: syscon@10003000 {