From patchwork Wed Apr 27 11:18:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828654 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF5AC43217 for ; Wed, 27 Apr 2022 11:19:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232390AbiD0LWX (ORCPT ); Wed, 27 Apr 2022 07:22:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232357AbiD0LWW (ORCPT ); Wed, 27 Apr 2022 07:22:22 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5ACF237D9; Wed, 27 Apr 2022 04:19:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651058350; x=1682594350; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pPoxV/V2cLRUOWS8UFmI+RkWvMDeDK6Kj3MHYC77tqI=; b=yfd6RTHbt3ywCfjaEsWDRUHO+uwqXtUoywY4kY5E9t3awwIi5p1VVi7Z S6RAPx3B6raxjrxCPctkvBa8B2LBnrthpH3YAiQZV+ZkpmLI3GEfzHXXE gL1wibyL74Ik3z78zdXYCyekGExwWJcbZ83/Rqxb+U63LIcxqs2ftPsYQ E=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Apr 2022 04:19:10 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:10 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:09 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:07 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 1/9] dt: bindings: net: add bindings of WCN6750 for ath11k Date: Wed, 27 Apr 2022 16:48:40 +0530 Message-ID: <20220427111848.9257-2-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org WCN6750 is the WLAN chip on Qualcomm Snapdragon SoC SC7280; Though being a PCIe based solution, it is not attached to the APSS processor (Application Processor SubSystem), it is instead attached to another tiny processor called WPSS Q6 processor (Wireless Processor SubSystem) on the SC7280 MSM, where the WLAN firmware runs, and it is the WLAN firmware running on the Q6 processor which enumerates WCN6750, as a result APPS processor would never know such a device being present in the system and would not detect the WCN6750 hardware unless and otherwise WCN6750 is registered as a platform device. This is the reason behind adding WCN6750 WLAN node in the device tree. Add WCN6750 wireless driver support, its based on ath11k driver. Reviewed-by: Rob Herring Signed-off-by: Manikanta Pubbisetty --- .../bindings/net/wireless/qcom,ath11k.yaml | 361 ++++++++++++------ 1 file changed, 252 insertions(+), 109 deletions(-) diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml index cdf7b873b419..6b32caa8311c 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml @@ -20,120 +20,17 @@ properties: enum: - qcom,ipq8074-wifi - qcom,ipq6018-wifi + - qcom,wcn6750-wifi reg: maxItems: 1 interrupts: - items: - - description: misc-pulse1 interrupt events - - description: misc-latch interrupt events - - description: sw exception interrupt events - - description: watchdog interrupt events - - description: interrupt event for ring CE0 - - description: interrupt event for ring CE1 - - description: interrupt event for ring CE2 - - description: interrupt event for ring CE3 - - description: interrupt event for ring CE4 - - description: interrupt event for ring CE5 - - description: interrupt event for ring CE6 - - description: interrupt event for ring CE7 - - description: interrupt event for ring CE8 - - description: interrupt event for ring CE9 - - description: interrupt event for ring CE10 - - description: interrupt event for ring CE11 - - description: interrupt event for ring host2wbm-desc-feed - - description: interrupt event for ring host2reo-re-injection - - description: interrupt event for ring host2reo-command - - description: interrupt event for ring host2rxdma-monitor-ring3 - - description: interrupt event for ring host2rxdma-monitor-ring2 - - description: interrupt event for ring host2rxdma-monitor-ring1 - - description: interrupt event for ring reo2ost-exception - - description: interrupt event for ring wbm2host-rx-release - - description: interrupt event for ring reo2host-status - - description: interrupt event for ring reo2host-destination-ring4 - - description: interrupt event for ring reo2host-destination-ring3 - - description: interrupt event for ring reo2host-destination-ring2 - - description: interrupt event for ring reo2host-destination-ring1 - - description: interrupt event for ring rxdma2host-monitor-destination-mac3 - - description: interrupt event for ring rxdma2host-monitor-destination-mac2 - - description: interrupt event for ring rxdma2host-monitor-destination-mac1 - - description: interrupt event for ring ppdu-end-interrupts-mac3 - - description: interrupt event for ring ppdu-end-interrupts-mac2 - - description: interrupt event for ring ppdu-end-interrupts-mac1 - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3 - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2 - - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1 - - description: interrupt event for ring host2rxdma-host-buf-ring-mac3 - - description: interrupt event for ring host2rxdma-host-buf-ring-mac2 - - description: interrupt event for ring host2rxdma-host-buf-ring-mac1 - - description: interrupt event for ring rxdma2host-destination-ring-mac3 - - description: interrupt event for ring rxdma2host-destination-ring-mac2 - - description: interrupt event for ring rxdma2host-destination-ring-mac1 - - description: interrupt event for ring host2tcl-input-ring4 - - description: interrupt event for ring host2tcl-input-ring3 - - description: interrupt event for ring host2tcl-input-ring2 - - description: interrupt event for ring host2tcl-input-ring1 - - description: interrupt event for ring wbm2host-tx-completions-ring3 - - description: interrupt event for ring wbm2host-tx-completions-ring2 - - description: interrupt event for ring wbm2host-tx-completions-ring1 - - description: interrupt event for ring tcl2host-status-ring - + minItems: 32 + maxItems: 52 interrupt-names: - items: - - const: misc-pulse1 - - const: misc-latch - - const: sw-exception - - const: watchdog - - const: ce0 - - const: ce1 - - const: ce2 - - const: ce3 - - const: ce4 - - const: ce5 - - const: ce6 - - const: ce7 - - const: ce8 - - const: ce9 - - const: ce10 - - const: ce11 - - const: host2wbm-desc-feed - - const: host2reo-re-injection - - const: host2reo-command - - const: host2rxdma-monitor-ring3 - - const: host2rxdma-monitor-ring2 - - const: host2rxdma-monitor-ring1 - - const: reo2ost-exception - - const: wbm2host-rx-release - - const: reo2host-status - - const: reo2host-destination-ring4 - - const: reo2host-destination-ring3 - - const: reo2host-destination-ring2 - - const: reo2host-destination-ring1 - - const: rxdma2host-monitor-destination-mac3 - - const: rxdma2host-monitor-destination-mac2 - - const: rxdma2host-monitor-destination-mac1 - - const: ppdu-end-interrupts-mac3 - - const: ppdu-end-interrupts-mac2 - - const: ppdu-end-interrupts-mac1 - - const: rxdma2host-monitor-status-ring-mac3 - - const: rxdma2host-monitor-status-ring-mac2 - - const: rxdma2host-monitor-status-ring-mac1 - - const: host2rxdma-host-buf-ring-mac3 - - const: host2rxdma-host-buf-ring-mac2 - - const: host2rxdma-host-buf-ring-mac1 - - const: rxdma2host-destination-ring-mac3 - - const: rxdma2host-destination-ring-mac2 - - const: rxdma2host-destination-ring-mac1 - - const: host2tcl-input-ring4 - - const: host2tcl-input-ring3 - - const: host2tcl-input-ring2 - - const: host2tcl-input-ring1 - - const: wbm2host-tx-completions-ring3 - - const: wbm2host-tx-completions-ring2 - - const: wbm2host-tx-completions-ring1 - - const: tcl2host-status-ring + maxItems: 52 qcom,rproc: $ref: /schemas/types.yaml#/definitions/phandle @@ -151,20 +48,205 @@ properties: board-2.bin for designs with colliding bus and device specific ids memory-region: - maxItems: 1 + minItems: 1 + maxItems: 2 description: phandle to a node describing reserved memory (System RAM memory) used by ath11k firmware (see bindings/reserved-memory/reserved-memory.txt) + iommus: + minItems: 1 + maxItems: 2 + + wifi-firmware: + type: object + description: | + WCN6750 wifi node can contain one optional firmware subnode. + Firmware subnode is needed when the platform does not have Trustzone. + required: + - iommus + required: - compatible - reg - interrupts - - interrupt-names - qcom,rproc additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-wifi + - qcom,ipq6018-wifi + then: + properties: + interrupts: + items: + - description: misc-pulse1 interrupt events + - description: misc-latch interrupt events + - description: sw exception interrupt events + - description: watchdog interrupt events + - description: interrupt event for ring CE0 + - description: interrupt event for ring CE1 + - description: interrupt event for ring CE2 + - description: interrupt event for ring CE3 + - description: interrupt event for ring CE4 + - description: interrupt event for ring CE5 + - description: interrupt event for ring CE6 + - description: interrupt event for ring CE7 + - description: interrupt event for ring CE8 + - description: interrupt event for ring CE9 + - description: interrupt event for ring CE10 + - description: interrupt event for ring CE11 + - description: interrupt event for ring host2wbm-desc-feed + - description: interrupt event for ring host2reo-re-injection + - description: interrupt event for ring host2reo-command + - description: interrupt event for ring host2rxdma-monitor-ring3 + - description: interrupt event for ring host2rxdma-monitor-ring2 + - description: interrupt event for ring host2rxdma-monitor-ring1 + - description: interrupt event for ring reo2ost-exception + - description: interrupt event for ring wbm2host-rx-release + - description: interrupt event for ring reo2host-status + - description: interrupt event for ring reo2host-destination-ring4 + - description: interrupt event for ring reo2host-destination-ring3 + - description: interrupt event for ring reo2host-destination-ring2 + - description: interrupt event for ring reo2host-destination-ring1 + - description: interrupt event for ring rxdma2host-monitor-destination-mac3 + - description: interrupt event for ring rxdma2host-monitor-destination-mac2 + - description: interrupt event for ring rxdma2host-monitor-destination-mac1 + - description: interrupt event for ring ppdu-end-interrupts-mac3 + - description: interrupt event for ring ppdu-end-interrupts-mac2 + - description: interrupt event for ring ppdu-end-interrupts-mac1 + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3 + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2 + - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac3 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac2 + - description: interrupt event for ring host2rxdma-host-buf-ring-mac1 + - description: interrupt event for ring rxdma2host-destination-ring-mac3 + - description: interrupt event for ring rxdma2host-destination-ring-mac2 + - description: interrupt event for ring rxdma2host-destination-ring-mac1 + - description: interrupt event for ring host2tcl-input-ring4 + - description: interrupt event for ring host2tcl-input-ring3 + - description: interrupt event for ring host2tcl-input-ring2 + - description: interrupt event for ring host2tcl-input-ring1 + - description: interrupt event for ring wbm2host-tx-completions-ring3 + - description: interrupt event for ring wbm2host-tx-completions-ring2 + - description: interrupt event for ring wbm2host-tx-completions-ring1 + - description: interrupt event for ring tcl2host-status-ring + interrupt-names: + items: + - const: misc-pulse1 + - const: misc-latch + - const: sw-exception + - const: watchdog + - const: ce0 + - const: ce1 + - const: ce2 + - const: ce3 + - const: ce4 + - const: ce5 + - const: ce6 + - const: ce7 + - const: ce8 + - const: ce9 + - const: ce10 + - const: ce11 + - const: host2wbm-desc-feed + - const: host2reo-re-injection + - const: host2reo-command + - const: host2rxdma-monitor-ring3 + - const: host2rxdma-monitor-ring2 + - const: host2rxdma-monitor-ring1 + - const: reo2ost-exception + - const: wbm2host-rx-release + - const: reo2host-status + - const: reo2host-destination-ring4 + - const: reo2host-destination-ring3 + - const: reo2host-destination-ring2 + - const: reo2host-destination-ring1 + - const: rxdma2host-monitor-destination-mac3 + - const: rxdma2host-monitor-destination-mac2 + - const: rxdma2host-monitor-destination-mac1 + - const: ppdu-end-interrupts-mac3 + - const: ppdu-end-interrupts-mac2 + - const: ppdu-end-interrupts-mac1 + - const: rxdma2host-monitor-status-ring-mac3 + - const: rxdma2host-monitor-status-ring-mac2 + - const: rxdma2host-monitor-status-ring-mac1 + - const: host2rxdma-host-buf-ring-mac3 + - const: host2rxdma-host-buf-ring-mac2 + - const: host2rxdma-host-buf-ring-mac1 + - const: rxdma2host-destination-ring-mac3 + - const: rxdma2host-destination-ring-mac2 + - const: rxdma2host-destination-ring-mac1 + - const: host2tcl-input-ring4 + - const: host2tcl-input-ring3 + - const: host2tcl-input-ring2 + - const: host2tcl-input-ring1 + - const: wbm2host-tx-completions-ring3 + - const: wbm2host-tx-completions-ring2 + - const: wbm2host-tx-completions-ring1 + - const: tcl2host-status-ring + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-wifi + - qcom,ipq6018-wifi + then: + required: + - interrupt-names + + - if: + properties: + compatible: + contains: + enum: + - qcom,wcn6750-wifi + then: + properties: + interrupts: + items: + - description: interrupt event for ring CE1 + - description: interrupt event for ring CE2 + - description: interrupt event for ring CE3 + - description: interrupt event for ring CE4 + - description: interrupt event for ring CE5 + - description: interrupt event for ring CE6 + - description: interrupt event for ring CE7 + - description: interrupt event for ring CE8 + - description: interrupt event for ring CE9 + - description: interrupt event for ring CE10 + - description: interrupt event for ring DP1 + - description: interrupt event for ring DP2 + - description: interrupt event for ring DP3 + - description: interrupt event for ring DP4 + - description: interrupt event for ring DP5 + - description: interrupt event for ring DP6 + - description: interrupt event for ring DP7 + - description: interrupt event for ring DP8 + - description: interrupt event for ring DP9 + - description: interrupt event for ring DP10 + - description: interrupt event for ring DP11 + - description: interrupt event for ring DP12 + - description: interrupt event for ring DP13 + - description: interrupt event for ring DP14 + - description: interrupt event for ring DP15 + - description: interrupt event for ring DP16 + - description: interrupt event for ring DP17 + - description: interrupt event for ring DP18 + - description: interrupt event for ring DP19 + - description: interrupt event for ring DP20 + - description: interrupt event for ring DP21 + - description: interrupt event for ring DP22 + examples: - | @@ -309,3 +391,64 @@ examples: }; }; }; + + - | + #include + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + wlan_ce_mem: memory@4cd000 { + no-map; + reg = <0x0 0x004cd000 0x0 0x1000>; + }; + + wlan_fw_mem: memory@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0xc00000>; + }; + }; + + wifi: wifi@17a10040 { + compatible = "qcom,wcn6750-wifi"; + reg = <0x17a10040 0x0>; + iommus = <&apps_smmu 0x1c00 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,rproc = <&remoteproc_wpss>; + memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; + wifi-firmware { + iommus = <&apps_smmu 0x1c02 0x1>; + }; + }; From patchwork Wed Apr 27 11:18:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828655 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08A55C433F5 for ; Wed, 27 Apr 2022 11:19:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232405AbiD0LWZ (ORCPT ); Wed, 27 Apr 2022 07:22:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232357AbiD0LWX (ORCPT ); Wed, 27 Apr 2022 07:22:23 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4ED832E692; Wed, 27 Apr 2022 04:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651058353; x=1682594353; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mjVazpQFKDyA+YjbJj9K/J/xsHPSwdqRoyb/2895IyA=; b=sOZHu2xxhREWPYTVCd7Ib2p+PB1AP7mOulmfrflCBdRHnd0dCTo7rGu9 DlRq7aYsRcbcCJfO4PBrrzRic207zdhBKA71OSWP9it1BxnuqoJvNP+MD K8r0noJZtTHffAtub5/9CRq92NR5uyKE7ZXkwMoJpJ8IeidJ35BOBxYYe s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 27 Apr 2022 04:19:13 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:13 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:12 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:09 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 2/9] ath11k: Add HW params for WCN6750 Date: Wed, 27 Apr 2022 16:48:41 +0530 Message-ID: <20220427111848.9257-3-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Add HW params for WCN6750. It is similar to the HW params of QCA6390 with few differences wrt DP APIs and register offsets. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/core.c | 62 ++++++++++++++++++++++++++ drivers/net/wireless/ath/ath11k/core.h | 1 + drivers/net/wireless/ath/ath11k/qmi.h | 2 + 3 files changed, 65 insertions(+) diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c index 7e074b7716e7..c626d5273be6 100644 --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -433,6 +433,68 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .global_reset = true, .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, }, + { + .name = "wcn6750 hw1.0", + .hw_rev = ATH11K_HW_WCN6750_HW10, + .fw = { + .dir = "WCN6750/hw1.0", + .board_size = 256 * 1024, + .cal_offset = 128 * 1024, + }, + .max_radios = 1, + .bdf_addr = 0x4B0C0000, + .ring_mask = &ath11k_hw_ring_mask_qca6390, + .internal_sleep_clock = false, + .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, + .host_ce_config = ath11k_host_ce_config_qca6390, + .ce_count = 9, + .target_ce_config = ath11k_target_ce_config_wlan_qca6390, + .target_ce_count = 9, + .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, + .svc_to_ce_map_len = 14, + .rfkill_pin = 0, + .rfkill_cfg = 0, + .rfkill_on_level = 0, + .single_pdev_only = true, + .rxdma1_enable = false, + .num_rxmda_per_pdev = 1, + .rx_mac_buf_ring = true, + .vdev_start_delay = true, + .htt_peer_map_v2 = false, + + .spectral = { + .fft_sz = 0, + .fft_pad_sz = 0, + .summary_pad_sz = 0, + .fft_hdr_len = 0, + .max_fft_bins = 0, + }, + + .interface_modes = BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_AP), + .supports_monitor = false, + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, + .cold_boot_calib = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, + .num_peers = 512, + .supports_suspend = false, + .supports_regdb = true, + .fix_l1ss = false, + .credit_flow = true, + .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, + .hal_params = &ath11k_hw_hal_params_qca6390, + .supports_dynamic_smps_6ghz = false, + .alloc_cacheable_memory = false, + .supports_rssi_stats = true, + .fw_wmi_diag_event = false, + .current_cc_support = true, + .dbr_debug_support = false, + .global_reset = false, + .bios_sar_capa = NULL, + }, }; static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h index 7a505531acf9..8f775cdd0b93 100644 --- a/drivers/net/wireless/ath/ath11k/core.h +++ b/drivers/net/wireless/ath/ath11k/core.h @@ -140,6 +140,7 @@ enum ath11k_hw_rev { ATH11K_HW_QCN9074_HW10, ATH11K_HW_WCN6855_HW20, ATH11K_HW_WCN6855_HW21, + ATH11K_HW_WCN6750_HW10, }; enum ath11k_firmware_mode { diff --git a/drivers/net/wireless/ath/ath11k/qmi.h b/drivers/net/wireless/ath/ath11k/qmi.h index 61678de56ac7..872646c3b3ed 100644 --- a/drivers/net/wireless/ath/ath11k/qmi.h +++ b/drivers/net/wireless/ath/ath11k/qmi.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH11K_QMI_H @@ -20,6 +21,7 @@ #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 +#define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 #define ATH11K_QMI_RESP_LEN_MAX 8192 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 From patchwork Wed Apr 27 11:18:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828656 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24E05C4332F for ; Wed, 27 Apr 2022 11:19:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232428AbiD0LW1 (ORCPT ); Wed, 27 Apr 2022 07:22:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232426AbiD0LW0 (ORCPT ); Wed, 27 Apr 2022 07:22:26 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D4A02E9F6; Wed, 27 Apr 2022 04:19:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651058356; x=1682594356; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YHUI8It2Nca0K7+UnVYz8KwyL5zVLLx9r/4p/ptVvsc=; b=ZvYDV1MBHlYdZBbAHHs3w5Y/bt5wnr/GXwuu6vQo1IMC6DQblKx0sCVJ Qs+5aq+m8/Aolpqq+/7kpIXs4mKRjbM2blVchwndPowew9czfL8NZ+1/B HtpFYMAloxJLIZraecoYDiPhpHmzUaqoonXWPlKryBWtnueSw408aIVmn Y=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Apr 2022 04:19:15 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:15 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:15 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:12 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 3/9] ath11k: Add bus params for WCN6750 Date: Wed, 27 Apr 2022 16:48:42 +0530 Message-ID: <20220427111848.9257-4-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org WCN6750 is a PCIe based solution that is attached to and enumerated by the WPSS (Wireless Processor SubSystem) Q6 processor. Though it is a PCIe device, since it is not attached to APSS processor (Application Processor SubSystem), APSS will be unaware of such a decice and hence it is registered to the APSS processor as a platform device(AHB). Because of this hybrid nature, it is called as a hybrid bus device. A new variable is defined in bus params to indicate the hybrid nature. Add bus params for WCN6750. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/ahb.c | 10 ++++++++++ drivers/net/wireless/ath/ath11k/ahb.h | 2 ++ drivers/net/wireless/ath/ath11k/core.h | 1 + drivers/net/wireless/ath/ath11k/pci.c | 1 + 4 files changed, 14 insertions(+) diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c index f407d4af2074..cfdd415f0203 100644 --- a/drivers/net/wireless/ath/ath11k/ahb.c +++ b/drivers/net/wireless/ath/ath11k/ahb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -33,6 +34,15 @@ static const struct ath11k_bus_params ath11k_ahb_bus_params = { .m3_fw_support = false, .fixed_bdf_addr = true, .fixed_mem_region = true, + .hybrid_bus_type = false, +}; + +const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = { + .mhi_support = false, + .m3_fw_support = false, + .fixed_bdf_addr = false, + .fixed_mem_region = false, + .hybrid_bus_type = true, }; #define ATH11K_IRQ_CE0_OFFSET 4 diff --git a/drivers/net/wireless/ath/ath11k/ahb.h b/drivers/net/wireless/ath/ath11k/ahb.h index 51e6e4a5f686..a276e3d1dff8 100644 --- a/drivers/net/wireless/ath/ath11k/ahb.h +++ b/drivers/net/wireless/ath/ath11k/ahb.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH11K_AHB_H #define ATH11K_AHB_H @@ -9,6 +10,7 @@ #define ATH11K_AHB_RECOVERY_TIMEOUT (3 * HZ) struct ath11k_base; +extern const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params; struct ath11k_ahb { struct rproc *tgt_rproc; diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h index 8f775cdd0b93..51f313dd7f26 100644 --- a/drivers/net/wireless/ath/ath11k/core.h +++ b/drivers/net/wireless/ath/ath11k/core.h @@ -755,6 +755,7 @@ struct ath11k_bus_params { bool fixed_bdf_addr; bool fixed_mem_region; bool static_window_map; + bool hybrid_bus_type; }; struct ath11k_pci_ops { diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c index 024661a17008..ddd1e2de6a2e 100644 --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c @@ -120,6 +120,7 @@ static const struct ath11k_bus_params ath11k_pci_bus_params = { .m3_fw_support = true, .fixed_bdf_addr = false, .fixed_mem_region = false, + .hybrid_bus_type = false, }; static const struct ath11k_msi_config msi_config_one_msi = { From patchwork Wed Apr 27 11:18:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828657 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 416CCC433FE for ; Wed, 27 Apr 2022 11:19:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232441AbiD0LWb (ORCPT ); Wed, 27 Apr 2022 07:22:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232433AbiD0LWb (ORCPT ); Wed, 27 Apr 2022 07:22:31 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C90282ED5C; Wed, 27 Apr 2022 04:19:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651058359; x=1682594359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UJ0NNaQXSE+E91PQwsCcFnAiv2y9/HGUuqGhd91HhtQ=; b=d9QR6YYHH4zUFaZ4qx+gETHvbkJLAXxubPbLPnVgBKF6OCiQL1GjSwDG p2A8AS+jdSIi0LaVdbmNDSQV7daDDv3zqKJNiNqQZ/itZg2QKKKZHBQid F682fiHEWpme7CsXRlmFahxi2QAT8DkJtRVcGLsGSH5+6d87KlOUnKuo5 s=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 27 Apr 2022 04:19:19 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:19 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:17 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:15 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 4/9] ath11k: Add register access logic for WCN6750 Date: Wed, 27 Apr 2022 16:48:43 +0530 Message-ID: <20220427111848.9257-5-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org WCN6750 uses static window mapping to access the HW registers. Unlike QCN9074 which uses 2nd window for CE and 3rd window for UMAC register accesses, WCN6750 uses 1st window for UMAC and 2nd window for CE registers. Code is refactored so that WCN6750 can use the existing ath11k_pci_read/write() APIs for accessing the registers. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/ahb.c | 6 +++ drivers/net/wireless/ath/ath11k/core.h | 2 + drivers/net/wireless/ath/ath11k/pci.c | 34 ++++++++++++++-- drivers/net/wireless/ath/ath11k/pcic.c | 54 +++++++++----------------- 4 files changed, 58 insertions(+), 38 deletions(-) diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c index cfdd415f0203..fa12e50f32f4 100644 --- a/drivers/net/wireless/ath/ath11k/ahb.c +++ b/drivers/net/wireless/ath/ath11k/ahb.c @@ -34,7 +34,10 @@ static const struct ath11k_bus_params ath11k_ahb_bus_params = { .m3_fw_support = false, .fixed_bdf_addr = true, .fixed_mem_region = true, + .static_window_map = false, .hybrid_bus_type = false, + .dp_window_idx = 0, + .ce_window_idx = 0, }; const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = { @@ -42,7 +45,10 @@ const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = { .m3_fw_support = false, .fixed_bdf_addr = false, .fixed_mem_region = false, + .static_window_map = true, .hybrid_bus_type = true, + .dp_window_idx = 1, + .ce_window_idx = 2, }; #define ATH11K_IRQ_CE0_OFFSET 4 diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h index 51f313dd7f26..ee0ad93d5843 100644 --- a/drivers/net/wireless/ath/ath11k/core.h +++ b/drivers/net/wireless/ath/ath11k/core.h @@ -756,6 +756,8 @@ struct ath11k_bus_params { bool fixed_mem_region; bool static_window_map; bool hybrid_bus_type; + u8 dp_window_idx; + u8 ce_window_idx; }; struct ath11k_pci_ops { diff --git a/drivers/net/wireless/ath/ath11k/pci.c b/drivers/net/wireless/ath/ath11k/pci.c index ddd1e2de6a2e..9184cb893bd4 100644 --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c @@ -115,12 +115,26 @@ static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = { .window_read32 = ath11k_pci_window_read32, }; -static const struct ath11k_bus_params ath11k_pci_bus_params = { +static const struct ath11k_bus_params ath11k_pci_bus_params_qca6390 = { .mhi_support = true, .m3_fw_support = true, .fixed_bdf_addr = false, .fixed_mem_region = false, + .static_window_map = false, .hybrid_bus_type = false, + .dp_window_idx = 0, + .ce_window_idx = 0, +}; + +static const struct ath11k_bus_params ath11k_pci_bus_params_qcn9074 = { + .mhi_support = true, + .m3_fw_support = true, + .fixed_bdf_addr = false, + .fixed_mem_region = false, + .static_window_map = true, + .hybrid_bus_type = false, + .dp_window_idx = 3, + .ce_window_idx = 2, }; static const struct ath11k_msi_config msi_config_one_msi = { @@ -704,11 +718,26 @@ static int ath11k_pci_probe(struct pci_dev *pdev, { struct ath11k_base *ab; struct ath11k_pci *ab_pci; + const struct ath11k_bus_params *bus_params; u32 soc_hw_version_major, soc_hw_version_minor, addr; int ret; + switch (pci_dev->device) { + case QCA6390_DEVICE_ID: + case WCN6855_DEVICE_ID: + bus_params = &ath11k_pci_bus_params_qca6390; + break; + case QCN9074_DEVICE_ID: + bus_params = &ath11k_pci_bus_params_qcn9074; + break; + default: + dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", + pci_dev->device); + return -EOPNOTSUPP; + } + ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI, - &ath11k_pci_bus_params); + bus_params); if (!ab) { dev_err(&pdev->dev, "failed to allocate ath11k base\n"); return -ENOMEM; @@ -765,7 +794,6 @@ static int ath11k_pci_probe(struct pci_dev *pdev, ab->pci.ops = &ath11k_pci_ops_qca6390; break; case QCN9074_DEVICE_ID: - ab->bus_params.static_window_map = true; ab->pci.ops = &ath11k_pci_ops_qcn9074; ab->hw_rev = ATH11K_HW_QCN9074_HW10; break; diff --git a/drivers/net/wireless/ath/ath11k/pcic.c b/drivers/net/wireless/ath/ath11k/pcic.c index 63c678aea29e..d79433e20181 100644 --- a/drivers/net/wireless/ath/ath11k/pcic.c +++ b/drivers/net/wireless/ath/ath11k/pcic.c @@ -134,16 +134,13 @@ EXPORT_SYMBOL(ath11k_pcic_init_msi_config); static inline u32 ath11k_pcic_get_window_start(struct ath11k_base *ab, u32 offset) { - u32 window_start; + u32 window_start = 0; - /* If offset lies within DP register range, use 3rd window */ if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) - window_start = 3 * ATH11K_PCI_WINDOW_START; - /* If offset lies within CE register range, use 2nd window */ - else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < ATH11K_PCI_WINDOW_RANGE_MASK) - window_start = 2 * ATH11K_PCI_WINDOW_START; - else - window_start = ATH11K_PCI_WINDOW_START; + window_start = ab->bus_params.dp_window_idx * ATH11K_PCI_WINDOW_START; + else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < + ATH11K_PCI_WINDOW_RANGE_MASK) + window_start = ab->bus_params.ce_window_idx * ATH11K_PCI_WINDOW_START; return window_start; } @@ -162,19 +159,12 @@ void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value) if (offset < ATH11K_PCI_WINDOW_START) { iowrite32(value, ab->mem + offset); - } else { - if (ab->bus_params.static_window_map) - window_start = ath11k_pcic_get_window_start(ab, offset); - else - window_start = ATH11K_PCI_WINDOW_START; - - if (window_start == ATH11K_PCI_WINDOW_START && - ab->pci.ops->window_write32) { - ab->pci.ops->window_write32(ab, offset, value); - } else { - iowrite32(value, ab->mem + window_start + - (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); - } + } else if (ab->bus_params.static_window_map) { + window_start = ath11k_pcic_get_window_start(ab, offset); + iowrite32(value, ab->mem + window_start + + (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); + } else if (ab->pci.ops->window_write32) { + ab->pci.ops->window_write32(ab, offset, value); } if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && @@ -185,7 +175,8 @@ void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value) u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset) { - u32 val, window_start; + u32 val = 0; + u32 window_start; int ret = 0; /* for offset beyond BAR + 4K - 32, may @@ -197,19 +188,12 @@ u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset) if (offset < ATH11K_PCI_WINDOW_START) { val = ioread32(ab->mem + offset); - } else { - if (ab->bus_params.static_window_map) - window_start = ath11k_pcic_get_window_start(ab, offset); - else - window_start = ATH11K_PCI_WINDOW_START; - - if (window_start == ATH11K_PCI_WINDOW_START && - ab->pci.ops->window_read32) { - val = ab->pci.ops->window_read32(ab, offset); - } else { - val = ioread32(ab->mem + window_start + - (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); - } + } else if (ab->bus_params.static_window_map) { + window_start = ath11k_pcic_get_window_start(ab, offset); + val = ioread32(ab->mem + window_start + + (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); + } else if (ab->pci.ops->window_read32) { + val = ab->pci.ops->window_read32(ab, offset); } if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && From patchwork Wed Apr 27 11:18:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828658 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B369C43217 for ; Wed, 27 Apr 2022 11:19:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232452AbiD0LWd (ORCPT ); Wed, 27 Apr 2022 07:22:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232433AbiD0LWc (ORCPT ); Wed, 27 Apr 2022 07:22:32 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 183772ED69; Wed, 27 Apr 2022 04:19:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651058361; x=1682594361; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/AXtOuRa8oelXWybdr3yw1r2OhGKxYqOekMawY2GmFw=; b=TidZ3nPLZjnJC3C28x6k+FAhhrll0n4biz7Pn9Vv9JK+8aUEyseEXzPc Z//iRNSYBuGg3ExNad0jA718KVJY4GhvMLyuAxkeOygxGq1NsI+YKdikF nkjcQZ9lcEg0JIwX9eZt1o/FaaPIZIbRZAkK9Wfw7fdLQDMajK0hwNJ/g U=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Apr 2022 04:19:20 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:20 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:20 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:17 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 5/9] ath11k: Fetch device information via QMI for WCN6750 Date: Wed, 27 Apr 2022 16:48:44 +0530 Message-ID: <20220427111848.9257-6-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Since WPPS Q6 does the PCIe enumeration of WCN6750, device information like BAR and BAR size is not known to the APPS processor (Application Processor SubSystem). In order to fetch these details, a QMI message called device info request will be sent to the target. Therefore, add logic to fetch BAR details from the target. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/qmi.c | 144 ++++++++++++++++++++++++++ drivers/net/wireless/ath/ath11k/qmi.h | 24 ++++- 2 files changed, 164 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/ath/ath11k/qmi.c b/drivers/net/wireless/ath/ath11k/qmi.c index 0442faa3b7af..df49f8b68556 100644 --- a/drivers/net/wireless/ath/ath11k/qmi.c +++ b/drivers/net/wireless/ath/ath11k/qmi.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -12,6 +13,8 @@ #include #include #include +#include +#include #define SLEEP_CLOCK_SELECT_INTERNAL_BIT 0x02 #define HOST_CSTATE_BIT 0x04 @@ -748,6 +751,68 @@ static struct qmi_elem_info qmi_wlanfw_cap_req_msg_v01_ei[] = { }, }; +static struct qmi_elem_info qmi_wlanfw_device_info_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlfw_device_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + static struct qmi_elem_info qmi_wlanfw_rf_chip_info_s_v01_ei[] = { { .data_type = QMI_UNSIGNED_4_BYTE, @@ -2007,6 +2072,79 @@ static int ath11k_qmi_assign_target_mem_chunk(struct ath11k_base *ab) return 0; } +static int ath11k_qmi_request_device_info(struct ath11k_base *ab) +{ + struct qmi_wlanfw_device_info_req_msg_v01 req = {}; + struct qmi_wlanfw_device_info_resp_msg_v01 resp = {}; + struct qmi_txn txn; + void __iomem *bar_addr_va; + int ret; + + /* device info message req is only sent for hybrid bus devices */ + if (!ab->bus_params.hybrid_bus_type) + return 0; + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlfw_device_info_resp_msg_v01_ei, &resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_DEVICE_INFO_REQ_V01, + QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN, + qmi_wlanfw_device_info_req_msg_v01_ei, &req); + if (ret < 0) { + qmi_txn_cancel(&txn); + ath11k_warn(ab, "qmi failed to send target device info request, err = %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH11K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) { + ath11k_warn(ab, "qmi failed target device info request %d\n", ret); + goto out; + } + + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ath11k_warn(ab, "qmi device info req failed, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } + + if (!resp.bar_addr_valid || !resp.bar_size_valid) { + ath11k_warn(ab, "qmi device info response invalid, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } + + if (!resp.bar_addr || + resp.bar_size != ATH11K_QMI_DEVICE_BAR_SIZE) { + ath11k_warn(ab, "qmi device info invalid addr and size, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } + + bar_addr_va = devm_ioremap(ab->dev, resp.bar_addr, resp.bar_size); + + if (!bar_addr_va) { + ath11k_warn(ab, "qmi device info ioremap failed\n"); + ab->mem_len = 0; + ret = -EIO; + goto out; + } + + ab->mem = bar_addr_va; + ab->mem_len = resp.bar_size; + + return 0; +out: + return ret; +} + static int ath11k_qmi_request_target_cap(struct ath11k_base *ab) { struct qmi_wlanfw_cap_req_msg_v01 req; @@ -2748,6 +2886,12 @@ static int ath11k_qmi_event_load_bdf(struct ath11k_qmi *qmi) return ret; } + ret = ath11k_qmi_request_device_info(ab); + if (ret < 0) { + ath11k_warn(ab, "failed to request qmi device info %d\n", ret); + return ret; + } + if (ab->hw_params.supports_regdb) ath11k_qmi_load_bdf_qmi(ab, true); diff --git a/drivers/net/wireless/ath/ath11k/qmi.h b/drivers/net/wireless/ath/ath11k/qmi.h index 872646c3b3ed..445b6bd34eb5 100644 --- a/drivers/net/wireless/ath/ath11k/qmi.h +++ b/drivers/net/wireless/ath/ath11k/qmi.h @@ -38,6 +38,8 @@ #define ATH11K_FIRMWARE_MODE_OFF 4 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) +#define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 + struct ath11k_base; enum ath11k_qmi_file_type { @@ -287,10 +289,12 @@ struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { char placeholder; }; -#define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 -#define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 -#define QMI_WLANFW_CAP_REQ_V01 0x0024 -#define QMI_WLANFW_CAP_RESP_V01 0x0024 +#define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 +#define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 +#define QMI_WLANFW_CAP_REQ_V01 0x0024 +#define QMI_WLANFW_CAP_RESP_V01 0x0024 +#define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C +#define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 enum qmi_wlanfw_pipedir_enum_v01 { QMI_WLFW_PIPEDIR_NONE_V01 = 0, @@ -383,6 +387,18 @@ struct qmi_wlanfw_cap_req_msg_v01 { char placeholder; }; +struct qmi_wlanfw_device_info_req_msg_v01 { + char placeholder; +}; + +struct qmi_wlanfw_device_info_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u64 bar_addr; + u32 bar_size; + u8 bar_addr_valid; + u8 bar_size_valid; +}; + #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 From patchwork Wed Apr 27 11:18:45 2022 Content-Type: text/plain; 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Wed, 27 Apr 2022 04:19:20 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 6/9] ath11k: Add QMI changes for WCN6750 Date: Wed, 27 Apr 2022 16:48:45 +0530 Message-ID: <20220427111848.9257-7-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org In the case of WCN6750, FW doesn't request for DDR memory via QMI, instead it uses a fixed 12MB reserved Memory region in the DDR which is called as MSA region. As a result, QMI message sequence is not same as other ath11k supported devices. Also, M3 firmware will be bundled into the FW and will be downloaded to the target as part of Q6 boot. This is the QMI flow in the case of WCN6750, 1) QMI firmware indication REQ/RESP 2) QMI host capability REQ/RESP 3) QMI target capability REQ/RESP 4) QMI device info REQ/RESP 5) QMI BDF download 6) QMI FW ready Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/core.c | 7 +++ drivers/net/wireless/ath/ath11k/hw.h | 1 + drivers/net/wireless/ath/ath11k/qmi.c | 76 ++++++++++++++++---------- 3 files changed, 56 insertions(+), 28 deletions(-) diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c index c626d5273be6..41f4125d104a 100644 --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -102,6 +102,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .dbr_debug_support = true, .global_reset = false, .bios_sar_capa = NULL, + .fixed_fw_mem = false, }, { .hw_rev = ATH11K_HW_IPQ6018_HW10, @@ -169,6 +170,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .dbr_debug_support = true, .global_reset = false, .bios_sar_capa = NULL, + .fixed_fw_mem = false, }, { .name = "qca6390 hw2.0", @@ -235,6 +237,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .dbr_debug_support = false, .global_reset = true, .bios_sar_capa = NULL, + .fixed_fw_mem = false, }, { .name = "qcn9074 hw1.0", @@ -301,6 +304,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .dbr_debug_support = true, .global_reset = false, .bios_sar_capa = NULL, + .fixed_fw_mem = false, }, { .name = "wcn6855 hw2.0", @@ -367,6 +371,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .dbr_debug_support = false, .global_reset = true, .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, + .fixed_fw_mem = false, }, { .name = "wcn6855 hw2.1", @@ -432,6 +437,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .dbr_debug_support = false, .global_reset = true, .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, + .fixed_fw_mem = false, }, { .name = "wcn6750 hw1.0", @@ -494,6 +500,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .dbr_debug_support = false, .global_reset = false, .bios_sar_capa = NULL, + .fixed_fw_mem = true, }, }; diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h index b7ece3d5678c..c2ee39f977c2 100644 --- a/drivers/net/wireless/ath/ath11k/hw.h +++ b/drivers/net/wireless/ath/ath11k/hw.h @@ -196,6 +196,7 @@ struct ath11k_hw_params { bool dbr_debug_support; bool global_reset; const struct cfg80211_sar_capa *bios_sar_capa; + bool fixed_fw_mem; }; struct ath11k_hw_ops { diff --git a/drivers/net/wireless/ath/ath11k/qmi.c b/drivers/net/wireless/ath/ath11k/qmi.c index df49f8b68556..57804c152692 100644 --- a/drivers/net/wireless/ath/ath11k/qmi.c +++ b/drivers/net/wireless/ath/ath11k/qmi.c @@ -1799,10 +1799,6 @@ static int ath11k_qmi_fw_ind_register_send(struct ath11k_base *ab) req->client_id = QMI_WLANFW_CLIENT_ID; req->fw_ready_enable_valid = 1; req->fw_ready_enable = 1; - req->request_mem_enable_valid = 1; - req->request_mem_enable = 1; - req->fw_mem_ready_enable_valid = 1; - req->fw_mem_ready_enable = 1; req->cal_done_enable_valid = 1; req->cal_done_enable = 1; req->fw_init_done_enable_valid = 1; @@ -1811,6 +1807,17 @@ static int ath11k_qmi_fw_ind_register_send(struct ath11k_base *ab) req->pin_connect_result_enable_valid = 0; req->pin_connect_result_enable = 0; + /* WCN6750 doesn't request for DDR memory via QMI, + * instead it uses a fixed 12MB reserved memory + * region in DDR. + */ + if (!ab->hw_params.fixed_fw_mem) { + req->request_mem_enable_valid = 1; + req->request_mem_enable = 1; + req->fw_mem_ready_enable_valid = 1; + req->fw_mem_ready_enable = 1; + } + ret = qmi_txn_init(handle, &txn, qmi_wlanfw_ind_register_resp_msg_v01_ei, resp); if (ret < 0) @@ -2839,27 +2846,6 @@ ath11k_qmi_driver_event_post(struct ath11k_qmi *qmi, return 0; } -static int ath11k_qmi_event_server_arrive(struct ath11k_qmi *qmi) -{ - struct ath11k_base *ab = qmi->ab; - int ret; - - ret = ath11k_qmi_fw_ind_register_send(ab); - if (ret < 0) { - ath11k_warn(ab, "failed to send qmi firmware indication: %d\n", - ret); - return ret; - } - - ret = ath11k_qmi_host_cap_send(ab); - if (ret < 0) { - ath11k_warn(ab, "failed to send qmi host cap: %d\n", ret); - return ret; - } - - return ret; -} - static int ath11k_qmi_event_mem_request(struct ath11k_qmi *qmi) { struct ath11k_base *ab = qmi->ab; @@ -2901,9 +2887,33 @@ static int ath11k_qmi_event_load_bdf(struct ath11k_qmi *qmi) return ret; } - ret = ath11k_qmi_wlanfw_m3_info_send(ab); + return 0; +} + +static int ath11k_qmi_event_server_arrive(struct ath11k_qmi *qmi) +{ + struct ath11k_base *ab = qmi->ab; + int ret; + + ret = ath11k_qmi_fw_ind_register_send(ab); + if (ret < 0) { + ath11k_warn(ab, "failed to send qmi firmware indication: %d\n", + ret); + return ret; + } + + ret = ath11k_qmi_host_cap_send(ab); if (ret < 0) { - ath11k_warn(ab, "failed to send qmi m3 info req: %d\n", ret); + ath11k_warn(ab, "failed to send qmi host cap: %d\n", ret); + return ret; + } + + if (!ab->hw_params.fixed_fw_mem) + return ret; + + ret = ath11k_qmi_event_load_bdf(qmi); + if (ret < 0) { + ath11k_warn(ab, "qmi failed to download BDF:%d\n", ret); return ret; } @@ -3103,8 +3113,18 @@ static void ath11k_qmi_driver_event_work(struct work_struct *work) break; case ATH11K_QMI_EVENT_FW_MEM_READY: ret = ath11k_qmi_event_load_bdf(qmi); - if (ret < 0) + if (ret < 0) { set_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags); + break; + } + + ret = ath11k_qmi_wlanfw_m3_info_send(ab); + if (ret < 0) { + ath11k_warn(ab, + "failed to send qmi m3 info req: %d\n", ret); + set_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags); + } + break; case ATH11K_QMI_EVENT_FW_READY: clear_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags); From patchwork Wed Apr 27 11:18:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828660 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE8D5C433FE for ; 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Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 27 Apr 2022 04:19:26 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:26 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:25 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:23 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 7/9] ath11k: HAL changes to support WCN6750 Date: Wed, 27 Apr 2022 16:48:46 +0530 Message-ID: <20220427111848.9257-8-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Add HAL changes required to support WCN6750. Offsets of some registers for WCN6750 are different from other supported devices; move such register offsets to platform specific ath11k_hw_regs. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/core.c | 2 + drivers/net/wireless/ath/ath11k/hal.c | 15 +-- drivers/net/wireless/ath/ath11k/hal.h | 15 +-- drivers/net/wireless/ath/ath11k/hw.c | 134 +++++++++++++++++++++++++ drivers/net/wireless/ath/ath11k/hw.h | 10 ++ 5 files changed, 163 insertions(+), 13 deletions(-) diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c index 41f4125d104a..5ee9f1c53a89 100644 --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -449,8 +449,10 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { }, .max_radios = 1, .bdf_addr = 0x4B0C0000, + .hw_ops = &wcn6750_ops, .ring_mask = &ath11k_hw_ring_mask_qca6390, .internal_sleep_clock = false, + .regs = &wcn6750_regs, .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, .host_ce_config = ath11k_host_ce_config_qca6390, .ce_count = 9, diff --git a/drivers/net/wireless/ath/ath11k/hal.c b/drivers/net/wireless/ath/ath11k/hal.c index 2ec09ae90080..9a6340d655b7 100644 --- a/drivers/net/wireless/ath/ath11k/hal.c +++ b/drivers/net/wireless/ath/ath11k/hal.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include "hal_tx.h" @@ -1082,10 +1083,10 @@ static void ath11k_hal_srng_update_hp_tp_addr(struct ath11k_base *ab, srng = &hal->srng_list[ring_id]; if (srng_config->ring_dir == HAL_SRNG_DIR_DST) - srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + + srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) + (unsigned long)ab->mem); else - srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + + srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(ab, shadow_cfg_idx) + (unsigned long)ab->mem); } @@ -1120,7 +1121,7 @@ int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, ath11k_dbg(ab, ATH11k_DBG_HAL, "target_reg %x, shadow reg 0x%x shadow_idx 0x%x, ring_type %d, ring num %d", target_reg, - HAL_SHADOW_REG(shadow_cfg_idx), + HAL_SHADOW_REG(ab, shadow_cfg_idx), shadow_cfg_idx, ring_type, ring_num); @@ -1193,12 +1194,12 @@ static int ath11k_hal_srng_create_config(struct ath11k_base *ab) s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP(ab); s = &hal->srng_config[HAL_REO_REINJECT]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP(ab); s = &hal->srng_config[HAL_REO_CMD]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP(ab); s = &hal->srng_config[HAL_REO_STATUS]; s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h index a7d9b4c551ad..6fbda016cd63 100644 --- a/drivers/net/wireless/ath/ath11k/hal.h +++ b/drivers/net/wireless/ath/ath11k/hal.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH11K_HAL_H @@ -31,12 +32,12 @@ struct ath11k_base; #define HAL_DSCP_TID_TBL_SIZE 24 /* calculate the register address from bar0 of shadow register x */ -#define HAL_SHADOW_BASE_ADDR 0x000008fc +#define HAL_SHADOW_BASE_ADDR(ab) ab->hw_params.regs->hal_shadow_base_addr #define HAL_SHADOW_NUM_REGS 36 #define HAL_HP_OFFSET_IN_REG_START 1 #define HAL_OFFSET_FROM_HP_TO_TP 4 -#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) +#define HAL_SHADOW_REG(ab, x) (HAL_SHADOW_BASE_ADDR(ab) + (4 * (x))) /* WCSS Relative address */ #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 @@ -180,16 +181,18 @@ struct ath11k_base; #define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp /* REO CMD R0 address */ -#define HAL_REO_CMD_RING_BASE_LSB 0x00000194 +#define HAL_REO_CMD_RING_BASE_LSB(ab) \ + ab->hw_params.regs->hal_reo_cmd_ring_base_lsb /* REO CMD R2 address */ -#define HAL_REO_CMD_HP 0x00003020 +#define HAL_REO_CMD_HP(ab) ab->hw_params.regs->hal_reo_cmd_ring_hp /* SW2REO R0 address */ -#define HAL_SW2REO_RING_BASE_LSB 0x000001ec +#define HAL_SW2REO_RING_BASE_LSB(ab) \ + ab->hw_params.regs->hal_sw2reo_ring_base_lsb /* SW2REO R2 address */ -#define HAL_SW2REO_RING_HP 0x00003028 +#define HAL_SW2REO_RING_HP(ab) ab->hw_params.regs->hal_sw2reo_ring_hp /* CE ring R0 address */ #define HAL_CE_DST_RING_BASE_LSB 0x00000000 diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c index 46449a18b5cb..fc026969069c 100644 --- a/drivers/net/wireless/ath/ath11k/hw.c +++ b/drivers/net/wireless/ath/ath11k/hw.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1014,6 +1015,13 @@ const struct ath11k_hw_ops wcn6855_ops = { .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, }; +const struct ath11k_hw_ops wcn6750_ops = { + .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, + .wmi_init_config = ath11k_init_wmi_config_qca6390, + .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, + .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, +}; + #define ATH11K_TX_RING_MASK_0 0x1 #define ATH11K_TX_RING_MASK_1 0x2 #define ATH11K_TX_RING_MASK_2 0x4 @@ -1908,10 +1916,18 @@ const struct ath11k_hw_regs ipq8074_regs = { .hal_reo_tcl_ring_base_lsb = 0x000003fc, .hal_reo_tcl_ring_hp = 0x00003058, + /* REO CMD ring address */ + .hal_reo_cmd_ring_base_lsb = 0x00000194, + .hal_reo_cmd_ring_hp = 0x00003020, + /* REO status address */ .hal_reo_status_ring_base_lsb = 0x00000504, .hal_reo_status_hp = 0x00003070, + /* SW2REO ring address */ + .hal_sw2reo_ring_base_lsb = 0x000001ec, + .hal_sw2reo_ring_hp = 0x00003028, + /* WCSS relative address */ .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, @@ -1932,6 +1948,9 @@ const struct ath11k_hw_regs ipq8074_regs = { /* PCIe base address */ .pcie_qserdes_sysclk_en_sel = 0x0, .pcie_pcs_osc_dtct_config_base = 0x0, + + /* Shadow register area */ + .hal_shadow_base_addr = 0x0, }; const struct ath11k_hw_regs qca6390_regs = { @@ -1979,10 +1998,18 @@ const struct ath11k_hw_regs qca6390_regs = { .hal_reo_tcl_ring_base_lsb = 0x000003a4, .hal_reo_tcl_ring_hp = 0x00003050, + /* REO CMD ring address */ + .hal_reo_cmd_ring_base_lsb = 0x00000194, + .hal_reo_cmd_ring_hp = 0x00003020, + /* REO status address */ .hal_reo_status_ring_base_lsb = 0x000004ac, .hal_reo_status_hp = 0x00003068, + /* SW2REO ring address */ + .hal_sw2reo_ring_base_lsb = 0x000001ec, + .hal_sw2reo_ring_hp = 0x00003028, + /* WCSS relative address */ .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, @@ -2003,6 +2030,9 @@ const struct ath11k_hw_regs qca6390_regs = { /* PCIe base address */ .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, .pcie_pcs_osc_dtct_config_base = 0x01e0c628, + + /* Shadow register area */ + .hal_shadow_base_addr = 0x000008fc, }; const struct ath11k_hw_regs qcn9074_regs = { @@ -2050,10 +2080,18 @@ const struct ath11k_hw_regs qcn9074_regs = { .hal_reo_tcl_ring_base_lsb = 0x000003fc, .hal_reo_tcl_ring_hp = 0x00003058, + /* REO CMD ring address */ + .hal_reo_cmd_ring_base_lsb = 0x00000194, + .hal_reo_cmd_ring_hp = 0x00003020, + /* REO status address */ .hal_reo_status_ring_base_lsb = 0x00000504, .hal_reo_status_hp = 0x00003070, + /* SW2REO ring address */ + .hal_sw2reo_ring_base_lsb = 0x000001ec, + .hal_sw2reo_ring_hp = 0x00003028, + /* WCSS relative address */ .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, @@ -2074,6 +2112,9 @@ const struct ath11k_hw_regs qcn9074_regs = { /* PCIe base address */ .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, + + /* Shadow register area */ + .hal_shadow_base_addr = 0x0, }; const struct ath11k_hw_regs wcn6855_regs = { @@ -2121,10 +2162,18 @@ const struct ath11k_hw_regs wcn6855_regs = { .hal_reo_tcl_ring_base_lsb = 0x00000454, .hal_reo_tcl_ring_hp = 0x00003060, + /* REO CMD ring address */ + .hal_reo_cmd_ring_base_lsb = 0x00000194, + .hal_reo_cmd_ring_hp = 0x00003020, + /* REO status address */ .hal_reo_status_ring_base_lsb = 0x0000055c, .hal_reo_status_hp = 0x00003078, + /* SW2REO ring address */ + .hal_sw2reo_ring_base_lsb = 0x000001ec, + .hal_sw2reo_ring_hp = 0x00003028, + /* WCSS relative address */ .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, @@ -2145,6 +2194,91 @@ const struct ath11k_hw_regs wcn6855_regs = { /* PCIe base address */ .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, .pcie_pcs_osc_dtct_config_base = 0x01e0c628, + + /* Shadow register area */ + .hal_shadow_base_addr = 0x000008fc, +}; + +const struct ath11k_hw_regs wcn6750_regs = { + /* SW2TCL(x) R0 ring configuration address */ + .hal_tcl1_ring_base_lsb = 0x00000694, + .hal_tcl1_ring_base_msb = 0x00000698, + .hal_tcl1_ring_id = 0x0000069c, + .hal_tcl1_ring_misc = 0x000006a4, + .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, + .hal_tcl1_ring_tp_addr_msb = 0x000006b4, + .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, + .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, + .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, + .hal_tcl1_ring_msi1_base_msb = 0x000006e0, + .hal_tcl1_ring_msi1_data = 0x000006e4, + .hal_tcl2_ring_base_lsb = 0x000006ec, + .hal_tcl_ring_base_lsb = 0x0000079c, + + /* TCL STATUS ring address */ + .hal_tcl_status_ring_base_lsb = 0x000008a4, + + /* REO2SW(x) R0 ring configuration address */ + .hal_reo1_ring_base_lsb = 0x000001ec, + .hal_reo1_ring_base_msb = 0x000001f0, + .hal_reo1_ring_id = 0x000001f4, + .hal_reo1_ring_misc = 0x000001fc, + .hal_reo1_ring_hp_addr_lsb = 0x00000200, + .hal_reo1_ring_hp_addr_msb = 0x00000204, + .hal_reo1_ring_producer_int_setup = 0x00000210, + .hal_reo1_ring_msi1_base_lsb = 0x00000234, + .hal_reo1_ring_msi1_base_msb = 0x00000238, + .hal_reo1_ring_msi1_data = 0x0000023c, + .hal_reo2_ring_base_lsb = 0x00000244, + .hal_reo1_aging_thresh_ix_0 = 0x00000564, + .hal_reo1_aging_thresh_ix_1 = 0x00000568, + .hal_reo1_aging_thresh_ix_2 = 0x0000056c, + .hal_reo1_aging_thresh_ix_3 = 0x00000570, + + /* REO2SW(x) R2 ring pointers (head/tail) address */ + .hal_reo1_ring_hp = 0x00003028, + .hal_reo1_ring_tp = 0x0000302c, + .hal_reo2_ring_hp = 0x00003030, + + /* REO2TCL R0 ring configuration address */ + .hal_reo_tcl_ring_base_lsb = 0x000003fc, + .hal_reo_tcl_ring_hp = 0x00003058, + + /* REO CMD ring address */ + .hal_reo_cmd_ring_base_lsb = 0x000000e4, + .hal_reo_cmd_ring_hp = 0x00003010, + + /* REO status address */ + .hal_reo_status_ring_base_lsb = 0x00000504, + .hal_reo_status_hp = 0x00003070, + + /* SW2REO ring address */ + .hal_sw2reo_ring_base_lsb = 0x0000013c, + .hal_sw2reo_ring_hp = 0x00003018, + + /* WCSS relative address */ + .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, + .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, + .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, + .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, + + /* WBM Idle address */ + .hal_wbm_idle_link_ring_base_lsb = 0x00000874, + .hal_wbm_idle_link_ring_misc = 0x00000884, + + /* SW2WBM release address */ + .hal_wbm_release_ring_base_lsb = 0x000001ec, + + /* WBM2SW release address */ + .hal_wbm0_release_ring_base_lsb = 0x00000924, + .hal_wbm1_release_ring_base_lsb = 0x0000097c, + + /* PCIe base address */ + .pcie_qserdes_sysclk_en_sel = 0x0, + .pcie_pcs_osc_dtct_config_base = 0x0, + + /* Shadow register area */ + .hal_shadow_base_addr = 0x00000504, }; const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { diff --git a/drivers/net/wireless/ath/ath11k/hw.h b/drivers/net/wireless/ath/ath11k/hw.h index c2ee39f977c2..f91009ef60b7 100644 --- a/drivers/net/wireless/ath/ath11k/hw.h +++ b/drivers/net/wireless/ath/ath11k/hw.h @@ -246,6 +246,7 @@ extern const struct ath11k_hw_ops ipq6018_ops; extern const struct ath11k_hw_ops qca6390_ops; extern const struct ath11k_hw_ops qcn9074_ops; extern const struct ath11k_hw_ops wcn6855_ops; +extern const struct ath11k_hw_ops wcn6750_ops; extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074; extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390; @@ -348,6 +349,12 @@ struct ath11k_hw_regs { u32 hal_reo_status_ring_base_lsb; u32 hal_reo_status_hp; + u32 hal_reo_cmd_ring_base_lsb; + u32 hal_reo_cmd_ring_hp; + + u32 hal_sw2reo_ring_base_lsb; + u32 hal_sw2reo_ring_hp; + u32 hal_seq_wcss_umac_ce0_src_reg; u32 hal_seq_wcss_umac_ce0_dst_reg; u32 hal_seq_wcss_umac_ce1_src_reg; @@ -363,12 +370,15 @@ struct ath11k_hw_regs { u32 pcie_qserdes_sysclk_en_sel; u32 pcie_pcs_osc_dtct_config_base; + + u32 hal_shadow_base_addr; }; extern const struct ath11k_hw_regs ipq8074_regs; extern const struct ath11k_hw_regs qca6390_regs; extern const struct ath11k_hw_regs qcn9074_regs; extern const struct ath11k_hw_regs wcn6855_regs; +extern const struct ath11k_hw_regs wcn6750_regs; static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type) { From patchwork Wed Apr 27 11:18:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828661 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43887C4332F for ; Wed, 27 Apr 2022 11:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232508AbiD0LWo (ORCPT ); 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27 Apr 2022 04:19:28 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:28 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:28 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:25 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 8/9] ath11k: Datapath changes to support WCN6750 Date: Wed, 27 Apr 2022 16:48:47 +0530 Message-ID: <20220427111848.9257-9-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org HAL RX descriptor for WCN6750 is same as QCN9074, this means that the size of the HAL RX decriptor and the DP APIs that WCN6750 requires to enable datapath should be initialized with that of QCN9074's RX descriptor size and the DP APIs respectively. There is one change wrt to REO configuration though, REO configuration for WCN6750 follows WCN6855, therefore use reo_setup() of WCN6855 for WCN6750. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/core.c | 1 + drivers/net/wireless/ath/ath11k/hw.c | 32 ++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/net/wireless/ath/ath11k/core.c b/drivers/net/wireless/ath/ath11k/core.c index 5ee9f1c53a89..6ef7f52a5c75 100644 --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -489,6 +489,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = { .num_vdevs = 16 + 1, .num_peers = 512, .supports_suspend = false, + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), .supports_regdb = true, .fix_l1ss = false, .credit_flow = true, diff --git a/drivers/net/wireless/ath/ath11k/hw.c b/drivers/net/wireless/ath/ath11k/hw.c index fc026969069c..845e25f98a68 100644 --- a/drivers/net/wireless/ath/ath11k/hw.c +++ b/drivers/net/wireless/ath/ath11k/hw.c @@ -1020,6 +1020,38 @@ const struct ath11k_hw_ops wcn6750_ops = { .wmi_init_config = ath11k_init_wmi_config_qca6390, .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, + .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, + .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, + .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, + .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, + .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, + .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, + .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, + .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, + .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, + .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, + .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, + .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, + .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, + .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, + .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, + .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, + .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, + .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, + .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, + .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, + .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, + .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, + .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, + .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, + .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, + .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, + .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, + .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, + .reo_setup = ath11k_hw_wcn6855_reo_setup, + .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, + .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, + .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, }; #define ATH11K_TX_RING_MASK_0 0x1 From patchwork Wed Apr 27 11:18:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Pubbisetty X-Patchwork-Id: 12828662 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2A53C43217 for ; Wed, 27 Apr 2022 11:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232487AbiD0LWp (ORCPT ); Wed, 27 Apr 2022 07:22:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232502AbiD0LWn (ORCPT ); Wed, 27 Apr 2022 07:22:43 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4BE42F03E; Wed, 27 Apr 2022 04:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651058371; x=1682594371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GRMvWEYoX0nBDgag5c6xSP5NPTllYkloxSH72AUW00w=; b=c7lsTgXhA1DFceErk2d3d3kww7wFbiJtvEf33bLFnZIu5KRZVFyZ5gbl qCC3udlry0/6d40Ou1tiEci7CL40Mt8vH0Shv0Cj6JwncG9KmAd05TUuA TIsryyjowuAubzQpIOEspnJV1sUELqbUxxDLWcINcxGLsePFBiK8Lw/HG 0=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Apr 2022 04:19:31 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 04:19:31 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:31 -0700 Received: from mpubbise-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 04:19:28 -0700 From: Manikanta Pubbisetty To: CC: , , , , Manikanta Pubbisetty Subject: [PATCH v6 9/9] ath11k: Add support for WCN6750 device Date: Wed, 27 Apr 2022 16:48:48 +0530 Message-ID: <20220427111848.9257-10-quic_mpubbise@quicinc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220427111848.9257-1-quic_mpubbise@quicinc.com> References: <20220427111848.9257-1-quic_mpubbise@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org WCN6750 is non-DBS 2x2 11AX chipset. Unlike QCA6390 which is a DBS (dual band simultaneous) solution (2 LMACs), WCN6750 has a single LMAC supporting 2G, 5G and 6G bands but will operate only on one band at any given point. WCN6750 is a PCIe based solution, but it is attached to the WPSS (Wireless Processor SubSystem) Q6 processor, hence it is enumerated by the Q6 processor. It is registered to the APSS processor (Application Processor SubSystem) as a platform device(AHB) and remoteproc APIs are used to boot up or shutdown the device like other AHB devices. Also, Device information like BAR and it's size is not known to the APSS processor as the chip is enumerated by WPSS Q6. These details are fetched over QMI. STA and AP modes are supported. Verified basic connectivity and ping in both the modes. An important point to note is that though WCN6750 is a PCIe device, it cannot be attached to any other platform except on Qualcomm Snapdragon SoCs due to the aforementioned reasons. Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-00887-QCAMSLSWPLZ-1 Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-01720.1-QCAHSPSWPL_V1_V2_SILICONZ_LITE-1 Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.5.0.1-01100-QCAHKSWPL_SILICONZ-1 Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.4.0.1-00192-QCAHKSWPL_SILICONZ-1 Signed-off-by: Manikanta Pubbisetty --- drivers/net/wireless/ath/ath11k/Makefile | 5 +- drivers/net/wireless/ath/ath11k/ahb.c | 152 ++++++++++++++++++++--- drivers/net/wireless/ath/ath11k/ahb.h | 1 - drivers/net/wireless/ath/ath11k/core.h | 1 + drivers/net/wireless/ath/ath11k/pcic.c | 23 ++++ 5 files changed, 164 insertions(+), 18 deletions(-) diff --git a/drivers/net/wireless/ath/ath11k/Makefile b/drivers/net/wireless/ath/ath11k/Makefile index 0ebfe41d6143..cc47e0114595 100644 --- a/drivers/net/wireless/ath/ath11k/Makefile +++ b/drivers/net/wireless/ath/ath11k/Makefile @@ -16,7 +16,8 @@ ath11k-y += core.o \ ce.o \ peer.o \ dbring.o \ - hw.o + hw.o \ + pcic.o ath11k-$(CONFIG_ATH11K_DEBUGFS) += debugfs.o debugfs_htt_stats.o debugfs_sta.o ath11k-$(CONFIG_NL80211_TESTMODE) += testmode.o @@ -29,7 +30,7 @@ obj-$(CONFIG_ATH11K_AHB) += ath11k_ahb.o ath11k_ahb-y += ahb.o obj-$(CONFIG_ATH11K_PCI) += ath11k_pci.o -ath11k_pci-y += mhi.o pci.o pcic.o +ath11k_pci-y += mhi.o pci.o # for tracing framework to find trace.h CFLAGS_trace.o := -I$(src) diff --git a/drivers/net/wireless/ath/ath11k/ahb.c b/drivers/net/wireless/ath/ath11k/ahb.c index fa12e50f32f4..8be84353b1cc 100644 --- a/drivers/net/wireless/ath/ath11k/ahb.c +++ b/drivers/net/wireless/ath/ath11k/ahb.c @@ -13,6 +13,7 @@ #include "debug.h" #include "hif.h" #include +#include "pcic.h" static const struct of_device_id ath11k_ahb_of_match[] = { /* TODO: Should we change the compatible string to something similar @@ -24,12 +25,15 @@ static const struct of_device_id ath11k_ahb_of_match[] = { { .compatible = "qcom,ipq6018-wifi", .data = (void *)ATH11K_HW_IPQ6018_HW10, }, + { .compatible = "qcom,wcn6750-wifi", + .data = (void *)ATH11K_HW_WCN6750_HW10, + }, { } }; MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match); -static const struct ath11k_bus_params ath11k_ahb_bus_params = { +static const struct ath11k_bus_params ath11k_ahb_bus_params_ipq8074 = { .mhi_support = false, .m3_fw_support = false, .fixed_bdf_addr = true, @@ -40,7 +44,7 @@ static const struct ath11k_bus_params ath11k_ahb_bus_params = { .ce_window_idx = 0, }; -const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = { +static const struct ath11k_bus_params ath11k_ahb_bus_params_wcn6750 = { .mhi_support = false, .m3_fw_support = false, .fixed_bdf_addr = false, @@ -51,6 +55,16 @@ const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params = { .ce_window_idx = 2, }; +static int +ath11k_ahb_get_msi_irq_wcn6750(struct ath11k_base *ab, unsigned int vector) +{ + return ab->pci.msi.irqs[vector]; +} + +static const struct ath11k_pci_ops ath11k_ahb_pci_ops_wcn6750 = { + .get_msi_irq = ath11k_ahb_get_msi_irq_wcn6750, +}; + #define ATH11K_IRQ_CE0_OFFSET 4 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { @@ -417,6 +431,9 @@ static void ath11k_ahb_free_irq(struct ath11k_base *ab) int irq_idx; int i; + if (ab->bus_params.hybrid_bus_type) + return ath11k_pcic_free_irq(ab); + for (i = 0; i < ab->hw_params.ce_count; i++) { if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) continue; @@ -571,6 +588,9 @@ static int ath11k_ahb_config_irq(struct ath11k_base *ab) int irq, irq_idx, i; int ret; + if (ab->bus_params.hybrid_bus_type) + return ath11k_pcic_config_irq(ab); + /* Configure CE irqs */ for (i = 0; i < ab->hw_params.ce_count; i++) { struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; @@ -640,7 +660,7 @@ static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id return 0; } -static const struct ath11k_hif_ops ath11k_ahb_hif_ops = { +static const struct ath11k_hif_ops ath11k_ahb_hif_ops_ipq8074 = { .start = ath11k_ahb_start, .stop = ath11k_ahb_stop, .read32 = ath11k_ahb_read32, @@ -652,6 +672,20 @@ static const struct ath11k_hif_ops ath11k_ahb_hif_ops = { .power_up = ath11k_ahb_power_up, }; +static const struct ath11k_hif_ops ath11k_ahb_hif_ops_wcn6750 = { + .start = ath11k_pcic_start, + .stop = ath11k_pcic_stop, + .read32 = ath11k_pcic_read32, + .write32 = ath11k_pcic_write32, + .irq_enable = ath11k_pcic_ext_irq_enable, + .irq_disable = ath11k_pcic_ext_irq_disable, + .get_msi_address = ath11k_pcic_get_msi_address, + .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment, + .map_service_to_pipe = ath11k_pcic_map_service_to_pipe, + .power_down = ath11k_ahb_power_down, + .power_up = ath11k_ahb_power_up, +}; + static int ath11k_core_get_rproc(struct ath11k_base *ab) { struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); @@ -674,12 +708,85 @@ static int ath11k_core_get_rproc(struct ath11k_base *ab) return 0; } +static int ath11k_ahb_setup_msi_resources(struct ath11k_base *ab) +{ + struct platform_device *pdev = ab->pdev; + phys_addr_t msi_addr_pa; + dma_addr_t msi_addr_iova; + struct resource *res; + int int_prop; + int ret; + int i; + + ret = ath11k_pcic_init_msi_config(ab); + if (ret) { + ath11k_err(ab, "failed to init msi config: %d\n", ret); + return ret; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ath11k_err(ab, "failed to fetch msi_addr\n"); + return -ENOENT; + } + + msi_addr_pa = res->start; + msi_addr_iova = dma_map_resource(ab->dev, msi_addr_pa, PAGE_SIZE, + DMA_FROM_DEVICE, 0); + if (dma_mapping_error(ab->dev, msi_addr_iova)) + return -ENOMEM; + + ab->pci.msi.addr_lo = lower_32_bits(msi_addr_iova); + ab->pci.msi.addr_hi = upper_32_bits(msi_addr_iova); + + ret = of_property_read_u32_index(ab->dev->of_node, "interrupts", 1, &int_prop); + if (ret) + return ret; + + ab->pci.msi.ep_base_data = int_prop + 32; + + for (i = 0; i < ab->pci.msi.config->total_vectors; i++) { + res = platform_get_resource(pdev, IORESOURCE_IRQ, i); + if (!res) + return -ENODEV; + + ab->pci.msi.irqs[i] = res->start; + } + + set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); + + return 0; +} + +static int ath11k_ahb_setup_resources(struct ath11k_base *ab) +{ + struct platform_device *pdev = ab->pdev; + struct resource *mem_res; + void __iomem *mem; + + if (ab->bus_params.hybrid_bus_type) + return ath11k_ahb_setup_msi_resources(ab); + + mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); + if (IS_ERR(mem)) { + dev_err(&pdev->dev, "ioremap error\n"); + return PTR_ERR(mem); + } + + ab->mem = mem; + ab->mem_len = resource_size(mem_res); + + return 0; +} + static int ath11k_ahb_probe(struct platform_device *pdev) { struct ath11k_base *ab; const struct of_device_id *of_id; - struct resource *mem_res; - void __iomem *mem; + const struct ath11k_bus_params *bus_params; + const struct ath11k_hif_ops *hif_ops; + const struct ath11k_pci_ops *pci_ops; + enum ath11k_hw_rev hw_rev; int ret; of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev); @@ -688,10 +795,23 @@ static int ath11k_ahb_probe(struct platform_device *pdev) return -EINVAL; } - mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); - if (IS_ERR(mem)) { - dev_err(&pdev->dev, "ioremap error\n"); - return PTR_ERR(mem); + hw_rev = (enum ath11k_hw_rev)of_id->data; + + switch (hw_rev) { + case ATH11K_HW_IPQ8074: + case ATH11K_HW_IPQ6018_HW10: + bus_params = &ath11k_ahb_bus_params_ipq8074; + hif_ops = &ath11k_ahb_hif_ops_ipq8074; + pci_ops = NULL; + break; + case ATH11K_HW_WCN6750_HW10: + bus_params = &ath11k_ahb_bus_params_wcn6750; + hif_ops = &ath11k_ahb_hif_ops_wcn6750; + pci_ops = &ath11k_ahb_pci_ops_wcn6750; + break; + default: + dev_err(&pdev->dev, "unsupported device type %d\n", hw_rev); + return -EOPNOTSUPP; } ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); @@ -701,20 +821,22 @@ static int ath11k_ahb_probe(struct platform_device *pdev) } ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb), - ATH11K_BUS_AHB, - &ath11k_ahb_bus_params); + ATH11K_BUS_AHB, bus_params); if (!ab) { dev_err(&pdev->dev, "failed to allocate ath11k base\n"); return -ENOMEM; } - ab->hif.ops = &ath11k_ahb_hif_ops; + ab->hif.ops = hif_ops; + ab->pci.ops = pci_ops; ab->pdev = pdev; - ab->hw_rev = (enum ath11k_hw_rev)of_id->data; - ab->mem = mem; - ab->mem_len = resource_size(mem_res); + ab->hw_rev = hw_rev; platform_set_drvdata(pdev, ab); + ret = ath11k_ahb_setup_resources(ab); + if (ret) + goto err_core_free; + ret = ath11k_core_pre_init(ab); if (ret) goto err_core_free; diff --git a/drivers/net/wireless/ath/ath11k/ahb.h b/drivers/net/wireless/ath/ath11k/ahb.h index a276e3d1dff8..eeb1feed2c81 100644 --- a/drivers/net/wireless/ath/ath11k/ahb.h +++ b/drivers/net/wireless/ath/ath11k/ahb.h @@ -10,7 +10,6 @@ #define ATH11K_AHB_RECOVERY_TIMEOUT (3 * HZ) struct ath11k_base; -extern const struct ath11k_bus_params ath11k_ahb_hybrid_bus_params; struct ath11k_ahb { struct rproc *tgt_rproc; diff --git a/drivers/net/wireless/ath/ath11k/core.h b/drivers/net/wireless/ath/ath11k/core.h index ee0ad93d5843..18f212f3fc27 100644 --- a/drivers/net/wireless/ath/ath11k/core.h +++ b/drivers/net/wireless/ath/ath11k/core.h @@ -962,6 +962,7 @@ struct ath11k_base { struct { const struct ath11k_msi_config *config; u32 ep_base_data; + u32 irqs[32]; u32 addr_lo; u32 addr_hi; } msi; diff --git a/drivers/net/wireless/ath/ath11k/pcic.c b/drivers/net/wireless/ath/ath11k/pcic.c index d79433e20181..2d93a3b766b5 100644 --- a/drivers/net/wireless/ath/ath11k/pcic.c +++ b/drivers/net/wireless/ath/ath11k/pcic.c @@ -106,6 +106,15 @@ static const struct ath11k_msi_config ath11k_msi_config[] = { }, .hw_rev = ATH11K_HW_WCN6855_HW21, }, + { + .total_vectors = 28, + .total_users = 2, + .users = (struct ath11k_msi_user[]) { + { .name = "CE", .num_vectors = 10, .base_vector = 0 }, + { .name = "DP", .num_vectors = 18, .base_vector = 10 }, + }, + .hw_rev = ATH11K_HW_WCN6750_HW10, + }, }; int ath11k_pcic_init_msi_config(struct ath11k_base *ab) @@ -172,6 +181,7 @@ void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value) !ret) ab->pci.ops->release(ab); } +EXPORT_SYMBOL(ath11k_pcic_write32); u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset) { @@ -203,6 +213,7 @@ u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset) return val; } +EXPORT_SYMBOL(ath11k_pcic_read32); void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, u32 *msi_addr_hi) @@ -210,6 +221,7 @@ void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, *msi_addr_lo = ab->pci.msi.addr_lo; *msi_addr_hi = ab->pci.msi.addr_hi; } +EXPORT_SYMBOL(ath11k_pcic_get_msi_address); int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, int *num_vectors, u32 *user_base_data, @@ -237,6 +249,7 @@ int ath11k_pcic_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, return -EINVAL; } +EXPORT_SYMBOL(ath11k_pcic_get_user_msi_assignment); void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx) { @@ -253,6 +266,7 @@ void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx) } *msi_idx = msi_data_idx; } +EXPORT_SYMBOL(ath11k_pcic_get_ce_msi_idx); static void ath11k_pcic_free_ext_irq(struct ath11k_base *ab) { @@ -281,6 +295,7 @@ void ath11k_pcic_free_irq(struct ath11k_base *ab) ath11k_pcic_free_ext_irq(ab); } +EXPORT_SYMBOL(ath11k_pcic_free_irq); static void ath11k_pcic_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) { @@ -431,6 +446,7 @@ void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab) ath11k_pcic_ext_grp_enable(irq_grp); } } +EXPORT_SYMBOL(ath11k_pcic_ext_irq_enable); static void ath11k_pcic_sync_ext_irqs(struct ath11k_base *ab) { @@ -451,6 +467,7 @@ void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab) __ath11k_pcic_ext_irq_disable(ab); ath11k_pcic_sync_ext_irqs(ab); } +EXPORT_SYMBOL(ath11k_pcic_ext_irq_disable); static int ath11k_pcic_ext_grp_napi_poll(struct napi_struct *napi, int budget) { @@ -630,6 +647,7 @@ int ath11k_pcic_config_irq(struct ath11k_base *ab) return 0; } +EXPORT_SYMBOL(ath11k_pcic_config_irq); void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab) { @@ -643,6 +661,7 @@ void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab) ath11k_pcic_ce_irq_enable(ab, i); } } +EXPORT_SYMBOL(ath11k_pcic_ce_irqs_enable); static void ath11k_pcic_kill_tasklets(struct ath11k_base *ab) { @@ -664,12 +683,14 @@ void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab) ath11k_pcic_sync_ce_irqs(ab); ath11k_pcic_kill_tasklets(ab); } +EXPORT_SYMBOL(ath11k_pcic_ce_irq_disable_sync); void ath11k_pcic_stop(struct ath11k_base *ab) { ath11k_pcic_ce_irq_disable_sync(ab); ath11k_ce_cleanup_pipes(ab); } +EXPORT_SYMBOL(ath11k_pcic_stop); int ath11k_pcic_start(struct ath11k_base *ab) { @@ -680,6 +701,7 @@ int ath11k_pcic_start(struct ath11k_base *ab) return 0; } +EXPORT_SYMBOL(ath11k_pcic_start); int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, u8 *ul_pipe, u8 *dl_pipe) @@ -723,3 +745,4 @@ int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, return 0; } +EXPORT_SYMBOL(ath11k_pcic_map_service_to_pipe);