From patchwork Wed Apr 27 17:09:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12829241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92367C433F5 for ; Wed, 27 Apr 2022 17:10:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243805AbiD0RN2 (ORCPT ); Wed, 27 Apr 2022 13:13:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243785AbiD0RN1 (ORCPT ); Wed, 27 Apr 2022 13:13:27 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2159F33347; Wed, 27 Apr 2022 10:10:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651079416; x=1682615416; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=wchRf7uasp3Msv81sa2LxNNZ/QRRHIhp2gjeakQULuA=; b=ff1ztKQ7qao+sthnIyS+/Y35ImPU9JQLTIKfWNysLHPM7yqNz9NrlYBH TrTtrMDoJ4Kya6pv484zsSbSSAE9HIebnKbhCrW8tOovE1Mal8u2tHZ6k YR+66iYN1H82x9M7x2Icnvqe4y5xDwv1sU/Tj96HRpxn+8a4712utCaqS s=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Apr 2022 10:10:15 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 10:10:15 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:15 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:10 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 1/4] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset Date: Wed, 27 Apr 2022 22:39:40 +0530 Message-ID: <1651079383-7665-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> References: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add pinmux nodes for primary and secondary I2S for SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 015a347..fb1f4ca 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -359,6 +359,20 @@ bias-disable; }; +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; + &pm7325_gpios { key_vol_up_default: key-vol-up-default { pins = "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 00bacc4..0242f1d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3713,6 +3713,46 @@ function = "edp_hot"; }; + mi2s0_data0: mi2s0-data0 { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + mi2s0_data1: mi2s0-data1 { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + mi2s0_mclk: mi2s0-mclk { + pins = "gpio96"; + function = "pri_mi2s"; + }; + + mi2s0_sclk: mi2s0-sclk { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + mi2s0_ws: mi2s0-ws { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + mi2s1_data0: mi2s1-data0 { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + mi2s1_sclk: mi2s1-sclk { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + mi2s1_ws: mi2s1-ws { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; From patchwork Wed Apr 27 17:09:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12829242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CE90C433FE for ; Wed, 27 Apr 2022 17:10:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243770AbiD0RNe (ORCPT ); Wed, 27 Apr 2022 13:13:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243785AbiD0RNb (ORCPT ); Wed, 27 Apr 2022 13:13:31 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EE3335248; Wed, 27 Apr 2022 10:10:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651079420; x=1682615420; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=OQKs7KpvW32lkG5kymmJYdP5T6OV+9+SRNex0SKdl8k=; b=fegTpj03Ga2NHDbaA7EqGRy6GJqto4I3v8/IKlC3e2hdNgUL8PqUybnP q9qgvbem40a94iAMgtQQ8kQmGShjX9MNhvBjCVxtWiS8tYa3xNcpBt+cB uiB4aV3idFrksKm0FFDT0GozWIkvyWcDdLB0ZFsLAnleWp62jWy6jBFqT o=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Apr 2022 10:10:20 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 10:10:20 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:19 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:15 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 2/4] arm64: dts: qcom: sc7280: Add secondary MI2S pinmux specifications for CRD 3.0/3.1 Date: Wed, 27 Apr 2022 22:39:41 +0530 Message-ID: <1651079383-7665-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> References: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add drive strength property for secondary MI2S on sc7280 based platforms of rev5+ (aka CRD 3.0/3.1) boards. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index b06f61e..deaea3a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -111,6 +111,20 @@ ap_ts_pen_1v8: &i2c13 { * - If a pin is not hooked up on Qcard, it gets no name. */ +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; + &pm8350c_gpios { gpio-line-names = "FLASH_STROBE_1", /* 1 */ "AP_SUSPEND", From patchwork Wed Apr 27 17:09:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12829243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36FB2C433F5 for ; Wed, 27 Apr 2022 17:10:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243785AbiD0RNm (ORCPT ); Wed, 27 Apr 2022 13:13:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243775AbiD0RNl (ORCPT ); Wed, 27 Apr 2022 13:13:41 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22FA73AA4B; Wed, 27 Apr 2022 10:10:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651079429; x=1682615429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=gDa4x6ig5LhgIGsVxyAAqW17uIgDW7wMzKHLc+1Lryg=; b=aVcwhQ3MWx94usfnwWNEGfnSedd+HEbMXbe/E8PyIzzEuOMsu6yFq1ZX msUIQfFkewWxzXzZmU4a53r13pREtFRRAstus3dugkw6zIKvBvgcEw5ZP bzxXzI63WMZlILnQvYADEwd6xkuNZGqAoeR8PeFV3MEsjS+e/iZAfToix E=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Apr 2022 10:10:28 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 10:10:28 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:27 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:19 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 3/4] arm64: dts: qcom: sc7280: add lpass lpi pin controller node Date: Wed, 27 Apr 2022 22:39:42 +0530 Message-ID: <1651079383-7665-4-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> References: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add LPASS LPI pinctrl node required for Audio functionality on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 84 ++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 +++++++++++++++++++++++++++++++ 2 files changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index fb1f4ca..2f863c0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -359,6 +359,90 @@ bias-disable; }; +&lpass_dmic01 { + clk { + drive-strength = <8>; + }; +}; + +&lpass_dmic01_sleep { + clk { + drive-strength = <2>; + bias-disable; + }; + + data { + pull-down; + }; +}; + +&lpass_dmic23 { + clk { + drive-strength = <8>; + }; +}; + +&lpass_dmic23_sleep { + clk { + drive-strength = <2>; + bias-disable; + }; + + data { + pull-down; + }; +}; + +&lpass_rx_swr { + clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; +}; + +&lpass_rx_swr_sleep { + clk { + drive-strength = <2>; + bias-pull-down; + }; + + data { + drive-strength = <2>; + bias-pull-down; + }; +}; + +&lpass_tx_swr { + clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + slew-rate = <1>; + bias-bus-hold; + }; +}; + +&lpass_tx_swr_sleep { + clk { + drive-strength = <2>; + bias-pull-down; + }; + + data { + bias-bus-hold; + }; +}; + &mi2s1_data0 { drive-strength = <6>; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0242f1d..fe500f4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2083,6 +2083,113 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0 0x033c0000 0x0 0x20000>, + <0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + #clock-cells = <1>; + + lpass_dmic01: dmic01 { + clk { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + data { + pins = "gpio7"; + function = "dmic1_data"; + }; + }; + + lpass_dmic01_sleep: dmic01-sleep { + clk { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + data { + pins = "gpio7"; + function = "dmic1_data"; + }; + }; + + lpass_dmic23: dmic23 { + clk { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + data { + pins = "gpio9"; + function = "dmic2_data"; + }; + }; + + lpass_dmic23_sleep: dmic23-sleep { + clk { + pins = "gpio8"; + function = "dmic2_clk"; + }; + + data { + pins = "gpio9"; + function = "dmic2_data"; + }; + }; + + lpass_rx_swr: rx-swr { + clk { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + }; + + lpass_rx_swr_sleep: rx-swr-sleep { + clk { + pins = "gpio3"; + function = "swr_rx_clk"; + }; + + data { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + }; + }; + + lpass_tx_swr: tx-swr { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + data { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + }; + + lpass_tx_swr_sleep: tx-swr-sleep { + clk { + pins = "gpio0"; + function = "swr_tx_clk"; + }; + + data { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; reg = <0 0x03d00000 0 0x40000>, From patchwork Wed Apr 27 17:09:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivasa Rao Mandadapu X-Patchwork-Id: 12829244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B349EC433EF for ; Wed, 27 Apr 2022 17:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243901AbiD0RNq (ORCPT ); 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27 Apr 2022 10:10:32 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:32 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Apr 2022 10:10:28 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v12 4/4] arm64: dts: qcom: sc7280-herobrine: Add lpi pinmux properties for CRD 3.0/3.1 Date: Wed, 27 Apr 2022 22:39:43 +0530 Message-ID: <1651079383-7665-5-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> References: <1651079383-7665-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add LPASS LPI pinctrl properties, which are required for Audio functionality on herobrine based platforms of rev5+ (aka CRD 3.0/3.1) boards. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 84 +++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index deaea3a..dfc42df 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -111,6 +111,90 @@ ap_ts_pen_1v8: &i2c13 { * - If a pin is not hooked up on Qcard, it gets no name. */ +&lpass_dmic01 { + clk { + drive-strength = <8>; + }; +}; + +&lpass_dmic01_sleep { + clk { + drive-strength = <2>; + bias-disable; + }; + + data { + pull-down; + }; +}; + +&lpass_dmic23 { + clk { + drive-strength = <8>; + }; +}; + +&lpass_dmic23_sleep { + clk { + drive-strength = <2>; + bias-disable; + }; + + data { + pull-down; + }; +}; + +&lpass_rx_swr { + clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; +}; + +&lpass_rx_swr_sleep { + clk { + drive-strength = <2>; + bias-pull-down; + }; + + data { + drive-strength = <2>; + bias-pull-down; + }; +}; + +&lpass_tx_swr { + clk { + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + slew-rate = <1>; + bias-bus-hold; + }; +}; + +&lpass_tx_swr_sleep { + clk { + drive-strength = <2>; + bias-pull-down; + }; + + data { + bias-bus-hold; + }; +}; + &mi2s1_data0 { drive-strength = <6>; bias-disable;