From patchwork Thu Apr 28 08:28:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12830207 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CBDBC433F5 for ; Thu, 28 Apr 2022 08:33:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344319AbiD1Ig4 (ORCPT ); Thu, 28 Apr 2022 04:36:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344219AbiD1IgJ (ORCPT ); Thu, 28 Apr 2022 04:36:09 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24B1BA66F7 for ; Thu, 28 Apr 2022 01:29:15 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id c190-20020a1c35c7000000b0038e37907b5bso4864936wma.0 for ; Thu, 28 Apr 2022 01:29:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=solid-run-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ahe9kmz5sZkVP4ViBXwullVhsY17APIJQ3g9W0K/6H4=; b=yfcJEiY5Fch3WC38kIxmXGd8u+P1R7SXR02eCOL9g+0TLv8H8RrUu+pvws5hrQW3Ys K0id9eCydzjBqNCdCGuroFsD1VI0Um+2EPS2CtZQLYU8+0qndFDGWXlfEIdKcWUB3+9t Nwfmoj36nySzLmAaDCcMxAUrGIo0w+KLdHIlFkaLEsiFceJZMwt+Otobj4qwDI9e1akn TiZEsXV3YTBagZYl/nhq4hcJtvM7GwsJPkVdabToN8cuJxGzpNCMJrb5/C4MWP1VQ+D1 trOvrBFHq2Ky+uBiyyy8M/txo4lbWtrf5S6QPT9YC2FNlT1L2B135DFnJd4RWK66knEH zeVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ahe9kmz5sZkVP4ViBXwullVhsY17APIJQ3g9W0K/6H4=; b=C4nISZfe9f6NvRUAHioa3INIl27pnaftVX5XMJRuwaMA0eqhKP5xDPOa7YGUleIu68 LblgGrNqylrQl+kl8eohxS8fh+LHYNDdlLDNQ/54SuAxEta0gwmgrc//NYz8pqsWGRBJ WaP3m/9BxyEQ3gOfJ26mZ82GWkXDZERT27gaFoqEorfC0JiAm2jQqo2JzgqA4RI/pATu Dk0jygCRx8M57rIIBNiVTKxrcCbsRCP5DF7P3jQtUwvf8+BKosPP5J+Q8v478byQxIsb sTg/13XZV8leVBlwbph1Vj4YUXSq/G0oys93tozK88BBiygGYSmdr+CUXAmIY1VLpjJm 8lDg== X-Gm-Message-State: AOAM531e4zwuyn0HGhbzIxb2sNPBRGTKhQIHos4/iZucp03rW4O8UugP /+fEkrE0t32HxP6nvCIle7jxXS1WqPgkxbD60s3gwA== X-Google-Smtp-Source: ABdhPJxKU7CIrW8O5/1yBAOs8Fox+v2V/SG61aUDCYJQB8JIKWP7RSOwT0g6GPkApQhEj58GkBdxZA== X-Received: by 2002:a7b:cd97:0:b0:38f:f785:ff8 with SMTP id y23-20020a7bcd97000000b0038ff7850ff8mr38324474wmj.44.1651134553361; Thu, 28 Apr 2022 01:29:13 -0700 (PDT) Received: from josua-work.lan (bzq-82-81-222-124.cablep.bezeqint.net. [82.81.222.124]) by smtp.gmail.com with ESMTPSA id bj3-20020a0560001e0300b0020af3d365f4sm1876249wrb.98.2022.04.28.01.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 01:29:12 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Andrew Lunn , Michael Hennerich , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Alexandru Ardelean Subject: [PATCH v3 1/3] dt-bindings: net: adin: document phy clock output properties Date: Thu, 28 Apr 2022 11:28:46 +0300 Message-Id: <20220428082848.12191-2-josua@solid-run.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220428082848.12191-1-josua@solid-run.com> References: <20220419102709.26432-1-josua@solid-run.com> <20220428082848.12191-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add DT properties to configure both pins. Signed-off-by: Josua Mayer Reviewed-by: Andrew Lunn --- V1 -> V2: changed clkout property to enum V1 -> V2: added property for CLK25_REF pin .../devicetree/bindings/net/adi,adin.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml index 1129f2b58e98..3e0c6304f190 100644 --- a/Documentation/devicetree/bindings/net/adi,adin.yaml +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml @@ -36,6 +36,23 @@ properties: enum: [ 4, 8, 12, 16, 20, 24 ] default: 8 + adi,phy-output-clock: + description: Select clock output on GP_CLK pin. Three clocks are available: + A 25MHz reference, a free-running 125MHz and a recovered 125MHz. + The phy can also automatically switch between the reference and the + respective 125MHz clocks based on its internal state. + $ref: /schemas/types.yaml#/definitions/string + enum: + - 25mhz-reference + - 125mhz-free-running + - 125mhz-recovered + - adaptive-free-running + - adaptive-recovered + + adi,phy-output-reference-clock: + description: Enable 25MHz reference clock output on CLK25_REF pin. + $ref: /schemas/types.yaml#/definitions/flag + unevaluatedProperties: false examples: From patchwork Thu Apr 28 08:28:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12830208 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE196C433F5 for ; Thu, 28 Apr 2022 08:33:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344362AbiD1IhD (ORCPT ); Thu, 28 Apr 2022 04:37:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344451AbiD1IgU (ORCPT ); Thu, 28 Apr 2022 04:36:20 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE921A6E0C for ; Thu, 28 Apr 2022 01:29:16 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id q20so2497654wmq.1 for ; Thu, 28 Apr 2022 01:29:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=solid-run-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iUV3MD6MJVtQufo/3QTs0bizwDdcnDn7xd+ebVY+1Ig=; b=z7Kc+STRzxPgMhGBQTxsoGW7qSFRwplz7ysTPRXax1PT8KvV+MY0G/TRdeuDboWO5+ IKNzmOW9PWf+cde/wPAUlkaAlnCqm480rnbplSUylCt0Y4bzFItK2Z6xuh+J6mkhn3CA muVBU0wBNT3aO0A52LyGol71xCrCCYO3mDyB5sFbHg4BerZw/VhMkwKJL9ivaTwoUbMH muagIeIi8KCpyK+fOTthYRfD+b/GX5Jt54Y3zXL8F8SGmr9z/0QZY6d+tYd5e5KwAE+O dh9NG0aAX9hsMdvRdmK5iHqMw8cdXNQ+4cRpkDYlHpqEyodlGPi39b/D0XY0q6AUHpH7 AMTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iUV3MD6MJVtQufo/3QTs0bizwDdcnDn7xd+ebVY+1Ig=; b=0o4mUnPNyVxVntaM7Zs+nTlMQ/cAcGDZK++6cYskO41ZOg+PqOhvjzvcsFH8CEEGBt 5hiAN6i+yFtDHdgZImWo7MuijyH+vj11ps/BCQouItCzeJzGF5VetjFFAaOY/5EfIsT/ AOZdTE21zWq56iBjoWyakbp86T8f1hdYlSAYwSC9TZbds0q/FWxLjsbSQ+fiOgHD19OG Kxh4axmDx4/UEz4XVTogQ+btQtnnzf/OahPGUH5DTiQRc6LUpW2n/PpRs2XO5wjTbEKQ GODclXaRVUExOeGJPbgDR79Gg7h+MnYl5ehhoFKFvmxpzJC/hlg3QmQdqBt2IdOjElt/ ApEg== X-Gm-Message-State: AOAM531uain+Ih2jdFKDwMoPIphrIXUZ6lGYOJ++qP+nL6/BFgJgkRns A3mYvKXumEGnQm3wEE354MfQDtiRC8nd6CnHFECJWg== X-Google-Smtp-Source: ABdhPJzd4PL9toOx7EcOqqv9hRX/KxjJFzbV2jiP8qTDAJArmBiqQyjE7YagE4bZrZDb0qHUK7eHkQ== X-Received: by 2002:a1c:4e0b:0:b0:393:fd8f:e340 with SMTP id g11-20020a1c4e0b000000b00393fd8fe340mr8134882wmh.136.1651134554983; Thu, 28 Apr 2022 01:29:14 -0700 (PDT) Received: from josua-work.lan (bzq-82-81-222-124.cablep.bezeqint.net. [82.81.222.124]) by smtp.gmail.com with ESMTPSA id bj3-20020a0560001e0300b0020af3d365f4sm1876249wrb.98.2022.04.28.01.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 01:29:14 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Michael Hennerich , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Jakub Kicinski , Paolo Abeni Subject: [PATCH v3 2/3] net: phy: adin: add support for clock output Date: Thu, 28 Apr 2022 11:28:47 +0300 Message-Id: <20220428082848.12191-3-josua@solid-run.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220428082848.12191-1-josua@solid-run.com> References: <20220419102709.26432-1-josua@solid-run.com> <20220428082848.12191-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add support for selecting the clock via device-tree properties. Co-developed-by: Alvaro Karsz Signed-off-by: Alvaro Karsz Signed-off-by: Josua Mayer --- V2 -> V3: fix integer-as-null-pointer compiler warning V1 -> V2: revised dts property name for clock(s) V1 -> V2: implemented all 6 bits in the clock configuration register drivers/net/phy/adin.c | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 5ce6da62cc8e..2de3eaddfb8e 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -99,6 +99,15 @@ #define ADIN1300_GE_SOFT_RESET_REG 0xff0c #define ADIN1300_GE_SOFT_RESET BIT(0) +#define ADIN1300_GE_CLK_CFG_REG 0xff1f +#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0) +#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5) +#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4) +#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3) +#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2) +#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1) +#define ADIN1300_GE_CLK_CFG_25 BIT(0) + #define ADIN1300_GE_RGMII_CFG_REG 0xff23 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) #define ADIN1300_GE_RGMII_RX_SEL(x) \ @@ -433,6 +442,37 @@ static int adin_set_tunable(struct phy_device *phydev, } } +static int adin_config_clk_out(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + const char *val = NULL; + u8 sel = 0; + + device_property_read_string(dev, "adi,phy-output-clock", &val); + if(!val) { + /* property not present, do not enable GP_CLK pin */ + } else if(strcmp(val, "25mhz-reference") == 0) { + sel |= ADIN1300_GE_CLK_CFG_25; + } else if(strcmp(val, "125mhz-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_FREE_125; + } else if(strcmp(val, "125mhz-recovered") == 0) { + sel |= ADIN1300_GE_CLK_CFG_RCVR_125; + } else if(strcmp(val, "adaptive-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_FREE; + } else if(strcmp(val, "adaptive-recovered") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_RCVR; + } else { + phydev_err(phydev, "invalid adi,phy-output-clock\n"); + return -EINVAL; + } + + if(device_property_read_bool(dev, "adi,phy-output-reference-clock")) + sel |= ADIN1300_GE_CLK_CFG_REF_EN; + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG, + ADIN1300_GE_CLK_CFG_MASK, sel); +} + static int adin_config_init(struct phy_device *phydev) { int rc; @@ -455,6 +495,10 @@ static int adin_config_init(struct phy_device *phydev) if (rc < 0) return rc; + rc = adin_config_clk_out(phydev); + if (rc < 0) + return rc; + phydev_dbg(phydev, "PHY is using mode '%s'\n", phy_modes(phydev->interface)); From patchwork Thu Apr 28 08:28:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12830209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F219C433F5 for ; Thu, 28 Apr 2022 08:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344390AbiD1IhK (ORCPT ); Thu, 28 Apr 2022 04:37:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344393AbiD1IgY (ORCPT ); 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[82.81.222.124]) by smtp.gmail.com with ESMTPSA id bj3-20020a0560001e0300b0020af3d365f4sm1876249wrb.98.2022.04.28.01.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 01:29:16 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Russell King , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Subject: [PATCH v3 3/3] ARM: dts: imx6qdl-sr-som: update phy configuration for som revision 1.9 Date: Thu, 28 Apr 2022 11:28:48 +0300 Message-Id: <20220428082848.12191-4-josua@solid-run.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220428082848.12191-1-josua@solid-run.com> References: <20220419102709.26432-1-josua@solid-run.com> <20220428082848.12191-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Since SoM revision 1.9 the PHY has been replaced with an ADIN1300, add an entry for it next to the original. As Russell King pointed out, additional phy nodes cause warnings like: mdio_bus 2188000.ethernet-1: MDIO device at address 1 is missing To avoid this the new node has its status set to disabled. U-Boot will be modified to enable the appropriate phy node after probing. The existing ar8035 nodes have to stay enabled by default to avoid breaking existing systems when they update Linux only. Co-developed-by: Alvaro Karsz Signed-off-by: Alvaro Karsz Signed-off-by: Josua Mayer --- V2 -> V3: new phy node status set disabled V1 -> V2: changed dts property name arch/arm/boot/dts/imx6qdl-sr-som.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi index f86efd0ccc40..ce543e325cd3 100644 --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -83,6 +83,16 @@ ethernet-phy@4 { qca,clk-out-frequency = <125000000>; qca,smarteee-tw-us-1g = <24>; }; + + /* + * ADIN1300 (som rev 1.9 or later) is always at address 1. It + * will be enabled automatically by U-Boot if detected. + */ + ethernet-phy@1 { + reg = <1>; + adi,phy-output-clock = "125mhz-free-running"; + status = "disabled"; + }; }; };