From patchwork Thu Apr 28 16:44:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12831014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 104DDC43219 for ; Thu, 28 Apr 2022 16:44:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350278AbiD1Qri (ORCPT ); Thu, 28 Apr 2022 12:47:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350268AbiD1Qrh (ORCPT ); Thu, 28 Apr 2022 12:47:37 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABF96B1AB0; Thu, 28 Apr 2022 09:44:22 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id q20so3287882wmq.1; Thu, 28 Apr 2022 09:44:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jo7tWOSsCgtTcP6fE9H4HS3FFxnoGMJ2maOVgOmkHE0=; b=A+Fljyzwqh3DrLonRv/nd+/Y/uw/gWADsGYkS4ovl3z2I+C+xEQm61Mx9p4Lzmgqoc XOB8U4z4+Enx3gYB9+pN90dvB8/A/AWe2FDKR6irzVvYpRoBO1uNX4S2AancqNqHpOe0 TSpVGhx2tq7nvbQkir5MnS3y//cuuWt1g7EAxS170vhq7OhZqfa146HSSjtpIZiDxhx4 hc9Alpt7SmiHpiHDZGtMz12+CN5t36Uxm3pZ7jDyeuebKoKMF6R8r/xqJk/i0rWm/C3i sdAuwP0LmoYEI6TZeevRTuEls4oYhO5tL5QGsjC8GICW4EAJcuzE+FP7AwUy6o4gUp4H LC9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jo7tWOSsCgtTcP6fE9H4HS3FFxnoGMJ2maOVgOmkHE0=; b=VIcJsj+koqJ0Gp0mVZS70SVWugHidlceLSO7iU0MjEAy2rcL56KK8Bd7+t1h0yMUoI 4VEyNowuPAJ5UiKDRe3I8ZBq1iq8x3kyKkGNcACu2avFlxIL6BPnX23O610BuA9IVCc8 m/RD7cFZSMBqebYu8hr4x80VYcHxmqzQP6BafbOSzec71jAEnSNH991RzngJl2zJnxlQ nCxhrprJ2iKgn1eyUzKJlic4lpKqoo40i6GTL+XP3wzBxTVwRauO4EvvT2g4VOGtYIos itezATjQfhsu1C19mcIY/DH0xWrhsrNrM3DVLjOhHkKOUdnP/ExqHLXCPg2jjkw7EI/1 frbg== X-Gm-Message-State: AOAM531Xgl1TPTbedYh3vzwMwnd71DpZuDuLYB3tLOYVRD79zYtLe/Gv 1Fs8DjCGhQlxhIPJm49TnOQF60P7wtg= X-Google-Smtp-Source: ABdhPJxUYMZqevp8Zfb4hVitKz5HC6RoWvg4OvuYXpeMGOGS33WIGlZIsiJFrF9s5ka2N9tlveXlvQ== X-Received: by 2002:a05:600c:3b9c:b0:394:1611:ff1b with SMTP id n28-20020a05600c3b9c00b003941611ff1bmr2751593wms.185.1651164261239; Thu, 28 Apr 2022 09:44:21 -0700 (PDT) Received: from localhost (92.40.203.206.threembb.co.uk. [92.40.203.206]) by smtp.gmail.com with ESMTPSA id f189-20020a1c38c6000000b0038ff83b9792sm4453035wma.43.2022.04.28.09.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 09:44:20 -0700 (PDT) From: Aidan MacDonald To: sboyd@kernel.org, mturquette@baylibre.com, tsbogend@alpha.franken.de Cc: paulburton@kernel.org, paul@crapouillou.net, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/3] clk: ingenic: Allow specifying common clock flags Date: Thu, 28 Apr 2022 17:44:52 +0100 Message-Id: <20220428164454.17908-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220428164454.17908-1-aidanmacdonald.0x0@gmail.com> References: <20220428164454.17908-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Provide a flags field for clocks under the ingenic-cgu driver, which can be used to set generic common clock framework flags on the created clocks. For example, the CLK_IS_CRITICAL flag is needed for some clocks (such as CPU or memory) to stop them being automatically disabled. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- drivers/clk/ingenic/cgu.c | 2 +- drivers/clk/ingenic/cgu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index af31633a8862..861c50d6cb24 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -660,7 +660,7 @@ static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx) ingenic_clk->idx = idx; clk_init.name = clk_info->name; - clk_init.flags = 0; + clk_init.flags = clk_info->flags; clk_init.parent_names = parent_names; caps = clk_info->type; diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index bfc2b9c38a41..147b7df0d657 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -136,6 +136,7 @@ struct ingenic_cgu_custom_info { * struct ingenic_cgu_clk_info - information about a clock * @name: name of the clock * @type: a bitmask formed from CGU_CLK_* values + * @flags: common clock flags to set on this clock * @parents: an array of the indices of potential parents of this clock * within the clock_info array of the CGU, or -1 in entries * which correspond to no valid parent @@ -161,6 +162,8 @@ struct ingenic_cgu_clk_info { CGU_CLK_CUSTOM = BIT(7), } type; + unsigned long flags; + int parents[4]; union { From patchwork Thu Apr 28 16:44:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12831015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34AC4C433F5 for ; Thu, 28 Apr 2022 16:44:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350304AbiD1Qrq (ORCPT ); Thu, 28 Apr 2022 12:47:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350282AbiD1Qrk (ORCPT ); Thu, 28 Apr 2022 12:47:40 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24CCBB1AB0; Thu, 28 Apr 2022 09:44:24 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id o12-20020a1c4d0c000000b00393fbe2973dso4695701wmh.2; Thu, 28 Apr 2022 09:44:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+OlFWTbdzDsv9ToIL/R1210CLuDsQYdcda5qA/W19rg=; b=GbfNWAoyM2WevW9mfDQ6B0o1VRET7tZQdeALnKgHhzIXdqO2GH/F6b/gSelnw0iPJH zTqVqE7u662EulQa/xmQHrq9g0IQt4BHv/nFna4/zucTVpg6qBB2RBq8gU1Q5BgyLYOW yxjlFqYFozouqqROp8zejWKsmPSq908+Ryyv3FVbmEuVlcp8A5rVX73QcDcSduIGheyr XPQwVMmzDYjyWzdThF6euRPQjQzW/3ubwWUpX+xdEJdQ1+l5YIt2y9jM6/4p84UskSZP IWBO5kpAhR21fzktbxTuFi+ohIkcCc9zR90Ab8YEwLsSav5e4MVgA4fhy4JB/3IoXEX/ iKeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+OlFWTbdzDsv9ToIL/R1210CLuDsQYdcda5qA/W19rg=; b=s718pZuAkh5nBfGcZa6LR2Ep7x0I6c5TvWaU1kmDse76klA3OqWTLNZ3Dxq8nlMAzo b5zeMhq+Uwu0t2a0unEPRY0JxV0HOUpV9t0DEjW492xacVUZ6XELoCNCYwvC9VkEVz/K UHX2g1FiNL9JpJfEDd7EHtbbpnK9EQMeKSqAg1gaIK/UTVyIjE9+3/Bi4il8lABNr3kq vYAcox9Wrqzp1sgXkA1lZDi9+evmDNPNsl8QTW28yNYhNZ4cixcm9VQZwLkoARTINvPq R6erUJ578nhi+vAQ3EuVE0p5E95SLGBh6Oe4jYKuZB7PWAX8Y6dRrYmsqxli0iPyY/3f tSqQ== X-Gm-Message-State: AOAM531ay3jf6yqucYeLQ2HFMO6Y3INp2d2HbJ14isJ+jiuwb+5JtSGm T9r6v559Bg9fwWnKDCo1udY= X-Google-Smtp-Source: ABdhPJxGuFltFCqoZbiB2CsQt6fjOfYm865SzHsHBG1LG0V6RbJwHElh59p0lhayuwW11XVzzcDwLA== X-Received: by 2002:a7b:cb48:0:b0:394:b64:8b88 with SMTP id v8-20020a7bcb48000000b003940b648b88mr5624216wmj.183.1651164262619; Thu, 28 Apr 2022 09:44:22 -0700 (PDT) Received: from localhost (92.40.203.206.threembb.co.uk. [92.40.203.206]) by smtp.gmail.com with ESMTPSA id f189-20020a1c38c6000000b0038ff83b9792sm4453035wma.43.2022.04.28.09.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 09:44:22 -0700 (PDT) From: Aidan MacDonald To: sboyd@kernel.org, mturquette@baylibre.com, tsbogend@alpha.franken.de Cc: paulburton@kernel.org, paul@crapouillou.net, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/3] clk: ingenic: Mark critical clocks in Ingenic SoCs Date: Thu, 28 Apr 2022 17:44:53 +0100 Message-Id: <20220428164454.17908-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220428164454.17908-1-aidanmacdonald.0x0@gmail.com> References: <20220428164454.17908-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing calls clk_get() on these clocks. Gating the CPU clock hangs the processor, and gating memory makes external DRAM inaccessible. Normal kernel code can't hope to deal with either situation so those clocks have to be critical. The L2 cache is required only if caches are running, and could be gated if the kernel takes care to flush and disable caches before gating the clock. There's no mechanism to do this, and probably no reason to do it, so it's simpler to mark the L2 cache as critical. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- drivers/clk/ingenic/jz4725b-cgu.c | 10 ++++++++++ drivers/clk/ingenic/jz4740-cgu.c | 10 ++++++++++ drivers/clk/ingenic/jz4760-cgu.c | 10 ++++++++++ drivers/clk/ingenic/jz4770-cgu.c | 5 +++++ drivers/clk/ingenic/jz4780-cgu.c | 15 +++++++++++++++ drivers/clk/ingenic/x1000-cgu.c | 15 +++++++++++++++ drivers/clk/ingenic/x1830-cgu.c | 11 +++++++++++ 7 files changed, 76 insertions(+) diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c index 15d61793f53b..590e9c85cb25 100644 --- a/drivers/clk/ingenic/jz4725b-cgu.c +++ b/drivers/clk/ingenic/jz4725b-cgu.c @@ -87,6 +87,11 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + /* + * Disabling the CPU clock or any parent clocks will hang the + * system; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, @@ -114,6 +119,11 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { [JZ4725B_CLK_MCLK] = { "mclk", CGU_CLK_DIV, + /* + * Disabling MCLK or its parents will render DRAM + * inaccessible; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c index 43ffb62c42bb..3e0a30574ebb 100644 --- a/drivers/clk/ingenic/jz4740-cgu.c +++ b/drivers/clk/ingenic/jz4740-cgu.c @@ -102,6 +102,11 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + /* + * Disabling the CPU clock or any parent clocks will hang the + * system; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, @@ -129,6 +134,11 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { [JZ4740_CLK_MCLK] = { "mclk", CGU_CLK_DIV, + /* + * Disabling MCLK or its parents will render DRAM + * inaccessible; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c index 8fdd383560fb..ecd395ac8a28 100644 --- a/drivers/clk/ingenic/jz4760-cgu.c +++ b/drivers/clk/ingenic/jz4760-cgu.c @@ -143,6 +143,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { [JZ4760_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + /* + * Disabling the CPU clock or any parent clocks will hang the + * system; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, @@ -175,6 +180,11 @@ static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = { }, [JZ4760_CLK_MCLK] = { "mclk", CGU_CLK_DIV, + /* + * Disabling MCLK or its parents will render DRAM + * inaccessible; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4760_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 7ef91257630e..6ae1740367f9 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -149,6 +149,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_CCLK] = { "cclk", CGU_CLK_DIV, + /* + * Disabling the CPU clock or any parent clocks will hang the + * system; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index e357c228e0f1..b1dadc0a5e75 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -341,12 +341,22 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_CPU] = { "cpu", CGU_CLK_DIV, + /* + * Disabling the CPU clock or any parent clocks will hang the + * system; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 }, }, [JZ4780_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, + /* + * The L2 cache clock is critical if caches are enabled and + * disabling it or any parent clocks will hang the system. + */ + .flags = CLK_IS_CRITICAL, .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 }, }, @@ -380,6 +390,11 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { [JZ4780_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV, + /* + * Disabling DDR clock or its parents will render DRAM + * inaccessible; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c index 3c4d5a77ccbd..b2ce3fb83f54 100644 --- a/drivers/clk/ingenic/x1000-cgu.c +++ b/drivers/clk/ingenic/x1000-cgu.c @@ -251,6 +251,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, + /* + * Disabling the CPU clock or any parent clocks will hang the + * system; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR, 30 }, @@ -258,6 +263,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, + /* + * The L2 cache clock is critical if caches are enabled and + * disabling it or any parent clocks will hang the system. + */ + .flags = CLK_IS_CRITICAL, .parents = { X1000_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, @@ -290,6 +300,11 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = { [X1000_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + /* + * Disabling DDR clock or its parents will render DRAM + * inaccessible; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c index e01ec2dc7a1a..0fd46e50a513 100644 --- a/drivers/clk/ingenic/x1830-cgu.c +++ b/drivers/clk/ingenic/x1830-cgu.c @@ -225,6 +225,7 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_CPU] = { "cpu", CGU_CLK_DIV | CGU_CLK_GATE, + .flags = CLK_IS_CRITICAL, .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 }, .gate = { CGU_REG_CLKGR1, 15 }, @@ -232,6 +233,11 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_L2CACHE] = { "l2cache", CGU_CLK_DIV, + /* + * The L2 cache clock is critical if caches are enabled and + * disabling it or any parent clocks will hang the system. + */ + .flags = CLK_IS_CRITICAL, .parents = { X1830_CLK_CPUMUX, -1, -1, -1 }, .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 }, }, @@ -264,6 +270,11 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = { [X1830_CLK_DDR] = { "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + /* + * Disabling DDR clock or its parents will render DRAM + * inaccessible; mark it critical. + */ + .flags = CLK_IS_CRITICAL, .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 }, .mux = { CGU_REG_DDRCDR, 30, 2 }, .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 }, From patchwork Thu Apr 28 16:44:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 12831016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B417C4332F for ; Thu, 28 Apr 2022 16:44:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350309AbiD1Qrr (ORCPT ); Thu, 28 Apr 2022 12:47:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350298AbiD1Qrk (ORCPT ); Thu, 28 Apr 2022 12:47:40 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4D34B2471; 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[92.40.203.206]) by smtp.gmail.com with ESMTPSA id f189-20020a1c38c6000000b0038ff83b9792sm4453035wma.43.2022.04.28.09.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 09:44:23 -0700 (PDT) From: Aidan MacDonald To: sboyd@kernel.org, mturquette@baylibre.com, tsbogend@alpha.franken.de Cc: paulburton@kernel.org, paul@crapouillou.net, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 3/3] mips: ingenic: Do not manually reference the CPU clock Date: Thu, 28 Apr 2022 17:44:54 +0100 Message-Id: <20220428164454.17908-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220428164454.17908-1-aidanmacdonald.0x0@gmail.com> References: <20220428164454.17908-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org It isn't necessary to manually walk the device tree and enable the CPU clock anymore. The CPU and other necessary clocks are now flagged as critical in the clock driver, which accomplishes the same thing in a more declarative fashion. Signed-off-by: Aidan MacDonald Reviewed-by: Paul Cercueil --- arch/mips/generic/board-ingenic.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c index 3f44f14bdb33..c422bbc890ed 100644 --- a/arch/mips/generic/board-ingenic.c +++ b/arch/mips/generic/board-ingenic.c @@ -131,36 +131,10 @@ static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = { static int __init ingenic_pm_init(void) { - struct device_node *cpu_node; - struct clk *cpu0_clk; - int ret; - if (boot_cpu_type() == CPU_XBURST) { if (IS_ENABLED(CONFIG_PM_SLEEP)) suspend_set_ops(&ingenic_pm_ops); _machine_halt = ingenic_halt; - - /* - * Unconditionally enable the clock for the first CPU. - * This makes sure that the PLL that feeds the CPU won't be - * stopped while the kernel is running. - */ - cpu_node = of_get_cpu_node(0, NULL); - if (!cpu_node) { - pr_err("Unable to get CPU node\n"); - } else { - cpu0_clk = of_clk_get(cpu_node, 0); - if (IS_ERR(cpu0_clk)) { - pr_err("Unable to get CPU0 clock\n"); - return PTR_ERR(cpu0_clk); - } - - ret = clk_prepare_enable(cpu0_clk); - if (ret) { - pr_err("Unable to enable CPU0 clock\n"); - return ret; - } - } } return 0;