From patchwork Thu Apr 28 22:10:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831286 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB486138F for ; Thu, 28 Apr 2022 22:10:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183816; x=1682719816; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wTOhNnGM4fH3f48hOp4pX+ub4ekvi2i7bAZMl9dNetU=; b=Eys17iY6pkZR7sJ1hg4r40bSrnMooKU8KxOLz3d2Hq/tMdPR5tEXbvRp G7snrdNP9ll9G+X8taLP+x1bBU/GhBwQjqEBfYv2HZUtOJ0gbo9mTgSsT FVxIFlemJ2olu1Q00aeSfDgwPjO4fUo7VP/Sqd+XXjwViTvmeWyxIRQ38 RYuc7DcoZwpgOAyLk8sShZ4+TDW1Nc08ZqyI25jdL+kYR1Q59rH5f8YdT Mg8pkfWFCyDJOY0OggK2PDHombRgY7m6tIe/q3fexjnaLw9ThaJo+AQqC 9G/IHpXmqCTgTvp9Od7o2DX52/pGHBlGbBV+UoelJ21NgnAM8uDYb+m7o Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="265967584" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="265967584" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:06 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="534122457" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:06 -0700 Subject: [ndctl PATCH 01/10] build: Move utility helpers to libutil.a From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:05 -0700 Message-ID: <165118380572.1676208.16232543117821121022.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Stop listing util/json.c and util/log.c per command, just add them to the common libutil.a object. Signed-off-by: Dan Williams --- cxl/meson.build | 2 -- daxctl/meson.build | 1 - ndctl/meson.build | 2 -- util/meson.build | 2 ++ 4 files changed, 2 insertions(+), 5 deletions(-) diff --git a/cxl/meson.build b/cxl/meson.build index 87cfea73e40b..671c8e1626ef 100644 --- a/cxl/meson.build +++ b/cxl/meson.build @@ -3,8 +3,6 @@ cxl_src = [ 'list.c', 'port.c', 'memdev.c', - '../util/json.c', - '../util/log.c', 'json.c', 'filter.c', ] diff --git a/daxctl/meson.build b/daxctl/meson.build index 8474d02f2c0d..8f27dd71b965 100644 --- a/daxctl/meson.build +++ b/daxctl/meson.build @@ -4,7 +4,6 @@ daxctl_src = [ 'list.c', 'migrate.c', 'device.c', - '../util/json.c', 'json.c', 'filter.c', ] diff --git a/ndctl/meson.build b/ndctl/meson.build index c7889af36084..050d5769c384 100644 --- a/ndctl/meson.build +++ b/ndctl/meson.build @@ -6,11 +6,9 @@ ndctl_src = [ 'check.c', 'region.c', 'dimm.c', - '../util/log.c', '../daxctl/filter.c', 'filter.c', 'list.c', - '../util/json.c', '../daxctl/json.c', 'json.c', 'json-smart.c', diff --git a/util/meson.build b/util/meson.build index 695037a924b9..a6ded7ee1473 100644 --- a/util/meson.build +++ b/util/meson.build @@ -3,6 +3,8 @@ util = static_library('util', [ 'parse-configs.c', 'usage.c', 'size.c', + 'json.c', + 'log.c', 'main.c', 'help.c', 'strbuf.c', From patchwork Thu Apr 28 22:10:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831285 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0321E138F for ; Thu, 28 Apr 2022 22:10:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183812; x=1682719812; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RFAyZN2/4uvSqxhe+/wCCpJLam8t6Vv9GJQX9Qczqpo=; b=jWqcWTSZcKg2LmqWMIby6LqXNVsUC+VMVyNOi5klGhrxzoAOMMq8Ekp3 5Y035rRTdPBwyocVcaDSu1HQ5dRTozQXFANFEnCx6MycQDZHw655cJuNk lnRRfF8GhZ1a1/jUaD8vGcCxu+h8Xgw6Sb4R52ZqbzVytGY7nqcZYf57z rXxQhtQ13dEju+wS1faW76tazIG34STvx5oq+T+ZIvT5YoFbEtrjheBl7 y2j/d7hRavUJ5ZZK56K2ByyekcJcuyStUQDyvJnkt94SO05+VYAhSAJIb 0C6QFA+/4zBgtqZqF3X5TrGUrk+7A74Z1otaaN41nLHYhFAkiYXjuMRVj g==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="266597231" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="266597231" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:11 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="618356191" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:11 -0700 Subject: [ndctl PATCH 02/10] util: Use SZ_ size macros in display size From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:11 -0700 Message-ID: <165118381109.1676208.8857362319985041575.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In preparation for adding "Terabyte" support, cleanup the "1024" multiplication with the SZ_* macros. Signed-off-by: Dan Williams --- util/json.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/util/json.c b/util/json.c index f8cc81f6e706..ebdf8d9eedd9 100644 --- a/util/json.c +++ b/util/json.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -27,24 +28,24 @@ static int display_size(struct json_object *jobj, struct printbuf *pbuf, * If prefix == JEDEC, we mean prefixes like kilo,mega,giga etc. */ - if (bytes < 5000*1024) + if (bytes < 5000*SZ_1K) snprintf(buf, sizeof(buf), "%lld", bytes); else { /* IEC */ - if (bytes < 2*1024LL*1024LL*1024LL) { - long cMiB = (bytes * 200LL / (1LL<<20) +1) /2; + if (bytes < 2L*SZ_1G) { + long cMiB = (bytes * 200LL / SZ_1M+1) /2; c = snprintf(buf, sizeof(buf), "\"%ld.%02ld MiB", cMiB/100 , cMiB % 100); } else { - long cGiB = (bytes * 200LL / (1LL<<30) +1) /2; + long cGiB = (bytes * 200LL / SZ_1G+1) /2; c = snprintf(buf, sizeof(buf), "\"%ld.%02ld GiB", cGiB/100 , cGiB % 100); } /* JEDEC */ - if (bytes < 2*1024LL*1024LL*1024LL) { + if (bytes < 2L*SZ_1G) { long cMB = (bytes / (1000000LL / 200LL) + 1) / 2; snprintf(buf + c, sizeof(buf) - c, " (%ld.%02ld MB)\"", From patchwork Thu Apr 28 22:10:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831287 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 964421398 for ; Thu, 28 Apr 2022 22:10:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183817; x=1682719817; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nfv2zG5A8V35hocGwBFBf7FQQxSyBEnkJuli4Ie8N4s=; b=AwjWn+JUs2fHCziwcFzos9M8wjlxXHH0BvsQHY5kBCki55tZ1G0F9woH dyzZ/SSzp/uQUn26HPJan3GyyfhjMFQH3kZllGj7f6um9Qw1J+mjmeKmZ YVe7HoDfgagKiv3gANnH1kL4v1E0Pw1JcVIdjRW3UWvDnA1Jhz25xC5bH jZxRLln2nVrKNY1N0rpL5+sBM9ZNdmPO6b/66MmNAUls743Q3J0KgMek0 3hbkZ+ggfLMTlK7GSbi5YFawxqdxg7x1mqOPMMdxiBdOnbrxaa5G35qca sfmnqePwaIi7mHzEHFRLZDC/2sIGp5eBsYAwJrmiHQXDtYQJZz7TY8vU9 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="264028222" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="264028222" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:16 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="565821458" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:16 -0700 Subject: [ndctl PATCH 03/10] util: Pretty print terabytes From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:16 -0700 Message-ID: <165118381648.1676208.1686584406206186723.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CXL capacities are such that gigabytes are too small of a unit for displaying capacities. Add terabyte support to the display_size() helper. Signed-off-by: Dan Williams --- util/json.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/util/json.c b/util/json.c index ebdf8d9eedd9..1d5c6bc7822e 100644 --- a/util/json.c +++ b/util/json.c @@ -37,11 +37,16 @@ static int display_size(struct json_object *jobj, struct printbuf *pbuf, c = snprintf(buf, sizeof(buf), "\"%ld.%02ld MiB", cMiB/100 , cMiB % 100); - } else { + } else if (bytes < 2*SZ_1T) { long cGiB = (bytes * 200LL / SZ_1G+1) /2; c = snprintf(buf, sizeof(buf), "\"%ld.%02ld GiB", cGiB/100 , cGiB % 100); + } else { + long cTiB = (bytes * 200LL / SZ_1T+1) /2; + + c = snprintf(buf, sizeof(buf), "\"%ld.%02ld TiB", + cTiB/100 , cTiB % 100); } /* JEDEC */ @@ -50,12 +55,18 @@ static int display_size(struct json_object *jobj, struct printbuf *pbuf, snprintf(buf + c, sizeof(buf) - c, " (%ld.%02ld MB)\"", cMB/100, cMB % 100); - } else { + } else if (bytes < 2*SZ_1T) { long cGB = (bytes / (1000000000LL/200LL) + 1) / 2; snprintf(buf + c, sizeof(buf) - c, " (%ld.%02ld GB)\"", cGB/100 , cGB % 100); + } else { + long cTB = (bytes / (1000000000000LL/200LL) + 1) / 2; + + snprintf(buf + c, sizeof(buf) - c, " (%ld.%02ld TB)\"", + cTB/100 , cTB % 100); } + } return printbuf_memappend(pbuf, buf, strlen(buf)); From patchwork Thu Apr 28 22:10:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831288 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5C2F184C for ; Thu, 28 Apr 2022 22:10:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183823; x=1682719823; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eWAKZOCEiukJwwwO0K/9Rdi7TNhtTLDtQjOlHQTdGi0=; b=ggK5JBwSYT2pOZGy6yPnnKCKOZ3CNhQAnK7Z57ZII1vzMnzXu2OKJrb7 AxzNLepWtDVj4JOHiV7KCUN3YdrQWg4KgFCWP8L/EXS7EOByVI+PvDrkn N9FRRv0GzLF/y7jBpXGZ/2pG9TiZXu83yfgCxSr1ATMw20Cg5P/ra9zK6 RYx7b1Ce8qLeLGYRImo2eve+VeLXHsvHTJdKG/WMWkxriub5VwFpLtC+8 wnYWO53+7zlp6xOjJKoWzKCFTsBprDSGjZRUcoO5XjnACtW//3hGxRNtN jaadd4ouzJSBqEoVb95q99+gytJQLRoE14LDkKvbahri175QVaGV07B6k A==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="291604848" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="291604848" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:23 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="808817284" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:22 -0700 Subject: [ndctl PATCH 04/10] cxl/port: Fix disable-port man page From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:22 -0700 Message-ID: <165118382203.1676208.17234717366569348622.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The man page was copied from the enable-port. Fix up some enable-port leftovers, and duplicated --endpoint option description. Signed-off-by: Dan Williams --- Documentation/cxl/cxl-disable-port.txt | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/Documentation/cxl/cxl-disable-port.txt b/Documentation/cxl/cxl-disable-port.txt index de13c07d149b..ac56f20e8e6d 100644 --- a/Documentation/cxl/cxl-disable-port.txt +++ b/Documentation/cxl/cxl-disable-port.txt @@ -5,7 +5,7 @@ cxl-disable-port(1) NAME ---- -cxl-disable-port - activate / hot-add a given CXL port +cxl-disable-port - disable / hot-remove a given CXL port and descendants SYNOPSIS -------- @@ -22,7 +22,6 @@ OPTIONS Toggle from treating the port arguments as Switch Port identifiers to Endpoint Port identifiers. - -f:: --force:: DANGEROUS: Override the safety measure that blocks attempts to disable a @@ -31,9 +30,6 @@ OPTIONS firmware and disabling an active device is akin to force removing memory from a running system. - Toggle from treating the port arguments as Switch Port identifiers to - Endpoint Port identifiers. - --debug:: If the cxl tool was built with debug disabled, turn on debug messages. From patchwork Thu Apr 28 22:10:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831289 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD517184C for ; Thu, 28 Apr 2022 22:10:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183827; x=1682719827; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gN39W8hJNmHAkE5uIG1rVcKW1lQE+KnARB8xkz+H97Y=; b=h3Tr4UonMtvrTMiQazkxOonfvdItFxKtFx4HKAHLYHiP7i7JLwfppKR8 8Hy5nr6LvNLJQdN2auKhwC/C1/EkR8akbkPrJ+eoDOTO/jW/4sci1BxH2 ayss6+z8kie2rYfNBlVutGSCeW88AlPTlAwcfV+vqx4FZgErzK7WNFshz 8sXkjEryduofXpoN7eCeXyfEc39F7WZl6KZdvJS6qT29XRcGqaldumcYu he146R4m7XZRb4Em2VGtfJaD7iXF9LxRuE/EWPzPKNvcb6ss/Q6ZtXz6D l8CQTpouwz4k5f1h4EXx9PebwIYdv0nLHyP3GzlWDIC1c1TJ+RsFKco5m A==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="326933519" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="326933519" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:27 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="534122595" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:27 -0700 Subject: [ndctl PATCH 05/10] cxl/bus: Add bus disable support From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:27 -0700 Message-ID: <165118382738.1676208.16851880881648171660.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Route requests to disable the root back to unbinding the platform firmware device, ACPI0017 for ACPI.CXL platforms. Signed-off-by: Dan Williams --- Documentation/cxl/cxl-disable-bus.txt | 37 ++++++++ Documentation/cxl/lib/libcxl.txt | 12 ++ Documentation/cxl/meson.build | 1 cxl/builtin.h | 1 cxl/bus.c | 159 +++++++++++++++++++++++++++++++++ cxl/cxl.c | 1 cxl/filter.c | 3 - cxl/filter.h | 1 cxl/lib/libcxl.c | 15 +++ cxl/lib/libcxl.sym | 1 cxl/libcxl.h | 1 cxl/meson.build | 1 12 files changed, 231 insertions(+), 2 deletions(-) create mode 100644 Documentation/cxl/cxl-disable-bus.txt create mode 100644 cxl/bus.c diff --git a/Documentation/cxl/cxl-disable-bus.txt b/Documentation/cxl/cxl-disable-bus.txt new file mode 100644 index 000000000000..65f695cd06c8 --- /dev/null +++ b/Documentation/cxl/cxl-disable-bus.txt @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +cxl-disable-bus(1) +=================== + +NAME +---- +cxl-disable-bus - Shutdown an entire tree of CXL devices + +SYNOPSIS +-------- +[verse] +'cxl disable-bus' [..] [] + +For test and debug scenarios, disable a CXL bus and any associated +memory devices from CXL.mem operations. + +OPTIONS +------- +-f:: +--force:: + DANGEROUS: Override the safety measure that blocks attempts to disable a + bus if the tool determines a descendent memdev is in active usage. + Recall that CXL memory ranges might have been established by platform + firmware and disabling an active device is akin to force removing memory + from a running system. + +--debug:: + If the cxl tool was built with debug disabled, turn on debug + messages. + + +include::../copyright.txt[] + +SEE ALSO +-------- +linkcxl:cxl-disable-port[1] diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt index 7b223cbcac3f..f8f0e668ab59 100644 --- a/Documentation/cxl/lib/libcxl.txt +++ b/Documentation/cxl/lib/libcxl.txt @@ -216,6 +216,18 @@ discovery order. The possible provider names are 'ACPI.CXL' and the kernel device names that are subject to change based on discovery order. +=== BUS: Control +---- +int cxl_bus_disable_invalidate(struct cxl_bus *bus); +---- + +An entire CXL topology can be torn down with this API. Like other +_invalidate APIs callers must assume that all library objects have been +freed. This one goes one step further and also frees the @bus argument. +This may crash the system and is only useful in kernel driver +development scenarios. + + PORTS ----- CXL ports track the PCIe hierarchy between a platform firmware CXL root diff --git a/Documentation/cxl/meson.build b/Documentation/cxl/meson.build index e927644a3826..974a5a41d169 100644 --- a/Documentation/cxl/meson.build +++ b/Documentation/cxl/meson.build @@ -34,6 +34,7 @@ cxl_manpages = [ 'cxl-disable-memdev.txt', 'cxl-enable-port.txt', 'cxl-disable-port.txt', + 'cxl-disable-bus.txt', 'cxl-set-partition.txt', ] diff --git a/cxl/builtin.h b/cxl/builtin.h index 7bbad98f67ac..a437bc314a30 100644 --- a/cxl/builtin.h +++ b/cxl/builtin.h @@ -15,4 +15,5 @@ int cmd_enable_memdev(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_disable_port(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_enable_port(int argc, const char **argv, struct cxl_ctx *ctx); int cmd_set_partition(int argc, const char **argv, struct cxl_ctx *ctx); +int cmd_disable_bus(int argc, const char **argv, struct cxl_ctx *ctx); #endif /* _CXL_BUILTIN_H_ */ diff --git a/cxl/bus.c b/cxl/bus.c new file mode 100644 index 000000000000..33212951a404 --- /dev/null +++ b/cxl/bus.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2020-2022 Intel Corporation. All rights reserved. */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "filter.h" + +static struct parameters { + bool debug; + bool force; +} param; + +static struct log_ctx bl; + +#define BASE_OPTIONS() \ +OPT_BOOLEAN(0, "debug", ¶m.debug, "turn on debug") + +#define DISABLE_OPTIONS() \ +OPT_BOOLEAN('f', "force", ¶m.force, \ + "DANGEROUS: override active memdev safety checks") + +static const struct option disable_options[] = { + BASE_OPTIONS(), + DISABLE_OPTIONS(), + OPT_END(), +}; + +static int action_disable(struct cxl_bus *bus) +{ + const char *devname = cxl_bus_get_devname(bus); + struct cxl_ctx *ctx = cxl_bus_get_ctx(bus); + struct cxl_memdev *memdev; + int active_memdevs = 0; + + cxl_memdev_foreach(ctx, memdev) + if (bus == cxl_memdev_get_bus(memdev)) + active_memdevs++; + + if (active_memdevs && !param.force) { + /* + * TODO: actually detect rather than assume active just + * because the memdev is enabled + */ + log_err(&bl, + "%s hosts %d memdev%s which %s part of an active region\n", + devname, active_memdevs, active_memdevs > 1 ? "s" : "", + active_memdevs > 1 ? "are" : "is"); + log_err(&bl, + "See 'cxl list -M -b %s' to see impacted device%s\n", + devname, active_memdevs > 1 ? "s" : ""); + return -EBUSY; + } + + return cxl_bus_disable_invalidate(bus); +} + +static struct cxl_bus *find_cxl_bus(struct cxl_ctx *ctx, const char *ident) +{ + struct cxl_bus *bus; + + cxl_bus_foreach(ctx, bus) + if (util_cxl_bus_filter(bus, ident)) + return bus; + return NULL; +} + +static int bus_action(int argc, const char **argv, struct cxl_ctx *ctx, + int (*action)(struct cxl_bus *bus), + const struct option *options, const char *usage) +{ + int i, rc = 0, count = 0, err = 0; + const char * const u[] = { + usage, + NULL + }; + unsigned long id; + + log_init(&bl, "cxl bus", "CXL_PORT_LOG"); + argc = parse_options(argc, argv, options, u, 0); + + if (argc == 0) + usage_with_options(u, options); + for (i = 0; i < argc; i++) { + if (strcmp(argv[i], "all") == 0) { + argv[0] = "all"; + argc = 1; + break; + } + + if (sscanf(argv[i], "root%lu", &id) == 1) + continue; + if (sscanf(argv[i], "%lu", &id) == 1) + continue; + + log_err(&bl, "'%s' is not a valid bus identifer\n", argv[i]); + err++; + } + + if (err == argc) { + usage_with_options(u, options); + return -EINVAL; + } + + if (param.debug) { + cxl_set_log_priority(ctx, LOG_DEBUG); + bl.log_priority = LOG_DEBUG; + } else + bl.log_priority = LOG_INFO; + + rc = 0; + err = 0; + count = 0; + + for (i = 0; i < argc; i++) { + struct cxl_bus *bus; + + bus = find_cxl_bus(ctx, argv[i]); + if (!bus) { + log_dbg(&bl, "bus: %s not found\n", argv[i]); + continue; + } + + log_dbg(&bl, "run action on bus: %s\n", + cxl_bus_get_devname(bus)); + rc = action(bus); + if (rc == 0) + count++; + else if (rc && !err) + err = rc; + } + rc = err; + + /* + * count if some actions succeeded, 0 if none were attempted, + * negative error code otherwise. + */ + if (count > 0) + return count; + return rc; +} + + int cmd_disable_bus(int argc, const char **argv, struct cxl_ctx *ctx) + { + int count = bus_action( + argc, argv, ctx, action_disable, disable_options, + "cxl disable-bus [..] []"); + + log_info(&bl, "disabled %d bus%s\n", count >= 0 ? count : 0, + count > 1 ? "s" : ""); + return count >= 0 ? 0 : EXIT_FAILURE; + } diff --git a/cxl/cxl.c b/cxl/cxl.c index ab4bbeccaa76..aa4ce61b7c87 100644 --- a/cxl/cxl.c +++ b/cxl/cxl.c @@ -69,6 +69,7 @@ static struct cmd_struct commands[] = { { "disable-port", .c_fn = cmd_disable_port }, { "enable-port", .c_fn = cmd_enable_port }, { "set-partition", .c_fn = cmd_set_partition }, + { "disable-bus", .c_fn = cmd_disable_bus }, }; int main(int argc, const char **argv) diff --git a/cxl/filter.c b/cxl/filter.c index b3396426dda8..c6ab9eb58124 100644 --- a/cxl/filter.c +++ b/cxl/filter.c @@ -176,8 +176,7 @@ util_cxl_decoder_filter_by_port(struct cxl_decoder *decoder, const char *ident, return NULL; } -static struct cxl_bus *util_cxl_bus_filter(struct cxl_bus *bus, - const char *__ident) +struct cxl_bus *util_cxl_bus_filter(struct cxl_bus *bus, const char *__ident) { char *ident, *save; const char *arg; diff --git a/cxl/filter.h b/cxl/filter.h index 697b7779c08e..955794366d5c 100644 --- a/cxl/filter.h +++ b/cxl/filter.h @@ -41,6 +41,7 @@ enum cxl_port_filter_mode { struct cxl_port *util_cxl_port_filter(struct cxl_port *port, const char *ident, enum cxl_port_filter_mode mode); +struct cxl_bus *util_cxl_bus_filter(struct cxl_bus *bus, const char *__ident); struct cxl_endpoint *util_cxl_endpoint_filter(struct cxl_endpoint *endpoint, const char *__ident); struct cxl_target *util_cxl_target_filter_by_memdev(struct cxl_target *target, diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 59e164464987..0e8dd20e3c47 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -556,6 +556,21 @@ static void bus_invalidate(struct cxl_bus *bus) cxl_flush(ctx); } +CXL_EXPORT int cxl_bus_disable_invalidate(struct cxl_bus *bus) +{ + struct cxl_ctx *ctx = cxl_bus_get_ctx(bus); + struct cxl_port *port = cxl_bus_get_port(bus); + int rc; + + rc = util_unbind(port->uport, ctx); + if (rc) + return rc; + + free_bus(bus, &ctx->buses); + cxl_flush(ctx); + return 0; +} + CXL_EXPORT int cxl_memdev_disable_invalidate(struct cxl_memdev *memdev) { struct cxl_ctx *ctx = cxl_memdev_get_ctx(memdev); diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index aab1112a91d8..dffcb60b8dd0 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -86,6 +86,7 @@ global: cxl_bus_get_id; cxl_bus_get_port; cxl_bus_get_ctx; + cxl_bus_disable_invalidate; cxl_port_get_first; cxl_port_get_next; cxl_port_get_devname; diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 0063d31ab398..0007f4d9bcee 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -73,6 +73,7 @@ const char *cxl_bus_get_devname(struct cxl_bus *bus); int cxl_bus_get_id(struct cxl_bus *bus); struct cxl_port *cxl_bus_get_port(struct cxl_bus *bus); struct cxl_ctx *cxl_bus_get_ctx(struct cxl_bus *bus); +int cxl_bus_disable_invalidate(struct cxl_bus *bus); #define cxl_bus_foreach(ctx, bus) \ for (bus = cxl_bus_get_first(ctx); bus != NULL; \ diff --git a/cxl/meson.build b/cxl/meson.build index 671c8e1626ef..d63dcb12eec2 100644 --- a/cxl/meson.build +++ b/cxl/meson.build @@ -2,6 +2,7 @@ cxl_src = [ 'cxl.c', 'list.c', 'port.c', + 'bus.c', 'memdev.c', 'json.c', 'filter.c', From patchwork Thu Apr 28 22:10:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831290 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3984D3D8D for ; Thu, 28 Apr 2022 22:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183833; x=1682719833; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hrj0oSqW1mU02KYyQv9rVPsdjuM/cGHNMk60O/cQWA4=; b=KOO9DR0+r/pl6yDN8ikt2dVQ9e0JBl8tl436A4f5MFvXbXggby7KXMcU W05okUnxI3q/6VwgmRMq+sxP8ke6nDhbouhj+xroQ186teyyj+mtdS0w2 wkDlhEHGWNZLKvsBZyaJJkLUa6lKZG5JZSb0DpNR2/qn+aIhI6vvzxsZN 2Q8lqDwi29Hof1t2FZ9MpQzsDTy7Wgmk4hLd/9TeSG3/6PuTJTN6rXkPN HAI/IzsqQEoSOjZWHF32/P0949zoKIimkekELcel3lLkFG+VWZCnNfwTG GuAb/Nvj6m7sW0okJJ/Vlks8L/Br5Ev7MaG55Y3z0Gk88vkkW4jkylya5 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="265289558" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="265289558" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:32 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="731735541" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:32 -0700 Subject: [ndctl PATCH 06/10] cxl/list: Auto-enable 'single' mode for port listings From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:32 -0700 Message-ID: <165118383246.1676208.2097194779584921177.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The --single parameter instructs the filter code to gate listing of ancestor ports. However, that behavior can be inferred by attempts to list a port without the --ports option, i.e. make: cxl list -p $port ...equivalent to: cxl list -P -S -p $port Signed-off-by: Dan Williams --- cxl/list.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cxl/list.c b/cxl/list.c index 1e9d441190a0..940782d33a10 100644 --- a/cxl/list.c +++ b/cxl/list.c @@ -104,6 +104,7 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx) error("please specify entities to list, e.g. using -m/-M\n"); usage_with_options(u, options); } + param.single = true; } log_init(¶m.ctx, "cxl list", "CXL_LIST_LOG"); From patchwork Thu Apr 28 22:10:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831291 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58FAE3D8D for ; Thu, 28 Apr 2022 22:10:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183838; x=1682719838; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=szNK7NyLKQ9MBHYyKQS30kvZW9aBafZ+FwCwnr+bNSM=; b=fXSPAJuogO+FRQ2k1q9ZerizsTDheMFPbYhT0SfY953TeB4Styii4T8r HY/MtqpJBg3OR6/f9yu/USppsiK2qkkqG8Z3rgkIVJL6B+y9jSjmX4pH+ WY/W1GIsIpf53EjRV/QkELYWog3gUQdhBrt7Ykm0nKbX7QnfxSEyuQJuE t14yxcsTPbEpfkx04XrmTJnRcjLjzY0B5G+a/AfTSbogdUqbfp+Bg8bRT TrVjjgiiPd+6qh8mYz1v27H76gFuTq/iUz2KeNOvsobnCafffYey7oDhz 0BuTMW2Db19YkhqZxYExyYIc2gLIgXEVYlJLTrk/0/qmLsfZXRTG2O3iR Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="352871328" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="352871328" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:37 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="808817336" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:37 -0700 Subject: [ndctl PATCH 07/10] cxl/memdev: Fix bus_invalidate() crash From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:37 -0700 Message-ID: <165118383756.1676208.5717187278816036969.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 bus_invalidate() attempts to limit the invalidation of memdevs to a single bus scope. However, the ordering of bus_invalidate() leads to a use after free. Unconditionally invalidate memdevs (disconnect memdevs from their endpoints) and resotre on next lookup. Otherwise the following command results in the following backtrace with cxl_test: cxl disable-memdev 5,1 --force #2 0x00007ffff7fb97d4 in snprintf (__fmt=0x7ffff7fbc3ed "%s/driver", __n=98, __s=0x574d545619f7bae2 ) at /usr/include/bits/stdio2.h:71 #3 cxl_port_is_enabled (port=port@entry=0x422eb0) at ../cxl/lib/libcxl.c:1379 #4 0x00007ffff7fb99a9 in cxl_port_get_bus (port=0x422eb0) at ../cxl/lib/libcxl.c:1339 #5 0x00007ffff7fba3d0 in bus_invalidate (bus=bus@entry=0x421740) at ../cxl/lib/libcxl.c:549 #6 0x00007ffff7fba4e7 in cxl_memdev_disable_invalidate (memdev=0x416fd0) at ../cxl/lib/libcxl.c:596 #7 0x000000000040624e in memdev_action (argc=, argv=, ctx=0x4152a0, action=action@entry=0x406b70 , options=options@entry=0x40fca0 , usage=usage@entry=0x40f4b0 "cxl disable-memdev [..] []") at ../cxl/memdev.c:506 #8 0x0000000000406d57 in cmd_disable_memdev (argc=, argv=, Signed-off-by: Dan Williams --- cxl/lib/libcxl.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 0e8dd20e3c47..374b0f13905a 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -546,8 +546,7 @@ static void bus_invalidate(struct cxl_bus *bus) * indeterminate, delete them all and start over. */ cxl_memdev_foreach(ctx, memdev) - if (cxl_memdev_get_bus(memdev) == bus) - memdev->endpoint = NULL; + memdev->endpoint = NULL; bus_port = cxl_bus_get_port(bus); list_for_each_safe(&bus_port->child_ports, port, _p, list) From patchwork Thu Apr 28 22:10:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831292 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87BF43D84 for ; Thu, 28 Apr 2022 22:10:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183843; x=1682719843; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NkAqIlYQJgJtxA35ufdp9ayM4/vxjLMZkUQ9nZovAmA=; b=Bivu7Zn3EU1Y8uyt0FdDFWHJ5KREzhEnG7OFqXcEXbXYe2Fn9PoKtXt4 Qb5yx23U0Pw9rX3KMPhYX8eTvsvdoDu+ccoAKdVy7yNHMFQYqQfYhcdGW kpMfQR2phamsyO7kZxkaCTq7vJ0Ns1NAZrDTxLQDlaUX4uIeZjBLbhNIF /BHF7Ww6N1OgTdtu/hIkLgwutpCLjL/iZtoCwnDfPy+MuxR7/pRWSINvb nqp+UcaGcVeRHwtmcFeeZTanZNaCVFMwmdGdRsBV9kPjEy7TpRRUgEQRo XpS9MineKiYlvtSHV2kE2gYsj7hjrwuoZemrFNcA8bnijQdgWn1nsjQYc A==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="352871336" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="352871336" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:43 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="629758881" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:43 -0700 Subject: [ndctl PATCH 08/10] cxl/list: Add support for filtering by host identifiers From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:42 -0700 Message-ID: <165118384289.1676208.4779565283924668304.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Accept host device names as valid filters for memdevs, ports, and endpoints. # cxl list -u -m 7 { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } # cxl list -u -m cxl_mem.6 { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } Signed-off-by: Dan Williams --- cxl/filter.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/cxl/filter.c b/cxl/filter.c index c6ab9eb58124..66fd7420144a 100644 --- a/cxl/filter.c +++ b/cxl/filter.c @@ -73,6 +73,9 @@ struct cxl_endpoint *util_cxl_endpoint_filter(struct cxl_endpoint *endpoint, if (strcmp(arg, cxl_endpoint_get_devname(endpoint)) == 0) break; + + if (strcmp(arg, cxl_endpoint_get_host(endpoint)) == 0) + break; } free(ident); @@ -116,6 +119,9 @@ static struct cxl_port *__util_cxl_port_filter(struct cxl_port *port, if (strcmp(arg, cxl_port_get_devname(port)) == 0) break; + + if (strcmp(arg, cxl_port_get_host(port)) == 0) + break; } free(ident); @@ -303,6 +309,9 @@ struct cxl_memdev *util_cxl_memdev_filter(struct cxl_memdev *memdev, if (strcmp(name, cxl_memdev_get_devname(memdev)) == 0) break; + + if (strcmp(name, cxl_memdev_get_host(memdev)) == 0) + break; } free(ident); From patchwork Thu Apr 28 22:10:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831293 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9B9F3D84 for ; Thu, 28 Apr 2022 22:10:49 +0000 (UTC) DKIM-Signature: v=1; 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28 Apr 2022 15:10:48 -0700 Subject: [ndctl PATCH 09/10] cxl/port: Relax port identifier validation From: Dan Williams To: vishal.l.verma@intel.com Cc: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:48 -0700 Message-ID: <165118384845.1676208.7570620216888371408.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Now that util_cxl_port_filter() accepts port host identifiers it is no longer possible to pre-validate that the port arguments follow the "port%d" format. Instead, let all inputs through and warn if the filter fails to identify a port. Signed-off-by: Dan Williams --- cxl/port.c | 30 ++++-------------------------- 1 file changed, 4 insertions(+), 26 deletions(-) diff --git a/cxl/port.c b/cxl/port.c index 46a8f32df8e1..89f3916d85aa 100644 --- a/cxl/port.c +++ b/cxl/port.c @@ -145,7 +145,6 @@ static int port_action(int argc, const char **argv, struct cxl_ctx *ctx, usage, NULL }; - unsigned long id; log_init(&pl, "cxl port", "CXL_PORT_LOG"); argc = parse_options(argc, argv, options, u, 0); @@ -153,31 +152,10 @@ static int port_action(int argc, const char **argv, struct cxl_ctx *ctx, if (argc == 0) usage_with_options(u, options); for (i = 0; i < argc; i++) { - const char *fmt; - if (strcmp(argv[i], "all") == 0) { argc = 1; break; } - - if (param.endpoint) - fmt = "endpoint%lu"; - else - fmt = "port%lu"; - - if (sscanf(argv[i], fmt, &id) == 1) - continue; - if (sscanf(argv[i], "%lu", &id) == 1) - continue; - - log_err(&pl, "'%s' is not a valid %s identifer\n", argv[i], - param.endpoint ? "endpoint" : "port"); - err++; - } - - if (err == argc) { - usage_with_options(u, options); - return -EINVAL; } if (param.debug) { @@ -187,7 +165,6 @@ static int port_action(int argc, const char **argv, struct cxl_ctx *ctx, pl.log_priority = LOG_INFO; rc = 0; - err = 0; count = 0; for (i = 0; i < argc; i++) { @@ -198,15 +175,16 @@ static int port_action(int argc, const char **argv, struct cxl_ctx *ctx, endpoint = find_cxl_endpoint(ctx, argv[i]); if (!endpoint) { - log_dbg(&pl, "endpoint: %s not found\n", - argv[i]); + log_notice(&pl, "endpoint: %s not found\n", + argv[i]); continue; } port = cxl_endpoint_get_port(endpoint); } else { port = find_cxl_port(ctx, argv[i]); if (!port) { - log_dbg(&pl, "port: %s not found\n", argv[i]); + log_notice(&pl, "port: %s not found\n", + argv[i]); continue; } } From patchwork Thu Apr 28 22:10:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 12831294 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93F4D3D60 for ; Thu, 28 Apr 2022 22:10:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651183854; x=1682719854; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6EmxZJQM6gbeuuBnZcbUrwJkT+T3QCR3Fl3Sx8kLU8s=; b=gZGh6vS+aG6qlZB5U09aCtCtFZqujPAoGa0qumhxeq72UHWaybK/ZvQP YahmTkRPVz5ouPMq+KPeFoJTPGkfRMx4qdREUsA0WVyXNjOAkYCqzaDHW C89sMLFXAz77dEgksFvKKG4vaC6+4tVPz55T2j1JwQoLlAki1DHJmJSNL qk/MF+XvkIzsjdZ5AQaG1S1X8Fw8oNr2FVGb8JsXQPG1uoMP/xCScd2Ol Y+kpvk+mx7eL0UKYyypAxnUfGj7P2yfTZ3AyPjOzERAJMqoIKFYqGo1rb 5wYBKWZ5km8vFT4u0I7l1BfioJ3VSsw86RMY+zTMV3Ud/LKtzPTKtIK7q g==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="253823647" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="253823647" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:54 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="731735723" Received: from dwillia2-desk3.jf.intel.com (HELO dwillia2-desk3.amr.corp.intel.com) ([10.54.39.25]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 15:10:54 -0700 Subject: [ndctl PATCH 10/10] cxl/test: Add topology enumeration and hotplug test From: Dan Williams To: vishal.l.verma@intel.com Cc: Luis Chamberlain , linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev Date: Thu, 28 Apr 2022 15:10:54 -0700 Message-ID: <165118385401.1676208.9224280236045777443.stgit@dwillia2-desk3.amr.corp.intel.com> In-Reply-To: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> References: <165118380037.1676208.7644295506592461996.stgit@dwillia2-desk3.amr.corp.intel.com> User-Agent: StGit/0.18-3-g996c Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Test the re-plug of memdevs, switch ports, root ports, and bus objects. Cc: Luis Chamberlain Signed-off-by: Dan Williams --- test/common | 12 ++++ test/cxl-topology.sh | 166 ++++++++++++++++++++++++++++++++++++++++++++++++++ test/meson.build | 2 + 3 files changed, 180 insertions(+) create mode 100644 test/cxl-topology.sh diff --git a/test/common b/test/common index fb487958a29b..65615cc09a3e 100644 --- a/test/common +++ b/test/common @@ -27,6 +27,18 @@ if [ -z $DAXCTL ]; then fi fi +# CXL +if [ -z $CXL ]; then + if [ -f "../cxl/cxl" ] && [ -x "../cxl/cxl" ]; then + export CXL=../cxl/cxl + elif [ -f "./cxl/cxl" ] && [ -x "./cxl/cxl" ]; then + export CXL=./cxl/cxl + else + echo "Couldn't find a cxl binary" + exit 1 + fi +fi + if [ -z $TEST_PATH ]; then export TEST_PATH=. fi diff --git a/test/cxl-topology.sh b/test/cxl-topology.sh new file mode 100644 index 000000000000..ff11614f4f14 --- /dev/null +++ b/test/cxl-topology.sh @@ -0,0 +1,166 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2022 Intel Corporation. All rights reserved. + +. $(dirname $0)/common + +rc=1 + +set -ex + +trap 'err $LINENO' ERR + +check_prereq "jq" + +modprobe -r cxl_test +modprobe cxl_test +udevadm settle + +# THEORY OF OPERATION: Validate the hard coded assumptions of the +# cxl_test.ko module that defines its topology in +# tools/testing/cxl/test/cxl.c. If that model ever changes then the +# paired update must be made to this test. + +# collect cxl_test root device id +json=$($CXL list -b cxl_test) +count=$(jq "length" <<< $json) +((count == 1)) || err "$LINENO" +root=$(jq -r ".[] | .bus" <<< $json) + + +# validate 2 host bridges under a root port +port_sort="sort_by(.port | .[4:] | tonumber)" +json=$($CXL list -b cxl_test -BP) +count=$(jq ".[] | .[\"ports:$root\"] | length" <<< $json) +((count == 2)) || err "$LINENO" + +bridge[0]=$(jq -r ".[] | .[\"ports:$root\"] | $port_sort | .[0].port" <<< $json) +bridge[1]=$(jq -r ".[] | .[\"ports:$root\"] | $port_sort | .[1].port" <<< $json) + + +# validate 2 root ports per host bridge +json=$($CXL list -b cxl_test -T -p ${bridge[0]}) +count=$(jq ".[] | .dports | length" <<< $json) +((count == 2)) || err "$LINENO" + +json=$($CXL list -b cxl_test -T -p ${bridge[1]}) +count=$(jq ".[] | .dports | length" <<< $json) +((count == 2)) || err "$LINENO" + + +# validate 2 switches per-root port +json=$($CXL list -b cxl_test -P -p ${bridge[0]}) +count=$(jq ".[] | .[\"ports:${bridge[0]}\"] | length" <<< $json) +((count == 2)) || err "$LINENO" + +switch[0]=$(jq -r ".[] | .[\"ports:${bridge[0]}\"] | $port_sort | .[0].host" <<< $json) +switch[1]=$(jq -r ".[] | .[\"ports:${bridge[0]}\"] | $port_sort | .[1].host" <<< $json) + +json=$($CXL list -b cxl_test -P -p ${bridge[1]}) +count=$(jq ".[] | .[\"ports:${bridge[1]}\"] | length" <<< $json) +((count == 2)) || err "$LINENO" + +switch[2]=$(jq -r ".[] | .[\"ports:${bridge[1]}\"] | $port_sort | .[0].host" <<< $json) +switch[3]=$(jq -r ".[] | .[\"ports:${bridge[1]}\"] | $port_sort | .[1].host" <<< $json) + + +# check that all 8 cxl_test memdevs are enabled by default and have a +# pmem size of 256M +json=$($CXL list -b cxl_test -M) +count=$(jq "map(select(.pmem_size == $((256 << 20)))) | length" <<< $json) +((count == 8)) || err "$LINENO" + + +# validate the expected properties of the 4 root decoders +json=$($CXL list -b cxl_test -D -d root) +port_id=${root:4} +port_id_len=${#port_id} +decoder_sort="sort_by(.decoder | .[$((8+port_id_len)):] | tonumber)" +count=$(jq "[ $decoder_sort | .[0] | + select(.volatile_capable == true) | + select(.size == $((256 << 20))) | + select(.nr_targets == 1) ] | length" <<< $json) +((count == 1)) || err "$LINENO" + +count=$(jq "[ $decoder_sort | .[1] | + select(.volatile_capable == true) | + select(.size == $((512 << 20))) | + select(.nr_targets == 2) ] | length" <<< $json) +((count == 1)) || err "$LINENO" + +count=$(jq "[ $decoder_sort | .[2] | + select(.pmem_capable == true) | + select(.size == $((256 << 20))) | + select(.nr_targets == 1) ] | length" <<< $json) +((count == 1)) || err "$LINENO" + +count=$(jq "[ $decoder_sort | .[3] | + select(.pmem_capable == true) | + select(.size == $((512 << 20))) | + select(.nr_targets == 2) ] | length" <<< $json) +((count == 1)) || err "$LINENO" + +# check that switch ports disappear after all of their memdevs have been +# disabled, and return when the memdevs are enabled. +for s in ${switch[@]} +do + json=$($CXL list -M -p $s) + count=$(jq "length" <<< $json) + ((count == 2)) || err "$LINENO" + + mem[0]=$(jq -r ".[0] | .memdev" <<< $json) + mem[1]=$(jq -r ".[1] | .memdev" <<< $json) + + $CXL disable-memdev ${mem[0]} --force + json=$($CXL list -p $s) + count=$(jq "length" <<< $json) + ((count == 1)) || err "$LINENO" + + $CXL disable-memdev ${mem[1]} --force + json=$($CXL list -p $s) + count=$(jq "length" <<< $json) + ((count == 0)) || err "$LINENO" + + $CXL enable-memdev ${mem[0]} + $CXL enable-memdev ${mem[1]} + + json=$($CXL list -p $s) + count=$(jq "length" <<< $json) + ((count == 1)) || err "$LINENO" + + $CXL disable-port $s --force + json=$($CXL list -p $s) + count=$(jq "length" <<< $json) + ((count == 0)) || err "$LINENO" + + $CXL enable-memdev ${mem[0]} ${mem[1]} + json=$($CXL list -p $s) + count=$(jq "length" <<< $json) + ((count == 1)) || err "$LINENO" +done + + +# validate host bridge tear down +for b in ${bridge[@]} +do + $CXL disable-port $b -f + json=$($CXL list -M -i -p $b) + count=$(jq "map(select(.state == \"disabled\")) | length" <<< $json) + ((count == 4)) || err "$LINENO" + + $CXL enable-port $b -m + json=$($CXL list -M -p $b) + count=$(jq "length" <<< $json) + ((count == 4)) || err "$LINENO" +done + + +# validate that the bus can be disabled without issue +$CXL disable-bus $root -f + + +# validate no WARN or lockdep report during the run +log=$(journalctl -r -k --since "-$((SECONDS+1))s") +grep -q "Call Trace" <<< $log && err "$LINENO" + +modprobe -r cxl_test diff --git a/test/meson.build b/test/meson.build index 7ccd45195236..210dcb0b5ff1 100644 --- a/test/meson.build +++ b/test/meson.build @@ -150,6 +150,7 @@ monitor = find_program('monitor.sh') max_extent = find_program('max_available_extent_ns.sh') pfn_meta_errors = find_program('pfn-meta-errors.sh') track_uuid = find_program('track-uuid.sh') +cxl_topo = find_program('cxl-topology.sh') tests = [ [ 'libndctl', libndctl, 'ndctl' ], @@ -174,6 +175,7 @@ tests = [ [ 'max_extent_ns', max_extent, 'ndctl' ], [ 'pfn-meta-errors.sh', pfn_meta_errors, 'ndctl' ], [ 'track-uuid.sh', track_uuid, 'ndctl' ], + [ 'cxl-topology.sh', cxl_topo, 'cxl' ], ] if get_option('destructive').enabled()