From patchwork Fri Apr 29 10:52:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12831813 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75E23C433F5 for ; Fri, 29 Apr 2022 10:52:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237455AbiD2K4C (ORCPT ); Fri, 29 Apr 2022 06:56:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237696AbiD2Kzz (ORCPT ); Fri, 29 Apr 2022 06:55:55 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8D294EDFA; Fri, 29 Apr 2022 03:52:35 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 04BDDFF805; Fri, 29 Apr 2022 10:52:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651229554; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dJ+tLuwq1BPOlvX+T85enpsOsl9owZcJnnnX3M9eI/E=; b=WYeu8IauKgebNrE5LqW60Ux/HLh2WCDLAb64VJegHbKgp3WSYNtafUn/rqJmQTw8rT01J4 D5UOZ3iDAFzhJn34qLr5uhirP5kHez7jtrrE9lc8KI3b1qiNQKvrhdxPFO/RDCjXBlGLRu uefh6mKF7PCzemDKkxdMZFN7MKmMDWkptpAY8kOOVhDEu25a3WL0dPQ+gLd6n190h9Sc2W Ik1YJ7zWO4zsOsauwJK5pzyb4LuXSXXR8F7xKHu6+W/DP7taurlq30HIqJJcZdpXCtUEzj Rv02bSkR/EhVn/oBP2+p4uMdSc+TcxcJy3PlUJ59d3jXvTtC37nCDjnVpKlC/w== From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, Miquel Raynal , Geert Uytterhoeven Subject: [PATCH 1/3] dt-bindings: mtd: renesas: Fix the NAND controller description Date: Fri, 29 Apr 2022 12:52:27 +0200 Message-Id: <20220429105229.368728-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220429105229.368728-1-miquel.raynal@bootlin.com> References: <20220429105229.368728-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the missing power-domain property which is needed on all the RZ/N1 SoC IPs. Suggested-by: Geert Uytterhoeven Signed-off-by: Miquel Raynal Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring --- Documentation/devicetree/bindings/mtd/renesas-nandc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml b/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml index 2870d36361c4..7b18bc5cc8b3 100644 --- a/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml +++ b/Documentation/devicetree/bindings/mtd/renesas-nandc.yaml @@ -36,11 +36,15 @@ properties: - const: hclk - const: eclk + power-domains: + maxItems: 1 + required: - compatible - reg - clocks - clock-names + - power-domains - interrupts unevaluatedProperties: false @@ -56,6 +60,7 @@ examples: interrupts = ; clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; clock-names = "hclk", "eclk"; + power-domains = <&sysctrl>; #address-cells = <1>; #size-cells = <0>; }; From patchwork Fri Apr 29 10:52:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12831815 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F4ACC433FE for ; Fri, 29 Apr 2022 10:52:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238752AbiD2K4F (ORCPT ); Fri, 29 Apr 2022 06:56:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238336AbiD2Kzz (ORCPT ); Fri, 29 Apr 2022 06:55:55 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 819824F440; Fri, 29 Apr 2022 03:52:37 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id A5899FF80B; Fri, 29 Apr 2022 10:52:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651229556; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wzW9cUh6UOXVytZ7otTBtN11xju/vNGhzQGZ27ZQgbI=; b=R9uxkzpFYbyvxiWMln9FuBgLN77uBY6Nck0tPzEFtFKmWVlyqv4vEun836cJ3IG+hT+S7Y Gj1qus7dsakEk1gWuWdltdmNyQndF89BUy8gIxCcwV4pj+uu3WpG1jDJJS/jvNBsjOEXJg N7/1JaGvq3vNtBfDY6ug3+P5k8EerY63xk2LnXCPuHgQED3nR2XAmOkobvG6vjprZxXDdj fDKrotVfhk2asvBfatN0KD9d7TurbnIIkEJXcx34H1lL0IvksYEPMQBK3N9eUMRViWBiLY p5qfFozZyzIrR7iMLkCXBp+iJrtIVq8Yu9uzoarB3ZQ9NSZJFl4aXeiJdqD7bQ== From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, Miquel Raynal Subject: [PATCH 2/3] ARM: dts: r9a06g032: Fix the NAND controller node Date: Fri, 29 Apr 2022 12:52:28 +0200 Message-Id: <20220429105229.368728-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220429105229.368728-1-miquel.raynal@bootlin.com> References: <20220429105229.368728-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add the missing power-domains property which is mandatory. Signed-off-by: Miquel Raynal Reviewed-by: Geert Uytterhoeven --- arch/arm/boot/dts/r9a06g032.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index a35bd19c616a..b3ca904c8647 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -234,6 +234,7 @@ nand_controller: nand-controller@40102000 { interrupts = ; clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; clock-names = "hclk", "eclk"; + power-domains = <&sysctrl>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From patchwork Fri Apr 29 10:52:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12831816 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91D55C43217 for ; Fri, 29 Apr 2022 10:52:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239075AbiD2K4J (ORCPT ); Fri, 29 Apr 2022 06:56:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239106AbiD2Kz5 (ORCPT ); Fri, 29 Apr 2022 06:55:57 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27CDC4F9CB; Fri, 29 Apr 2022 03:52:38 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 363E9FF803; Fri, 29 Apr 2022 10:52:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651229557; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ML7MMPbxJNuIHkREMTzbbN7ra3s9xRQtUGdWLtPRKW0=; b=C7lV+/AnLUxigu+17nAMHMaBP7dAw4Hmbt+hAAomQoa2AxGHau3sAxQc03EWqeVDjQylel 0v1eIjEK5+kipYLfly1JMghPwnkWsQIuoXQkCgqo0W1CeUl1sS/WdNB5I11nSkllAFke4u pt2lxO/iJUj0UU11/dy1N1q4U0VsizK2YfO3yjoIMLpToQUKexthzzG+YlKbg3dkgVUUbm 3kFctz5/MIGOsUrpCHIaNfdsgdcSjhaIowRoQT1OgAzbG6r4CQ1RTnAlw3u4ECpXb+rekz fm2nLDGYzutpAk82LXawLG6/QzF2uFQUqbgLIg02Gs/Ms/70sSWOSGFUrLfDCw== From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , Cc: linux-renesas-soc@vger.kernel.org, Magnus Damm , Gareth Williams , Phil Edworthy , Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, Miquel Raynal Subject: [PATCH 3/3] mtd: rawnand: renesas: Use runtime PM instead of the raw clock API Date: Fri, 29 Apr 2022 12:52:29 +0200 Message-Id: <20220429105229.368728-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220429105229.368728-1-miquel.raynal@bootlin.com> References: <20220429105229.368728-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This NAND controller is part of a well defined power domain handled by the runtime PM core. Let's keep the harmony with the other RZ/N1 drivers and exclusively use the runtime PM API to enable/disable the clocks. We still need to retrieve the external clock rate in order to derive the NAND timings, but that is not a big deal, we can still do that in the probe and just save this value to reuse it later. Signed-off-by: Miquel Raynal --- .../mtd/nand/raw/renesas-nand-controller.c | 58 +++++++++---------- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/nand/raw/renesas-nand-controller.c b/drivers/mtd/nand/raw/renesas-nand-controller.c index 6db063b230a9..72dfbc7fd424 100644 --- a/drivers/mtd/nand/raw/renesas-nand-controller.c +++ b/drivers/mtd/nand/raw/renesas-nand-controller.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #define COMMAND_REG 0x00 @@ -216,8 +217,7 @@ struct rnandc { struct nand_controller controller; struct device *dev; void __iomem *regs; - struct clk *hclk; - struct clk *eclk; + unsigned long ext_clk_rate; unsigned long assigned_cs; struct list_head chips; struct nand_chip *selected_chip; @@ -891,7 +891,7 @@ static int rnandc_setup_interface(struct nand_chip *chip, int chipnr, { struct rnand_chip *rnand = to_rnand(chip); struct rnandc *rnandc = to_rnandc(chip->controller); - unsigned int period_ns = 1000000000 / clk_get_rate(rnandc->eclk); + unsigned int period_ns = 1000000000 / rnandc->ext_clk_rate; const struct nand_sdr_timings *sdr; unsigned int cyc, cle, ale, bef_dly, ca_to_data; @@ -1319,6 +1319,7 @@ static int rnandc_chips_init(struct rnandc *rnandc) static int rnandc_probe(struct platform_device *pdev) { struct rnandc *rnandc; + struct clk *eclk; int irq, ret; rnandc = devm_kzalloc(&pdev->dev, sizeof(*rnandc), GFP_KERNEL); @@ -1335,29 +1336,10 @@ static int rnandc_probe(struct platform_device *pdev) if (IS_ERR(rnandc->regs)) return PTR_ERR(rnandc->regs); - /* APB clock */ - rnandc->hclk = devm_clk_get(&pdev->dev, "hclk"); - if (IS_ERR(rnandc->hclk)) - return PTR_ERR(rnandc->hclk); - - /* External NAND bus clock */ - rnandc->eclk = devm_clk_get(&pdev->dev, "eclk"); - if (IS_ERR(rnandc->eclk)) - return PTR_ERR(rnandc->eclk); - - ret = clk_prepare_enable(rnandc->hclk); - if (ret) - return ret; - - ret = clk_prepare_enable(rnandc->eclk); - if (ret) - goto disable_hclk; - rnandc_dis_interrupts(rnandc); irq = platform_get_irq_optional(pdev, 0); if (irq == -EPROBE_DEFER) { - ret = irq; - goto disable_eclk; + return irq; } else if (irq < 0) { dev_info(&pdev->dev, "No IRQ found, fallback to polling\n"); rnandc->use_polling = true; @@ -1365,12 +1347,25 @@ static int rnandc_probe(struct platform_device *pdev) ret = devm_request_irq(&pdev->dev, irq, rnandc_irq_handler, 0, "renesas-nand-controller", rnandc); if (ret < 0) - goto disable_eclk; + return ret; } ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) - goto disable_eclk; + return ret; + + pm_runtime_enable(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + /* The external NAND bus clock rate is needed for computing timings */ + eclk = clk_get(&pdev->dev, "eclk"); + if (IS_ERR(eclk)) { + ret = PTR_ERR(eclk); + goto dis_runtime_pm; + } + + rnandc->ext_clk_rate = clk_get_rate(eclk); + clk_put(eclk); rnandc_clear_fifo(rnandc); @@ -1378,14 +1373,13 @@ static int rnandc_probe(struct platform_device *pdev) ret = rnandc_chips_init(rnandc); if (ret) - goto disable_eclk; + goto dis_runtime_pm; return 0; -disable_eclk: - clk_disable_unprepare(rnandc->eclk); -disable_hclk: - clk_disable_unprepare(rnandc->hclk); +dis_runtime_pm: + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); return ret; } @@ -1396,8 +1390,8 @@ static int rnandc_remove(struct platform_device *pdev) rnandc_chips_cleanup(rnandc); - clk_disable_unprepare(rnandc->eclk); - clk_disable_unprepare(rnandc->hclk); + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); return 0; }