From patchwork Fri Apr 29 22:08:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 12832949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B42F3C433FE for ; Fri, 29 Apr 2022 22:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354986AbiD2WMN (ORCPT ); Fri, 29 Apr 2022 18:12:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381282AbiD2WML (ORCPT ); Fri, 29 Apr 2022 18:12:11 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBE7DDC594 for ; Fri, 29 Apr 2022 15:08:51 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id k14so7517887pga.0 for ; Fri, 29 Apr 2022 15:08:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3uXNxde6+oEFnU1eADSDWDv36HR4nxvYmBMvpMLrqUE=; b=siAF1f2iy+4k8YPyPcz4Z/uekmGasawINuwsf6+WDe/tVeeaPnb7gTbtjgiiSmeShz 1jcbNjdeuH10fAUnJfiqw9odOwjvCWSA29S+pHNxhMCnYfVNqZGB1rfpHSWNaqcFD402 mtmYOoKSbY5yCPIeHafZkux720lt3KnJY+ya4osF9VmCkWUgCsUKzEHu+MQmmjhZYi3e /dILsxFeU3/pb9lMMOAH3TY3Gxp3UsiK0RGHAi3wsdua+0cbWIk1cJo+uvDXfkg8F+EB rKfACVxAkq5Z4HbXL8ZatLl3nfvZeL03P7q2RtbcDsW17liVF7P74jnRxbxZkS1MXsoQ N8Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3uXNxde6+oEFnU1eADSDWDv36HR4nxvYmBMvpMLrqUE=; b=0mCg0BK13NM6DC2QoDlshDp/JXQ+sE6PPiKbEgwUHlk1VazK/iQEU5x0bJ9tdfMgtD KyOqE5QtG/UmJBFZKd1S2Oh4TamhuznGCNIA64XZZpQll/nIAYWAE4JNyP6iaq8/UoH0 uGXD6qJ1eHoUIcv5dWz4O+ZLm2av/t6lzMSGRI6XjGC2DN/KuBpDbcHupkrUYIg+A7wX f3uNOYVt5IUlPiCIAmKB3M61TCSX68ZFW3cCOWZLxsIX8JlNyZgMxYegaAgRQV1ALTWU yJF/hSXsigMxm/2sMVYF+dmj6gNFTEZuOaduqyJfx47SCjjU5QuPGPFuPhQ9cvJCJAkn ihjw== X-Gm-Message-State: AOAM531znMxSFO7DNh79SVgyl72aoZR9aMMqJSXSQEeCTWbRztmCKzhl p83MoKG78rHWmSRkffwb2GhkiA== X-Google-Smtp-Source: ABdhPJziHDsXi0fRDXzEMVE1/ugW+bUFk0pqhfd+mVF6WgZudWAhbyWUWGcKO9D2zL1MRH2KxpltnA== X-Received: by 2002:a05:6a00:140c:b0:4e1:530c:edc0 with SMTP id l12-20020a056a00140c00b004e1530cedc0mr1310265pfu.18.1651270131396; Fri, 29 Apr 2022 15:08:51 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id n21-20020aa78a55000000b0050dc76281c2sm170020pfa.156.2022.04.29.15.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 15:08:51 -0700 (PDT) From: Bhupesh Sharma To: linux-mmc@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, robh@kernel.org Subject: [PATCH 1/4] dt-bindings: mmc/sdhci-msm: Convert bindings to yaml Date: Sat, 30 Apr 2022 03:38:30 +0530 Message-Id: <20220429220833.873672-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429220833.873672-1-bhupesh.sharma@linaro.org> References: <20220429220833.873672-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert Qualcomm sdhci-msm devicetree binding to YAML. Cc: Ulf Hansson Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/mmc/sdhci-msm.txt | 123 ----------- .../devicetree/bindings/mmc/sdhci-msm.yaml | 192 ++++++++++++++++++ 2 files changed, 192 insertions(+), 123 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.txt create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-msm.yaml diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt deleted file mode 100644 index 6216ed777343..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ /dev/null @@ -1,123 +0,0 @@ -* Qualcomm SDHCI controller (sdhci-msm) - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-msm driver. - -Required properties: -- compatible: Should contain a SoC-specific string and a IP version string: - version strings: - "qcom,sdhci-msm-v4" for sdcc versions less than 5.0 - "qcom,sdhci-msm-v5" for sdcc version 5.0 - For SDCC version 5.0.0, MCI registers are removed from SDCC - interface and some registers are moved to HC. New compatible - string is added to support this change - "qcom,sdhci-msm-v5". - full compatible strings with SoC and version: - "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4" - "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4" - "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" - "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; - "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; - "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" - "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; - "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" - NOTE that some old device tree files may be floating around that only - have the string "qcom,sdhci-msm-v4" without the SoC compatible string - but doing that should be considered a deprecated practice. - -- reg: Base address and length of the register in the following order: - - Host controller register map (required) - - SD Core register map (required for controllers earlier than msm-v5) - - CQE register map (Optional, CQE support is present on SDHC instance meant - for eMMC and version v4.2 and above) - - Inline Crypto Engine register map (optional) -- reg-names: When CQE register map is supplied, below reg-names are required - - "hc" for Host controller register map - - "core" for SD core register map - - "cqhci" for CQE register map - - "ice" for Inline Crypto Engine register map (optional) -- interrupts: Should contain an interrupt-specifiers for the interrupts: - - Host controller interrupt (required) -- pinctrl-names: Should contain only one value - "default". -- pinctrl-0: Should specify pin control groups used for this controller. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names. -- clock-names: Should contain the following: - "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required) - "core" - SDC MMC clock (MCLK) (required) - "bus" - SDCC bus voter clock (optional) - "xo" - TCXO clock (optional) - "cal" - reference clock for RCLK delay calibration (optional) - "sleep" - sleep clock for RCLK delay calibration (optional) - "ice" - clock for Inline Crypto Engine (optional) - -- qcom,ddr-config: Certain chipsets and platforms require particular settings - for the DDR_CONFIG register. Use this field to specify the register - value as per the Hardware Programming Guide. - -- qcom,dll-config: Chipset and Platform specific value. Use this field to - specify the DLL_CONFIG register value as per Hardware Programming Guide. - -Optional Properties: -* Following bus parameters are required for interconnect bandwidth scaling: -- interconnects: Pairs of phandles and interconnect provider specifier - to denote the edge source and destination ports of - the interconnect path. - -- interconnect-names: For sdhc, we have two main paths. - 1. Data path : sdhc to ddr - 2. Config path : cpu to sdhc - For Data interconnect path the name supposed to be - is "sdhc-ddr" and for config interconnect path it is - "cpu-sdhc". - Please refer to Documentation/devicetree/bindings/ - interconnect/ for more details. - -Example: - - sdhc_1: sdhci@f9824900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - interrupts = <0 123 0>; - bus-width = <8>; - non-removable; - - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>, - <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - - qcom,dll-config = <0x000f642c>; - qcom,ddr-config = <0x80040868>; - }; - - sdhc_2: sdhci@f98a4900 { - compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - interrupts = <0 125 0>; - bus-width = <4>; - cd-gpios = <&msmgpio 62 0x1>; - - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>; - - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; - - qcom,dll-config = <0x0007642c>; - qcom,ddr-config = <0x80040868>; - }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml new file mode 100644 index 000000000000..c33f173e3b6c --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm SDHCI controller (sdhci-msm) + +maintainers: + - Bhupesh Sharma + +description: + Secure Digital Host Controller Interface (SDHCI) present on + Qualcomm SOCs supports SD/MMC/SDIO devices. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,apq8084-sdhci + - qcom,msm8226-sdhci + - qcom,msm8953-sdhci + - qcom,msm8974-sdhci + - qcom,msm8916-sdhci + - qcom,msm8992-sdhci + - qcom,msm8994-sdhci + - qcom,msm8996-sdhci + - qcom,qcs404-sdhci + - qcom,sc7180-sdhci + - qcom,sc7280-sdhci + - qcom,sdm630-sdhci + - qcom,sdm845-sdhci + - qcom,sdx55-sdhci + - qcom,sm6125-sdhci + - qcom,sm6350-sdhci + - qcom,sm8250-sdhci + - enum: + - qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 + - qcom,sdhci-msm-v5 # for sdcc version 5.0 + - items: + - const: qcom,sdhci-msm-v4 # Deprecated (only for backward compatibility) + # for sdcc versions less than 5.0 + + reg: + minItems: 1 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + + clocks: + minItems: 3 + items: + - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock + - description: SDC MMC clock, MCLK + - description: TCXO clock + - description: clock for Inline Crypto Engine + - description: SDCC bus voter clock + - description: reference clock for RCLK delay calibration + - description: sleep clock for RCLK delay calibration + + clock-names: + minItems: 2 + items: + - const: iface + - const: core + - const: xo + - const: ice + - const: bus + - const: cal + - const: sleep + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: hc_irq + - const: pwr_irq + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + + pinctrl-0: + description: + Should specify pin control groups used for this controller. + + qcom,ddr-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: platform specific settings for DDR_CONFIG reg. + + qcom,dll-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: platform specific settings for DLL_CONFIG reg. + + iommus: + minItems: 1 + maxItems: 8 + description: | + phandle to apps_smmu node with sid mask. + + interconnects: + items: + - description: data path, sdhc to ddr + - description: config path, cpu to sdhc + + interconnect-names: + items: + - const: sdhc-ddr + - const: cpu-sdhc + + power-domains: + description: A phandle to sdhci power domain node + maxItems: 1 + +patternProperties: + '^opp-table(-[a-z0-9]+)?$': + if: + properties: + compatible: + const: operating-points-v2 + then: + patternProperties: + '^opp-?[0-9]+$': + required: + - required-opps + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: true + +examples: + - | + #include + #include + #include + #include + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd SM8250_CX>; + + operating-points-v2 = <&sdhc2_opp_table>; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; From patchwork Fri Apr 29 22:08:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 12832950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE5EDC433EF for ; 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Fri, 29 Apr 2022 15:08:55 -0700 (PDT) From: Bhupesh Sharma To: linux-mmc@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, robh@kernel.org Subject: [PATCH 2/4] mmc: host/sdhci-msm: Add SoC specific compatibles Date: Sat, 30 Apr 2022 03:38:31 +0530 Message-Id: <20220429220833.873672-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429220833.873672-1-bhupesh.sharma@linaro.org> References: <20220429220833.873672-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Since Qualcomm device-trees already use SoC specific compatibles for describing the 'sdhci-msm' nodes, it makes sense to add the support for the same in the driver as well. Keep the old deprecated compatible strings still in the driver, to ensure backward compatibility with older device-trees. Cc: Ulf Hansson Signed-off-by: Bhupesh Sharma --- drivers/mmc/host/sdhci-msm.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 50c71e0ba5e4..2de8d115a37a 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2434,8 +2434,31 @@ static const struct sdhci_msm_variant_info sdm845_sdhci_var = { }; static const struct of_device_id sdhci_msm_dt_match[] = { + /* Following two entries are deprecated (kept only for backward compatibility) */ {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var}, {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var}, + /* Add entries for sdcc versions less than 5.0 here */ + {.compatible = "qcom,apq8084-sdhci", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,msm8226-sdhci", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,msm8916-sdhci", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,msm8953-sdhci", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,msm8974-sdhci", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,msm8992-sdhci", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,msm8994-sdhci", .data = &sdhci_msm_mci_var}, + {.compatible = "qcom,msm8996-sdhci", .data = &sdhci_msm_mci_var}, + /* + * Add entries for sdcc version 5.0 here. For SDCC version 5.0.0, + * MCI registers are removed from SDCC interface and some registers + * are moved to HC. + */ + {.compatible = "qcom,qcs404-sdhci", .data = &sdhci_msm_v5_var}, + {.compatible = "qcom,sdx55-sdhci", .data = &sdhci_msm_v5_var}, + {.compatible = "qcom,sdm630-sdhci", .data = &sdhci_msm_v5_var}, + {.compatible = "qcom,sm6125-sdhci", .data = &sdhci_msm_v5_var}, + {.compatible = "qcom,sm6350-sdhci", .data = &sdhci_msm_v5_var}, + {.compatible = "qcom,sm8250-sdhci", .data = &sdhci_msm_v5_var}, + {.compatible = "qcom,sc7280-sdhci", .data = &sdhci_msm_v5_var}, + /* Add entries where soc specific handling is required, here */ {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var}, {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var}, {}, From patchwork Fri Apr 29 22:08:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 12832951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51333C433F5 for ; Fri, 29 Apr 2022 22:09:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381304AbiD2WMV (ORCPT ); Fri, 29 Apr 2022 18:12:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381313AbiD2WMU (ORCPT ); Fri, 29 Apr 2022 18:12:20 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C5E6DCA8A for ; Fri, 29 Apr 2022 15:09:00 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id qe3-20020a17090b4f8300b001dc24e4da73so218731pjb.1 for ; Fri, 29 Apr 2022 15:09:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MoViicfii9p6utWoae7ElSIZUS07VgE/0ju82SmR24M=; b=k7HcWctvtlxZkalvnAZe0Z5u5NOvNI94X3lEw6NY1VMBjEzPyVc1CrHbTxTLGTkZrE SrzihBdRRB441L87xO29eXdylrY5XRz9RfsoK7jc97uXxY3sZ++1ES/lN5qsMvbYBnWT AZAjM5U+7f70eK/wKjZhIagWjQkF53uolMKAKWuTe80FQ/1c+z2fuDR2/bWu7hecXeKU 48A96M2TMQcjDl5drYDR5a14TtAN0oP8Pwmri/Ue5JxDhXNIezxWgdhILbMt5c9SIG6q jTnyMCuYWg6yB4XKGsAyxnaeCTepcpz0EDLZrc0TwQOWbk2qWhSaiZIcli85i4P5S1MV 9iEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MoViicfii9p6utWoae7ElSIZUS07VgE/0ju82SmR24M=; b=ESPy5KXwPwJusg7eDSfZakdNN/lXlBKtr2AC05yrThT048W1iJxTHHAeQWnEf9AB6q DWfmrJNMlW33cfZ0V1xp53zR+x9BpeK/A6F0oqwcWzhBsgSZ/3ytkv6Z4KhzMkOiHoyc X9L9qoCHEDaLkBg/zo50XHTheMbSHzVRgO/c8iDOExHCTSgXeUP/SjRZDdRabt6WkTlk 1Ng8tOhY27P1jTsIBTolkvIYT9jIW3yjKLp8anSkEj25OmoC2jscjfi2C9RPv4BcyG7J SCnmQ2WrLuVVY51KDZ5AXWcv4cCLVe/7dD85GKwv0HKGv4sseyAgswtQNNOHiu0BnFqk io+w== X-Gm-Message-State: AOAM531IsfV4Qns9/3lo3ojYKTOY9qttvlKFHadFKrQOrDQ4NaNxqP93 pnw4QeQ1UY5MB8LS8iJ3vDVq6Q== X-Google-Smtp-Source: ABdhPJxZ+EEi2RSJizGrNsZtppHOgq1GzCFOC9SGroJ2295J2M1o09ttfhXrciO0rwIXevRIfOUwBA== X-Received: by 2002:a17:902:e743:b0:15e:8ddd:c7bd with SMTP id p3-20020a170902e74300b0015e8dddc7bdmr126045plf.128.1651270139817; Fri, 29 Apr 2022 15:08:59 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id n21-20020aa78a55000000b0050dc76281c2sm170020pfa.156.2022.04.29.15.08.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 15:08:59 -0700 (PDT) From: Bhupesh Sharma To: linux-mmc@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, robh@kernel.org Subject: [PATCH 3/4] dt-bindings: mmc: sdhci-msm: Add compatible string for sm8150 Date: Sat, 30 Apr 2022 03:38:32 +0530 Message-Id: <20220429220833.873672-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429220833.873672-1-bhupesh.sharma@linaro.org> References: <20220429220833.873672-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add sm8150 SoC specific compatible strings for qcom-sdhci controller. Cc: Ulf Hansson Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index c33f173e3b6c..4eb213b3e551 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -35,6 +35,7 @@ properties: - qcom,sdx55-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci + - qcom,sm8150-sdhci - qcom,sm8250-sdhci - enum: - qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 From patchwork Fri Apr 29 22:08:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 12832952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A531CC433EF for ; Fri, 29 Apr 2022 22:09:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381306AbiD2WM1 (ORCPT ); Fri, 29 Apr 2022 18:12:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381324AbiD2WMZ (ORCPT ); Fri, 29 Apr 2022 18:12:25 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF806DC9A7 for ; Fri, 29 Apr 2022 15:09:04 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id fv2so8192685pjb.4 for ; Fri, 29 Apr 2022 15:09:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N/QIllet2sO5ytIOTpz7N/MbZoymNASzVzoHgwQd9ds=; b=WBnS6Imed8MhrDDQe17uOQPPjeD98ZW536sowUSPN2g8mkV7OJudTNICWQL0VoJgyF 5VGtjG29qgJkdlt34PTo8v2bQnfqXV/ir/a2n51WLugm5Cv3IfZAS8I2pvoueQl9kzu5 ZFvepRX7DJbxL3yWZKHbCJuc11GX5SFJZjdLNxDSY6Ml/+EONCpmOh3AtY/O272JVG0W ylXceMzSa0K6grbwu1kVnV+0vPaqNGmilY0W4YihHPtvxWAxLINBllEh2VekD8MJsL7r jAuJ3AFwdoRt/buFmtR+95tcKwcTz2ViaZ9MDYVr3ah7E9yx12lB8ckZ2Gb6HdJ4jvUM xzeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N/QIllet2sO5ytIOTpz7N/MbZoymNASzVzoHgwQd9ds=; b=k5Cjh/aUTXerrjKmYpRXIyg2aqf7lIQCn6TyH7dmfTme+zI36/s/E20RIV5TTPlp4g wvHXybE1F+i5w2sSELPHs+7cTSIAalvl6ry/OXfqKxStqWqx77iSJ3CzEjm7YvJFZPes rdDrHNu4G0qtLQe+TNbyYYYsqi6BY/V279sGmZB/ZsFq4rFtUBDWLwt8a25c0alfOcbp d2Enf1kSrMC/vQJDijpoUC+7V1mepXk1q6MEBq6S3Ebh8EVp6Ze0LCi9PXI0AiHUsceq Ely+Vht0Fvt1y5vJ3G0XXBvA18Eouf+PYpNR37QvrrzLQYS66o9KmfCZDlFJT7/Vcva/ vtkw== X-Gm-Message-State: AOAM5338RCO3w0piV90vTfeYjbq6C+LaWb/tfYt3VsGgV0S9jSOxvp8y P/Yv6c1zDESp3lXOdC5qYBSRnw== X-Google-Smtp-Source: ABdhPJx4L3grTpOzugZga8zMWulJpZrYlaCRwuLFI5+l3xNV5xWp+cHtfQ2McKzBWNGazJXnmOc0BQ== X-Received: by 2002:a17:903:4093:b0:15c:e5eb:9545 with SMTP id z19-20020a170903409300b0015ce5eb9545mr1416763plc.62.1651270144084; Fri, 29 Apr 2022 15:09:04 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id n21-20020aa78a55000000b0050dc76281c2sm170020pfa.156.2022.04.29.15.09.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 15:09:03 -0700 (PDT) From: Bhupesh Sharma To: linux-mmc@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, robh@kernel.org Subject: [PATCH 4/4] mmc: host/sdhci-msm: Add compatible string check for sm8150 Date: Sat, 30 Apr 2022 03:38:33 +0530 Message-Id: <20220429220833.873672-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429220833.873672-1-bhupesh.sharma@linaro.org> References: <20220429220833.873672-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add sm8150 SoC specific compatible string check inside qcom 'sdhci-msm' controller driver. Cc: Ulf Hansson Signed-off-by: Bhupesh Sharma --- drivers/mmc/host/sdhci-msm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 2de8d115a37a..fd8b4a9079ab 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2456,6 +2456,7 @@ static const struct of_device_id sdhci_msm_dt_match[] = { {.compatible = "qcom,sdm630-sdhci", .data = &sdhci_msm_v5_var}, {.compatible = "qcom,sm6125-sdhci", .data = &sdhci_msm_v5_var}, {.compatible = "qcom,sm6350-sdhci", .data = &sdhci_msm_v5_var}, + {.compatible = "qcom,sm8150-sdhci", .data = &sdhci_msm_v5_var}, {.compatible = "qcom,sm8250-sdhci", .data = &sdhci_msm_v5_var}, {.compatible = "qcom,sc7280-sdhci", .data = &sdhci_msm_v5_var}, /* Add entries where soc specific handling is required, here */