From patchwork Sat Apr 30 15:30:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12833310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 321EEC433F5 for ; Sat, 30 Apr 2022 15:30:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234807AbiD3PeP (ORCPT ); Sat, 30 Apr 2022 11:34:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382919AbiD3PeN (ORCPT ); Sat, 30 Apr 2022 11:34:13 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BFD5193CF; Sat, 30 Apr 2022 08:30:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651332651; x=1682868651; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=+In1ag4kFkCLPlwreoDghbPwvQpqGM1oYsrrAa0Dl3o=; b=vPOSLsky7v51dejLw9ZxeXiNyxDSZJnfDbiDTkBDT5i7Wd2Xqz5tkZaw E8uuX3qgxlF7YnXh6620he5MW3PuO8awOfXeclq0yOaIVQ4RQq+w+ofk1 tfND8bxGoDReaKQupL2OydNQXPziPuJNI8fRaUFi7J5TJqgjOgdl+gVji Y=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Apr 2022 08:30:51 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2022 08:30:51 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:30:50 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:30:47 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH 1/4] ARM: dts: qcom: sdx65: Add QPIC BAM support Date: Sat, 30 Apr 2022 08:30:07 -0700 Message-ID: <1651332610-6334-2-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree node to enable support for QPIC BAM DMA controller on Qualcomm SDX65 platform. Signed-off-by: Kaushal Kumar Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index a64be20..d6a6087 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -199,6 +199,18 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + qpic_bam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From patchwork Sat Apr 30 15:30:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12833311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A273FC4332F for ; Sat, 30 Apr 2022 15:31:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382919AbiD3PeS (ORCPT ); Sat, 30 Apr 2022 11:34:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382929AbiD3PeR (ORCPT ); Sat, 30 Apr 2022 11:34:17 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24C5C193E7; Sat, 30 Apr 2022 08:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651332655; x=1682868655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=LgRKR+kMO8bVjCXhBUYvuZNCnQBGBr53fcBrq4rdF0M=; b=QKZSoTTC2bNUNqy9D20gB1ZSzdeOyRLSji5rlsORCspOSYS4IvZOwpY8 keZ5zo23I89oEFi9SohDz5T2Yq2XJouBpwOwDsQCoy2GlEJTcRIXaBSA9 2IPq3rka4Yb+dUAvPG0eV8vcRFn1NIryzfxOwCP++cN+lLiT3u1aDjmE6 g=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 30 Apr 2022 08:30:55 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2022 08:30:54 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:30:54 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:30:51 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH 2/4] ARM: dts: qcom: sdx65: Add QPIC NAND support Date: Sat, 30 Apr 2022 08:30:08 -0700 Message-ID: <1651332610-6334-3-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX65 platform. Since there is no "aon" clock in SDX65, a dummy clock is provided. Signed-off-by: Kaushal Kumar Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index d6a6087..a75e9f1 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -211,6 +217,22 @@ status = "disabled"; }; + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From patchwork Sat Apr 30 15:30:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12833312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38DBEC433F5 for ; Sat, 30 Apr 2022 15:31:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382947AbiD3Pe2 (ORCPT ); Sat, 30 Apr 2022 11:34:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382946AbiD3Pe0 (ORCPT ); Sat, 30 Apr 2022 11:34:26 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 963151CFFF; Sat, 30 Apr 2022 08:30:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651332658; x=1682868658; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=3c4SxSvv9+jOUyVCaKYzoVU1+8/pgaLmnHAlzRwaBtk=; b=joFdRDM66oP4UueflG5Dnq9DF2BoAcfamnLay92s29i6C9jQHGZex6xg +nh8flgEp7BMDT2sEvrGePL1H+e2kCGu1nGUnCqGiQb5osXg57i2GR6hE kRfDsDF/jR2JX7ZDKXRqmq+JWfCNeB/6L9SlwZOUu1ZC6uKmQqn8cQQsy o=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 30 Apr 2022 08:30:58 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2022 08:30:58 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:30:57 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:30:54 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH 3/4] ARM: dts: qcom: sdx65-mtp: Enable QPIC BAM support Date: Sat, 30 Apr 2022 08:30:09 -0700 Message-ID: <1651332610-6334-4-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable QPIC BAM devicetree node for Qualcomm SDX65-MTP board. Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 6920524..5c5fcb0 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -68,6 +68,10 @@ status = "ok"; }; +&qpic_bam { + status = "ok"; +}; + &apps_rsc { pmx65-rpmh-regulators { compatible = "qcom,pmx65-rpmh-regulators"; From patchwork Sat Apr 30 15:30:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12833313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A525EC433EF for ; Sat, 30 Apr 2022 15:31:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382962AbiD3Peb (ORCPT ); Sat, 30 Apr 2022 11:34:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382964AbiD3Pe2 (ORCPT ); Sat, 30 Apr 2022 11:34:28 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F2A123BC2; Sat, 30 Apr 2022 08:31:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651332665; x=1682868665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Vdib3cq/uwHeVpO2OCfkLwJ2zzwCNhQe5GD7ZRnG7fg=; b=kvoFAhfSRCyD46HXsV+O1fILUR2iavwSvdbwrLage59KB6PZZybNOAQV 8EVzCS3OqskGjTZE2aWKEuomt72KW1HWUqCj9Weqca+x1MwV8E4ctdQNu 8qmrEcZRL7tQU+wF1rrOD1x8DQ9ntFpwcCDG6v3n5jfsAlp7Pm4DwllZk 8=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 30 Apr 2022 08:31:01 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2022 08:31:01 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:31:01 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Apr 2022 08:30:57 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH 4/4] ARM: dts: qcom: sdx65-mtp: Enable QPIC NAND support Date: Sat, 30 Apr 2022 08:30:10 -0700 Message-ID: <1651332610-6334-5-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651332610-6334-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable QPIC NAND devicetree node for Qualcomm SDX65-MTP board. Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 5c5fcb0..3628104 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -72,6 +72,21 @@ status = "ok"; }; +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* ico and efs2 partitions are secured */ + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + &apps_rsc { pmx65-rpmh-regulators { compatible = "qcom,pmx65-rpmh-regulators";