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[94.253.144.225]) by smtp.googlemail.com with ESMTPSA id gv49-20020a1709072bf100b006f3ef214e35sm2769811ejc.155.2022.05.01.11.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 11:22:03 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, amitk@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 1/5] dt-bindings: thermal: tsens: Add ipq8074 compatible Date: Sun, 1 May 2022 20:21:56 +0200 Message-Id: <20220501182200.47328-1-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm IPQ8074 has tsens v2.3.0 block, though unlike existing v2 IP it only uses one IRQ, so tsens v2 compatible cannot be used as the fallback. We also have to make sure that correct interrupts are set according to compatibles, so populate interrupt information per compatibles. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski --- Changes in v2: * No need for a list in compatible check * Specify minItems and maxItems for interrupt and interrupt-names --- .../bindings/thermal/qcom-tsens.yaml | 74 +++++++++++++++++-- 1 file changed, 67 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index b6406bcc683f..e9b85c99bb60 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -56,6 +56,10 @@ properties: - qcom,sm8350-tsens - const: qcom,tsens-v2 + - description: v2 of TSENS with combined interrupt + enum: + - qcom,ipq8074-tsens + reg: items: - description: TM registers @@ -63,15 +67,11 @@ properties: interrupts: minItems: 1 - items: - - description: Combined interrupt if upper or lower threshold crossed - - description: Interrupt if critical threshold crossed + maxItems: 2 interrupt-names: minItems: 1 - items: - - const: uplow - - const: critical + maxItems: 2 nvmem-cells: minItems: 1 @@ -125,21 +125,66 @@ allOf: properties: interrupts: maxItems: 1 + items: + - description: Combined interrupt if upper or lower threshold crossed interrupt-names: maxItems: 1 + items: + - const: uplow - else: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8953-tsens + - qcom,msm8996-tsens + - qcom,msm8998-tsens + - qcom,sc7180-tsens + - qcom,sc7280-tsens + - qcom,sc8180x-tsens + - qcom,sdm630-tsens + - qcom,sdm845-tsens + - qcom,sm8150-tsens + - qcom,sm8250-tsens + - qcom,sm8350-tsens + - qcom,tsens-v2 + then: properties: interrupts: minItems: 2 + items: + - description: Combined interrupt if upper or lower threshold crossed + - description: Interrupt if critical threshold crossed interrupt-names: minItems: 2 + items: + - const: uplow + - const: critical - if: properties: compatible: contains: enum: + - qcom,ipq8074-tsens + then: + properties: + interrupts: + maxItems: 1 + items: + - description: Combined interrupt if upper, lower or critical thresholds crossed + interrupt-names: + maxItems: 1 + items: + - const: combined + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 - qcom,tsens-v2 @@ -222,4 +267,19 @@ examples: #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; + + - | + #include + // Example 4 (for any IPQ8074 based SoC-s): + tsens4: thermal-sensor@4a9000 { + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + + interrupts = ; + interrupt-names = "combined"; + + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; ... 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[94.253.144.225]) by smtp.googlemail.com with ESMTPSA id gv49-20020a1709072bf100b006f3ef214e35sm2769811ejc.155.2022.05.01.11.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 11:22:04 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, amitk@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 2/5] drivers: thermal: tsens: Add support for combined interrupt Date: Sun, 1 May 2022 20:21:57 +0200 Message-Id: <20220501182200.47328-2-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220501182200.47328-1-robimarko@gmail.com> References: <20220501182200.47328-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for signaling both up/low and critical trips. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-8960.c | 1 + drivers/thermal/qcom/tsens-v0_1.c | 1 + drivers/thermal/qcom/tsens-v1.c | 1 + drivers/thermal/qcom/tsens-v2.c | 1 + drivers/thermal/qcom/tsens.c | 37 ++++++++++++++++++++++++++----- drivers/thermal/qcom/tsens.h | 2 ++ 6 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 67c1748cdf73..ee584e5b07e5 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 = { static struct tsens_features tsens_8960_feat = { .ver_major = VER_0, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 0, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index f136cb350238..6effb822bf3c 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_priv *priv) static struct tsens_features tsens_v0_1_feat = { .ver_major = VER_0_1, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 1, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 573e261ccca7..a4f561a6e582 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_priv *priv) static struct tsens_features tsens_v1_feat = { .ver_major = VER_1_X, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 1, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index b293ed32174b..129cdb247381 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -31,6 +31,7 @@ static struct tsens_features tsens_v2_feat = { .ver_major = VER_2_X, .crit_int = 1, + .combo_int = 0, .adc = 0, .srot_split = 1, .max_sensors = 16, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 154d3cb19c88..69b6f7b97e9e 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -532,6 +532,26 @@ static irqreturn_t tsens_irq_thread(int irq, void *data) return IRQ_HANDLED; } +/** + * tsens_combined_irq_thread - Threaded interrupt handler for combined interrupts + * @irq: irq number + * @data: tsens controller private data + * + * Handle the combined interrupt as if it were 2 separate interrupts, so call the + * critical handler first and then the up/low one. + * + * Return: IRQ_HANDLED + */ +static irqreturn_t tsens_combined_irq_thread(int irq, void *data) +{ + irqreturn_t ret; + + ret = tsens_critical_irq_thread(irq, data); + ret = tsens_irq_thread(irq, data); + + return ret; +} + static int tsens_set_trips(void *_sensor, int low, int high) { struct tsens_sensor *s = _sensor; @@ -1080,13 +1100,18 @@ static int tsens_register(struct tsens_priv *priv) tsens_mC_to_hw(priv->sensor, 0)); } - ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); - if (ret < 0) - return ret; + if (priv->feat->combo_int) { + ret = tsens_register_irq(priv, "combined", + tsens_combined_irq_thread); + } else { + ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); + if (ret < 0) + return ret; - if (priv->feat->crit_int) - ret = tsens_register_irq(priv, "critical", - tsens_critical_irq_thread); + if (priv->feat->crit_int) + ret = tsens_register_irq(priv, "critical", + tsens_critical_irq_thread); + } return ret; } diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 1471a2c00f15..4614177944d6 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -495,6 +495,7 @@ enum regfield_ids { * struct tsens_features - Features supported by the IP * @ver_major: Major number of IP version * @crit_int: does the IP support critical interrupts? + * @combo_int: does the IP use one IRQ for up, low and critical thresholds? * @adc: do the sensors only output adc code (instead of temperature)? * @srot_split: does the IP neatly splits the register space into SROT and TM, * with SROT only being available to secure boot firmware? @@ -504,6 +505,7 @@ enum regfield_ids { struct tsens_features { unsigned int ver_major; unsigned int crit_int:1; + unsigned int combo_int:1; unsigned int adc:1; unsigned int srot_split:1; unsigned int has_watchdog:1; From patchwork Sun May 1 18:21:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12833722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDD5DC43219 for ; Sun, 1 May 2022 18:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351121AbiEASZg (ORCPT ); Sun, 1 May 2022 14:25:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240872AbiEASZe (ORCPT ); Sun, 1 May 2022 14:25:34 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39E37527C2; Sun, 1 May 2022 11:22:08 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id n10so6801929ejk.5; Sun, 01 May 2022 11:22:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LFkwqeNMXvWSRmicZbw5B/Ot0aDTRBEW7BnChVj7xEc=; b=JWH/f6+0A2lPPZZNgFHa7QdUBxysG87MuW83tZWLgtuwdCay2qj/h0GAJ27W0blCCu Tv0eCbcnp75oN581WIxPFojLaUI3+GHedGkK3ISRs3c2p293GcWh8pVrsEiKndzzG0f4 0JdJ3uchoXca1tVgpzEl4l7F35qf8lh5iaYR4YEnW2Ct5fPCSNL+zJ8h2cVppF6J75i6 IJH5Ee95iqnyuahmAQL6LW4YuUj4cN2xQ9hYnkHnJOTmVOyCWpIZqQbarIIE1SH1kBKl C6lFBHaZEmcOnCipMvfewUzNPqRt8scfjowkYAg6qBf94yIaAb7/q/ZTv0oJViHM6tMo 2K+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LFkwqeNMXvWSRmicZbw5B/Ot0aDTRBEW7BnChVj7xEc=; b=YoCLxWunrGzyllbtBIzf0M9z78oFcjPifGW4M3PnjLkYgRrmSFJjpnhQjCcUSZBegF wBZYMYGxYL0IvGmJmbRnjBU372USPvc+J+7/GwGqEY+MHmyPCBZyNxzWRdpXZJkO+w34 xTdGQPapvIZEDmNwvC8bS8x4Y5Ih54+m5+nLzAjRF41HBiacFHh8tiMa7cpL1N2H3Ln+ UhGV1ulrTsxHe7eSAsC7TNK89C+AR8Cnq6FEysPCcK7pAPANUoxUfMYq7w+oJRdROORE GLf/xbiHT76B5c7+Gb5lvmvBpLBDu/WS5Dneu+IpuTmNSaligPlqEOGA10RicZLEjcT/ 3z8Q== X-Gm-Message-State: AOAM5325ASlbkTlrfQSu1XEmPEAIClQre1uF6QHTgne4QCg8YYIB+wOs SfHhb9T2rtqOtMmLDRvKZVg= X-Google-Smtp-Source: ABdhPJwxoeRc227SMw7EXvBwMkxjpYPuKGcpx8jQ/85o7TXvqpczBQ0Zi+Cg4LTYSOBVddPsb7wJug== X-Received: by 2002:a17:907:9710:b0:6f3:6e7e:d5bd with SMTP id jg16-20020a170907971000b006f36e7ed5bdmr8297678ejc.252.1651429326816; Sun, 01 May 2022 11:22:06 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-225-cbl.xnet.hr. [94.253.144.225]) by smtp.googlemail.com with ESMTPSA id gv49-20020a1709072bf100b006f3ef214e35sm2769811ejc.155.2022.05.01.11.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 11:22:06 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, amitk@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 3/5] drivers: thermal: tsens: allow configuring min and max trips Date: Sun, 1 May 2022 20:21:58 +0200 Message-Id: <20220501182200.47328-3-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220501182200.47328-1-robimarko@gmail.com> References: <20220501182200.47328-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 and IPQ6018 dont support negative trip temperatures and support up to 204 degrees C as the max trip temperature. So, instead of always setting the -40 as min and 120 degrees C as max allow it to be configured as part of the features. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-8960.c | 2 ++ drivers/thermal/qcom/tsens-v0_1.c | 2 ++ drivers/thermal/qcom/tsens-v1.c | 2 ++ drivers/thermal/qcom/tsens-v2.c | 2 ++ drivers/thermal/qcom/tsens.c | 4 ++-- drivers/thermal/qcom/tsens.h | 4 ++++ 6 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index ee584e5b07e5..4585904fb380 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_feat = { .adc = 1, .srot_split = 0, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; struct tsens_plat_data data_8960 = { diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 6effb822bf3c..2c203ff374e6 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -543,6 +543,8 @@ static struct tsens_features tsens_v0_1_feat = { .adc = 1, .srot_split = 1, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index a4f561a6e582..1d7f8a80bd13 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -306,6 +306,8 @@ static struct tsens_features tsens_v1_feat = { .adc = 1, .srot_split = 1, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 129cdb247381..9babc69bfd22 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_feat = { .adc = 0, .srot_split = 1, .max_sensors = 16, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 69b6f7b97e9e..b7701d5efdfc 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -572,8 +572,8 @@ static int tsens_set_trips(void *_sensor, int low, int high) dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); - cl_high = clamp_val(high, -40000, 120000); - cl_low = clamp_val(low, -40000, 120000); + cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp); + cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp); high_val = tsens_mC_to_hw(s, cl_high); low_val = tsens_mC_to_hw(s, cl_low); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 4614177944d6..747004476347 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -501,6 +501,8 @@ enum regfield_ids { * with SROT only being available to secure boot firmware? * @has_watchdog: does this IP support watchdog functionality? * @max_sensors: maximum sensors supported by this version of the IP + * @trip_min_temp: minimum trip temperature supported by this version of the IP + * @trip_max_temp: maximum trip temperature supported by this version of the IP */ struct tsens_features { unsigned int ver_major; @@ -510,6 +512,8 @@ struct tsens_features { unsigned int srot_split:1; unsigned int has_watchdog:1; unsigned int max_sensors; + int trip_min_temp; + int trip_max_temp; }; /** From patchwork Sun May 1 18:21:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12833724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6132CC4167E for ; Sun, 1 May 2022 18:22:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353080AbiEASZh (ORCPT ); Sun, 1 May 2022 14:25:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350485AbiEASZf (ORCPT ); Sun, 1 May 2022 14:25:35 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D08CA527E8; Sun, 1 May 2022 11:22:09 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id t5so3814065edw.11; Sun, 01 May 2022 11:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WTxPRlSp8k/tQZEOjjNIb49rT6gGrw+y6fIhsPtqfJw=; b=XTqEH+89rkDKQE+dauoDGDgNoNPIcHyX2OaAveqY9/vHuQf38j7QAEAhYTha9ba+SQ 4QklRV71JqeA8H947kJ969TzFGVC8rIz7g4bFsU4R+AIJg3MJOqv4Inh7GuPeTMx5Lzl WduWjCaqMnjLyPEoyf8+j/acvpmj7n9N+QD3R6JFUlGZbJNzVTWHpebOBY55CjPQyVgd +8S7V0qQabeZ6eQJPWcktGoz2sdXcRy9oMGC75xyCf4+sqDiAsY8c/9KR48rI79zuX1i 9ikRkyKftfzrLHmRBk62CNBqRCJNygCluxurdP+QrvuIMWxHzOfjVNHggB/Qe3mH89UV 8Ghw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WTxPRlSp8k/tQZEOjjNIb49rT6gGrw+y6fIhsPtqfJw=; b=XCG/6I22BIf/mkYH7w4AG6PtAWNW6LpUcYBA82NTGbpDvt7HWT8NmnR61+2OgvRToS fsF1aoRSSjDPRQaeiM+nRm6KPD3zD40jFSuQXRQZb6OKrwN+oGj++bQ2FzNcnPWDkjPw 9cE8d7dv3r5ulrO2Le0s56m+lGGIJ5wlOuB4AbsR0U5mfrO/D5KsRmP68CY6UZ3XJMAZ xDpODJ03o2gfBHpXZ1hJwWMPqLP3PDI9HXTtTq425I1X75Y0SzDyOcZZsI0p/4qD2Hb3 czNveiZGCJ9TjDEddjeXkTQmuJO2KKOziohDRoxHkp7kTWw58/yEe18aB7pMVhUbEOmA KJkg== X-Gm-Message-State: AOAM533tqxAt67ZxuEGCqfugamSlPj4ff3iOeCv7gOei3iIwaNZbJaNS 9mMcJ4Z5JeU/+M/X1mdFROI= X-Google-Smtp-Source: ABdhPJxc3oCu0NJkdSfdXGgA9+1i435hcic9oxk/ktV3VLAwh6ALNP/eKL5Tez9o9INkCy3eAY7yjQ== X-Received: by 2002:a05:6402:28b1:b0:425:c39e:b773 with SMTP id eg49-20020a05640228b100b00425c39eb773mr9630956edb.237.1651429328424; Sun, 01 May 2022 11:22:08 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-225-cbl.xnet.hr. [94.253.144.225]) by smtp.googlemail.com with ESMTPSA id gv49-20020a1709072bf100b006f3ef214e35sm2769811ejc.155.2022.05.01.11.22.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 11:22:08 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, amitk@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 4/5] drivers: thermal: tsens: add IPQ8074 support Date: Sun, 1 May 2022 20:21:59 +0200 Message-Id: <20220501182200.47328-4-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220501182200.47328-1-robimarko@gmail.com> References: <20220501182200.47328-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP it only has one IRQ, that is used for up/low as well as critical. It also does not support negative trip temperatures. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 9babc69bfd22..29a61d2d6ca3 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_feat = { .trip_max_temp = 120000, }; +static struct tsens_features ipq8074_feat = { + .ver_major = VER_2_X, + .crit_int = 1, + .combo_int = 1, + .adc = 0, + .srot_split = 1, + .max_sensors = 16, + .trip_min_temp = 0, + .trip_max_temp = 204000, +}; + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* ----- SROT ------ */ /* VERSION */ @@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = { .fields = tsens_v2_regfields, }; +struct tsens_plat_data data_ipq8074 = { + .ops = &ops_generic_v2, + .feat = &ipq8074_feat, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b7701d5efdfc..3624daaaf34b 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -990,6 +990,9 @@ static const struct of_device_id tsens_table[] = { { .compatible = "qcom,ipq8064-tsens", .data = &data_8960, + }, { + .compatible = "qcom,ipq8074-tsens", + .data = &data_ipq8074, }, { .compatible = "qcom,mdm9607-tsens", .data = &data_9607, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 747004476347..8dd990d944ad 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -599,6 +599,6 @@ extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; extern struct tsens_plat_data data_tsens_v1, data_8976; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */ From patchwork Sun May 1 18:22:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12833723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A6E3C35280 for ; Sun, 1 May 2022 18:22:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353700AbiEASZj (ORCPT ); Sun, 1 May 2022 14:25:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353656AbiEASZh (ORCPT ); Sun, 1 May 2022 14:25:37 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A2FA352B28; Sun, 1 May 2022 11:22:11 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id t5so3814111edw.11; Sun, 01 May 2022 11:22:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7ksfYzQBn7UrcwfXPR8oQDY9eW9oGago9RfblkVMga0=; b=ffLGJVCrtYMGOVbFuhVkbAI/YM3ho9JZOvR75oifjMhBEGBHXM4MrFPqSVi88fwlSg +tXWsTeuGgg9zPzksIkGDrp1MZmYd/DrWTeGFXh76ynyOQefGV/sdtB+eXJiuDAZhL4P LLdgqQaT4C+yFeBSFrR2Wo6nv/r3hvDtLaAOvYFwOYoBI6lzHN3G6YNDQd6MTxQ89dir yxyYyRVmKi9RFHCj1jKuXBepopt+FNulu7SEr8EZzVDq8dVPJPdNXIFcvFH/A6s/RX3A +INInXP9mm77uyFYkUFFvsTFieabB4YjSWNbGQ3thpesLnMEZn8D5qo1pEtwLW5D+F8t inSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7ksfYzQBn7UrcwfXPR8oQDY9eW9oGago9RfblkVMga0=; b=MK6zQ8eG9vttaW3vOjW7r5QEEqzvIBWgjlpBcTwOypG5nmOe5uMhtYLBGgavnaQ0Zc y+PBTYutBcDYyw70aoPd3u3ig/hVdgvhWM0F+kb/eHbWzBNdBvsjxMOHlNgXFLH1QeHa Y8MIeuV6MTKKJ6IE0LsAdgFsz07+ykaA+n+7FGBtu2gcM8qvxecK4n0mESlQ7htMy7Ci a6vs15Er64xGp4W0fOM/u7Q30ZmLGsQkID7t86SZXk0AuUEH3WL9ZSRbujerYlOa1xl2 GyS9nF8hYCCS50rpyPVSBD9vhMqAKFxbA77cWshw6xhzj9mmBUuHGTKhIgrgJD1cbaqU bXyw== X-Gm-Message-State: AOAM533HQFBiP/xWWkVWgC+pZMUjwGhPbXL2X/yutNRjGdgiXKwqm1MB VDIMMFznnLL1sGptcU3FOq8= X-Google-Smtp-Source: ABdhPJy+S4ZokkQAr8L+V+PJU0ouuLgC99QeSZtg1idRU+0+6pqvq46wPkj0ntcA0m/otZQkRXaAZg== X-Received: by 2002:a05:6402:3292:b0:427:b4c9:6522 with SMTP id f18-20020a056402329200b00427b4c96522mr5239035eda.406.1651429330230; Sun, 01 May 2022 11:22:10 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-225-cbl.xnet.hr. [94.253.144.225]) by smtp.googlemail.com with ESMTPSA id gv49-20020a1709072bf100b006f3ef214e35sm2769811ejc.155.2022.05.01.11.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 May 2022 11:22:09 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, amitk@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v2 5/5] arm64: dts: ipq8074: add thermal nodes Date: Sun, 1 May 2022 20:22:00 +0200 Message-Id: <20220501182200.47328-5-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220501182200.47328-1-robimarko@gmail.com> References: <20220501182200.47328-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the die. So lets add the tsens and thermal zone nodes, passive CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index afbae86cf6d3..76e02490b968 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -332,6 +332,16 @@ prng: rng@e3000 { status = "disabled"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00704000 0x20000>; @@ -1092,4 +1102,90 @@ wifi: wifi@c0000000 { status = "disabled"; }; }; + + thermal-zones { + nss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + }; + + nss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + }; + + nss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + }; + + wcss-phya0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + }; + + wcss-phya1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + }; + + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 11>; + }; + + cpu3_thermal: cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 12>; + }; + + cluster_thermal: cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 13>; + }; + + wcss-phyb0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 14>; + }; + + wcss-phyb1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 15>; + }; + }; };