From patchwork Mon May 2 14:14:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12834250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AA47C433EF for ; Mon, 2 May 2022 14:15:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385543AbiEBOTJ (ORCPT ); Mon, 2 May 2022 10:19:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385644AbiEBOTA (ORCPT ); Mon, 2 May 2022 10:19:00 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1458AB88; Mon, 2 May 2022 07:15:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651500932; x=1683036932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=AR3nROx9kSazZj+h7yJIP1c+hNRzoH3odyY+rnljXck=; b=bVvryGDfw3VqJ626c12lpqA3+M08FMLCC+nQTS6o12wHrLV7W4a4QkdI 4mreLl4jmhCi+DPpJWeEFsZYNfkjBLNtIK1Vp+fNdHZGN09Pgq2OMPPYC ASH1mqGhCrA0VQay4byJtbDMubu6E9zVtLNC9lnGcbou00g9jCo6A1pbt Y=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 02 May 2022 07:15:31 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 07:15:01 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:15:00 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:14:57 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v2 1/4] ARM: dts: qcom: sdx65: Add QPIC BAM support Date: Mon, 2 May 2022 07:14:35 -0700 Message-ID: <1651500878-10244-2-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree node to enable support for QPIC BAM DMA controller on Qualcomm SDX65 platform. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index a64be20..d6a6087 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -199,6 +199,18 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + qpic_bam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From patchwork Mon May 2 14:14:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12834247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E84FCC433EF for ; Mon, 2 May 2022 14:15:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385520AbiEBOSf (ORCPT ); Mon, 2 May 2022 10:18:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385523AbiEBOSd (ORCPT ); Mon, 2 May 2022 10:18:33 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9E8915830; Mon, 2 May 2022 07:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651500904; x=1683036904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=48+rVERvNTQxNqzw5fqv4Nm35unnocBFemLJibc0Q54=; b=YWgn7RQ6jD7QXGM2gYgQbmq3fRy0lv+IPXNbXBVF/OioVLNtFyjr+4zs cxBgY1x7MemnpDRsO9KjxGbeA4uYVOkNltNDNL7iMPfo/dSaO2ZRbXbXe zceIAQ5UvikRdNKVE9217mN8cCCmCsG5oR8OvimjxbdrI35pQkYlnzIVk w=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 02 May 2022 07:15:04 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 07:15:04 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:15:04 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:15:00 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v2 2/4] ARM: dts: qcom: sdx65: Add QPIC NAND support Date: Mon, 2 May 2022 07:14:36 -0700 Message-ID: <1651500878-10244-3-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX65 platform. Since there is no "aon" clock in SDX65, a dummy clock is provided. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index d6a6087..a75e9f1 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -211,6 +217,22 @@ status = "disabled"; }; + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From patchwork Mon May 2 14:14:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12834248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 515AEC433EF for ; Mon, 2 May 2022 14:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385532AbiEBOSi (ORCPT ); Mon, 2 May 2022 10:18:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385523AbiEBOSh (ORCPT ); Mon, 2 May 2022 10:18:37 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C29F315A16; Mon, 2 May 2022 07:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651500908; x=1683036908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=KeJg4jAJLGS3VV0AbRPdz3qfUX0gmuHZZzF/V15yHtA=; b=WmEK9is6GdJZnYEV24oWIHz9BDPI7ANSh4AVxOSYadgQmlickkWBA0x+ mf4NSf8jlsJ4GwRLSD+gOPHq+q3fhSaVlqoLseS01gIezc84viZrIZJJW l58nkELhwuNYH0zP/UgOEPsgwamiNth2wb1iAQYh+NYuV4J3oX3v462Qa 4=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 02 May 2022 07:15:08 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 07:15:07 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:15:07 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:15:04 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v2 3/4] ARM: dts: qcom: sdx65-mtp: Enable QPIC BAM support Date: Mon, 2 May 2022 07:14:37 -0700 Message-ID: <1651500878-10244-4-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable QPIC BAM devicetree node for Qualcomm SDX65-MTP board. While at it, sort the blsp1_uart3 node in alphabetical order. Signed-off-by: Kaushal Kumar Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 6920524..153ad2a 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -64,10 +64,6 @@ }; }; -&blsp1_uart3 { - status = "ok"; -}; - &apps_rsc { pmx65-rpmh-regulators { compatible = "qcom,pmx65-rpmh-regulators"; @@ -245,6 +241,14 @@ }; }; +&blsp1_uart3 { + status = "ok"; +}; + +&qpic_bam { + status = "ok"; +}; + &usb { status = "okay"; }; From patchwork Mon May 2 14:14:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaushal Kumar X-Patchwork-Id: 12834249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D739AC43217 for ; Mon, 2 May 2022 14:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385551AbiEBOTK (ORCPT ); Mon, 2 May 2022 10:19:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385646AbiEBOTB (ORCPT ); Mon, 2 May 2022 10:19:01 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C88CC13EB1; Mon, 2 May 2022 07:15:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651500932; x=1683036932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=yTX41JeraCfRTBjir39mA80cBsGj5BQ5Wv3IptkAcz0=; b=iBgwut29F8PS3+mmIrxPRUEMapnzLDUT1FXsEeSyjAYoFKsRUepTc0d9 F3JRFq6vFzMZzlYw2wCh8B3iwHz/85IoGVqGM4LMCvB2cOmaSxA8qyLlc q80b8335NO9WyXK2fKOZXxKpmysx1ibyas3Sw2ssa5ps962kSyiu8ra8h c=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 02 May 2022 07:15:31 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 07:15:11 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:15:10 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 07:15:07 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v2 4/4] ARM: dts: qcom: sdx65-mtp: Enable QPIC NAND support Date: Mon, 2 May 2022 07:14:38 -0700 Message-ID: <1651500878-10244-5-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651500878-10244-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable QPIC NAND devicetree node for Qualcomm SDX65-MTP board. Signed-off-by: Kaushal Kumar Reviewed-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 153ad2a..b0027c1 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -249,6 +249,21 @@ status = "ok"; }; +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* ico and efs2 partitions are secured */ + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + &usb { status = "okay"; };