From patchwork Tue May 3 20:08:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9B2AC433F5 for ; Tue, 3 May 2022 20:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235006AbiECUMZ (ORCPT ); Tue, 3 May 2022 16:12:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234689AbiECUMU (ORCPT ); Tue, 3 May 2022 16:12:20 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C60BB40924; Tue, 3 May 2022 13:08:17 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id kq17so35482039ejb.4; Tue, 03 May 2022 13:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7TqgrTONdYchEwgr6zN1k5TY6YG09ErgwU27PFjZsGs=; b=Jn8aoiI2ikVrlZIYq9rqh8SoHYiW/1m6s1JrW0hTdhmr19BSJjk+lPEN8x23p7EK+w XYGCNkJfmeXCuOf4H+O4RT2INXSqtQObntwZjKoU5hJfOTU8lEaVgiY0YqqaLBbqXMZx vbMBYku1R5bdWWKlr4/2wg0LI8cK1atNl3MGb4myEYlmtQ6L+aC/eOdXRoPd+usvGOEo h4HaLotLMsFU6uF8u2y6mPxi4/eMyKsUa5+uAt6t8vhr2+QUD11Ge1ElBh+KA+8QMRsG +2Cpl8Ucyj6RZYutcBUA6A4GB8hE8MfsDKuH26DLHNSr8mflUKEkLCKJiBbLUhVFNHLO qZxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7TqgrTONdYchEwgr6zN1k5TY6YG09ErgwU27PFjZsGs=; b=vNRNC3MaiX7eWwUzE5550y93uSldDmt2SDydIK38F6HGYIw5UvwnCILjUz8/7YFQmC XwXN/eS2c74iYuXP4sXd34LD31q5i7okAl6pw7I9wlHwdDQU1KXclZsKplYH3WTTNq8+ VU9Y5fq5uO+sOb09hep79UyFExnzuqugx1580vCM54e+3lxpmbY2CcqnhtC9/W5X24rO vzeP+YW8RNxevwCx5M0gtBIPGLBTHyqjcujOAB9/LM05MxRQj3D95RNevplgornprNY9 jCrhMgLc+pWR42EcHfYPWMV8dZJQxdsJxd4b1Lts2XVyUVS7XrY34Q1RGyYyEoF4f8cT SrEg== X-Gm-Message-State: AOAM532IraHsPRTJl4ZGPWiXsfqokZbSdRyU7NIEL+xBleiKMZiBexkU SOZxVu+/gRY9REBJ2+SwROY= X-Google-Smtp-Source: ABdhPJyhMc1NyL4B9pTCp0N118EakOxTWFSloDpilfKE1xgUQVkuCjz0Eud6mUmK07n/EFMd185Qlw== X-Received: by 2002:a17:906:974e:b0:6bb:4f90:a6ae with SMTP id o14-20020a170906974e00b006bb4f90a6aemr17628682ejy.452.1651608496367; Tue, 03 May 2022 13:08:16 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ml11-20020a170906cc0b00b006f3ef214e59sm4967466ejb.191.2022.05.03.13.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:08:15 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v4 1/5] dt-bindings: thermal: tsens: Add ipq8074 compatible Date: Tue, 3 May 2022 22:08:09 +0200 Message-Id: <20220503200813.4020698-1-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm IPQ8074 has tsens v2.3.0 block, though unlike existing v2 IP it only uses one IRQ, so tsens v2 compatible cannot be used as the fallback. We also have to make sure that correct interrupts are set according to compatibles, so populate interrupt information per compatibles. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- Changes in v4: * Add the forgotten Reviewed-by tag from Krzysztof Changes in v3: * Remove implied min/maxItem properties as pointed by Rob Changes in v2: * No need for a list in compatible check * Specify minItems and maxItems for interrupt and interrupt-names --- .../bindings/thermal/qcom-tsens.yaml | 76 ++++++++++++++++--- 1 file changed, 65 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index b6406bcc683f..23f69eead67e 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -56,6 +56,10 @@ properties: - qcom,sm8350-tsens - const: qcom,tsens-v2 + - description: v2 of TSENS with combined interrupt + enum: + - qcom,ipq8074-tsens + reg: items: - description: TM registers @@ -63,15 +67,11 @@ properties: interrupts: minItems: 1 - items: - - description: Combined interrupt if upper or lower threshold crossed - - description: Interrupt if critical threshold crossed + maxItems: 2 interrupt-names: minItems: 1 - items: - - const: uplow - - const: critical + maxItems: 2 nvmem-cells: minItems: 1 @@ -124,22 +124,61 @@ allOf: then: properties: interrupts: - maxItems: 1 + items: + - description: Combined interrupt if upper or lower threshold crossed interrupt-names: - maxItems: 1 + items: + - const: uplow - else: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8953-tsens + - qcom,msm8996-tsens + - qcom,msm8998-tsens + - qcom,sc7180-tsens + - qcom,sc7280-tsens + - qcom,sc8180x-tsens + - qcom,sdm630-tsens + - qcom,sdm845-tsens + - qcom,sm8150-tsens + - qcom,sm8250-tsens + - qcom,sm8350-tsens + - qcom,tsens-v2 + then: + properties: + interrupts: + items: + - description: Combined interrupt if upper or lower threshold crossed + - description: Interrupt if critical threshold crossed + interrupt-names: + items: + - const: uplow + - const: critical + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-tsens + then: properties: interrupts: - minItems: 2 + items: + - description: Combined interrupt if upper, lower or critical thresholds crossed interrupt-names: - minItems: 2 + items: + - const: combined - if: properties: compatible: contains: enum: + - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 - qcom,tsens-v2 @@ -222,4 +261,19 @@ examples: #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; + + - | + #include + // Example 4 (for any IPQ8074 based SoC-s): + tsens4: thermal-sensor@4a9000 { + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + + interrupts = ; + interrupt-names = "combined"; + + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; ... 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[88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ml11-20020a170906cc0b00b006f3ef214e59sm4967466ejb.191.2022.05.03.13.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:08:17 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v4 2/5] drivers: thermal: tsens: Add support for combined interrupt Date: Tue, 3 May 2022 22:08:10 +0200 Message-Id: <20220503200813.4020698-2-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200813.4020698-1-robimarko@gmail.com> References: <20220503200813.4020698-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for signaling both up/low and critical trips. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-8960.c | 1 + drivers/thermal/qcom/tsens-v0_1.c | 1 + drivers/thermal/qcom/tsens-v1.c | 1 + drivers/thermal/qcom/tsens-v2.c | 1 + drivers/thermal/qcom/tsens.c | 37 ++++++++++++++++++++++++++----- drivers/thermal/qcom/tsens.h | 2 ++ 6 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 67c1748cdf73..ee584e5b07e5 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 = { static struct tsens_features tsens_8960_feat = { .ver_major = VER_0, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 0, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index f136cb350238..6effb822bf3c 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_priv *priv) static struct tsens_features tsens_v0_1_feat = { .ver_major = VER_0_1, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 1, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 573e261ccca7..a4f561a6e582 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_priv *priv) static struct tsens_features tsens_v1_feat = { .ver_major = VER_1_X, .crit_int = 0, + .combo_int = 0, .adc = 1, .srot_split = 1, .max_sensors = 11, diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index b293ed32174b..129cdb247381 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -31,6 +31,7 @@ static struct tsens_features tsens_v2_feat = { .ver_major = VER_2_X, .crit_int = 1, + .combo_int = 0, .adc = 0, .srot_split = 1, .max_sensors = 16, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 154d3cb19c88..69b6f7b97e9e 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -532,6 +532,26 @@ static irqreturn_t tsens_irq_thread(int irq, void *data) return IRQ_HANDLED; } +/** + * tsens_combined_irq_thread - Threaded interrupt handler for combined interrupts + * @irq: irq number + * @data: tsens controller private data + * + * Handle the combined interrupt as if it were 2 separate interrupts, so call the + * critical handler first and then the up/low one. + * + * Return: IRQ_HANDLED + */ +static irqreturn_t tsens_combined_irq_thread(int irq, void *data) +{ + irqreturn_t ret; + + ret = tsens_critical_irq_thread(irq, data); + ret = tsens_irq_thread(irq, data); + + return ret; +} + static int tsens_set_trips(void *_sensor, int low, int high) { struct tsens_sensor *s = _sensor; @@ -1080,13 +1100,18 @@ static int tsens_register(struct tsens_priv *priv) tsens_mC_to_hw(priv->sensor, 0)); } - ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); - if (ret < 0) - return ret; + if (priv->feat->combo_int) { + ret = tsens_register_irq(priv, "combined", + tsens_combined_irq_thread); + } else { + ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); + if (ret < 0) + return ret; - if (priv->feat->crit_int) - ret = tsens_register_irq(priv, "critical", - tsens_critical_irq_thread); + if (priv->feat->crit_int) + ret = tsens_register_irq(priv, "critical", + tsens_critical_irq_thread); + } return ret; } diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 1471a2c00f15..4614177944d6 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -495,6 +495,7 @@ enum regfield_ids { * struct tsens_features - Features supported by the IP * @ver_major: Major number of IP version * @crit_int: does the IP support critical interrupts? + * @combo_int: does the IP use one IRQ for up, low and critical thresholds? * @adc: do the sensors only output adc code (instead of temperature)? * @srot_split: does the IP neatly splits the register space into SROT and TM, * with SROT only being available to secure boot firmware? @@ -504,6 +505,7 @@ enum regfield_ids { struct tsens_features { unsigned int ver_major; unsigned int crit_int:1; + unsigned int combo_int:1; unsigned int adc:1; unsigned int srot_split:1; unsigned int has_watchdog:1; From patchwork Tue May 3 20:08:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E32BC4321E for ; Tue, 3 May 2022 20:09:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242185AbiECUMd (ORCPT ); Tue, 3 May 2022 16:12:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238208AbiECUMU (ORCPT ); Tue, 3 May 2022 16:12:20 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 652634092D; Tue, 3 May 2022 13:08:21 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id gh6so35562419ejb.0; Tue, 03 May 2022 13:08:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LFkwqeNMXvWSRmicZbw5B/Ot0aDTRBEW7BnChVj7xEc=; b=fDmPwdLW1T+6OUcDyB7vVjMS6/hjXVkhZIyaIq6tv5Cq8rCeMJnyg7W4gKaYWIkA/o 640jziVpXAQ3myiaXG9VsiyOM1XB3XznXF+CL1qYTJepz10AqxavkqIMQh7w+2+9rWE3 iJT2lMa2bCcimtw+WMKe+o5tb/mIugs40kPJPlxTUVvzdck7FntCCm5VyDX1CC7DTKqh Ay0Z8Rcg8M3UwV3Yw6w8GiQtT0eOUVGfQseQDfRkc07/M+eUnGNLd6CbjaiLfEODBTaO xizD5yY9iwFRF+fc5FjxWbkySEaFOgmr8wnaJg/2mg8V4nd61Q6lIaUWwe6SDwbO/3cN RimQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LFkwqeNMXvWSRmicZbw5B/Ot0aDTRBEW7BnChVj7xEc=; b=m204n5HjE8gCTTE4mnTV2QtddfVyjtHowHQB+E0byVAQzRwikb2gDbjm5Ud1lFDnX3 qQ5WFeg3Rud2TuwpVwmzjLwDzZUtMu3xuI2dBrEvWdaLsY4ujJDPwrB3Vm7Qa5P/aznG hikw2oS7bMd1WtnZOP9XEVzVBEMFUWbY8QSJkW0LPqou5114XTfx3ZleSt4KMUNIvmrI QKjKm00msdIzoUn1WPgXHdPiGjzVNO7fJKaNhSNI51F4T0zZclTJWfifkNtrx3Df9elm 11njYo28dr4DUdy0XdtkOkf3qW9TTXFVx5nry/oIeEko0bdQTbcVi7t5tLiVtpe4d5z5 jcNw== X-Gm-Message-State: AOAM530Ex6NIy+HX+j0ur4BY9oARWS4wr2yYDSUUhGQmoUYmFZHIc2LR qLHLZQKS+J/Sm1l/UsqKaSac5n3//oeOxA== X-Google-Smtp-Source: ABdhPJz4EXklKvCfbO8c19iCYHJhew6+DjIfiJdh2Ufi84jYtpY4Z3xg0MR3BJk+jSpmXWn2q9MOmQ== X-Received: by 2002:a17:907:1b26:b0:6ef:eaca:d2d8 with SMTP id mp38-20020a1709071b2600b006efeacad2d8mr17607322ejc.604.1651608499949; Tue, 03 May 2022 13:08:19 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ml11-20020a170906cc0b00b006f3ef214e59sm4967466ejb.191.2022.05.03.13.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:08:19 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v4 3/5] drivers: thermal: tsens: allow configuring min and max trips Date: Tue, 3 May 2022 22:08:11 +0200 Message-Id: <20220503200813.4020698-3-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200813.4020698-1-robimarko@gmail.com> References: <20220503200813.4020698-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 and IPQ6018 dont support negative trip temperatures and support up to 204 degrees C as the max trip temperature. So, instead of always setting the -40 as min and 120 degrees C as max allow it to be configured as part of the features. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-8960.c | 2 ++ drivers/thermal/qcom/tsens-v0_1.c | 2 ++ drivers/thermal/qcom/tsens-v1.c | 2 ++ drivers/thermal/qcom/tsens-v2.c | 2 ++ drivers/thermal/qcom/tsens.c | 4 ++-- drivers/thermal/qcom/tsens.h | 4 ++++ 6 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index ee584e5b07e5..4585904fb380 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_feat = { .adc = 1, .srot_split = 0, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; struct tsens_plat_data data_8960 = { diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 6effb822bf3c..2c203ff374e6 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -543,6 +543,8 @@ static struct tsens_features tsens_v0_1_feat = { .adc = 1, .srot_split = 1, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index a4f561a6e582..1d7f8a80bd13 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -306,6 +306,8 @@ static struct tsens_features tsens_v1_feat = { .adc = 1, .srot_split = 1, .max_sensors = 11, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 129cdb247381..9babc69bfd22 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_feat = { .adc = 0, .srot_split = 1, .max_sensors = 16, + .trip_min_temp = -40000, + .trip_max_temp = 120000, }; static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 69b6f7b97e9e..b7701d5efdfc 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -572,8 +572,8 @@ static int tsens_set_trips(void *_sensor, int low, int high) dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); - cl_high = clamp_val(high, -40000, 120000); - cl_low = clamp_val(low, -40000, 120000); + cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp); + cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp); high_val = tsens_mC_to_hw(s, cl_high); low_val = tsens_mC_to_hw(s, cl_low); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 4614177944d6..747004476347 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -501,6 +501,8 @@ enum regfield_ids { * with SROT only being available to secure boot firmware? * @has_watchdog: does this IP support watchdog functionality? * @max_sensors: maximum sensors supported by this version of the IP + * @trip_min_temp: minimum trip temperature supported by this version of the IP + * @trip_max_temp: maximum trip temperature supported by this version of the IP */ struct tsens_features { unsigned int ver_major; @@ -510,6 +512,8 @@ struct tsens_features { unsigned int srot_split:1; unsigned int has_watchdog:1; unsigned int max_sensors; + int trip_min_temp; + int trip_max_temp; }; /** From patchwork Tue May 3 20:08:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24A33C433FE for ; Tue, 3 May 2022 20:08:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242000AbiECUM1 (ORCPT ); Tue, 3 May 2022 16:12:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242250AbiECUMV (ORCPT ); Tue, 3 May 2022 16:12:21 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D6034093C; Tue, 3 May 2022 13:08:23 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id g23so21070199edy.13; Tue, 03 May 2022 13:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WTxPRlSp8k/tQZEOjjNIb49rT6gGrw+y6fIhsPtqfJw=; b=U+4hBfSOv9Abvqqi+SKK7arXEjCuYzM+IVRVZ6f0Ajq6bHA0VsHYdpooYARsGwQXy8 VZnQ/0gA8g8bn97eeSU4xsMyr6CWQHQJcCzbQKxc/r5Ed0mNSNMi3S92X7lX9zUierQ6 JuOJr9qpsMK7YsJEqk7KOKDXri8Z4ONs7Z2bo0pfpBKHpIbx+Vwy4qjyp26cwZ7X18BJ 0mKEfzb2ZzUQcrgHYaTvCfrs9rFpWbxS3haPbxc5swktPAx/2kCfQ9XjKT8ku+gl8Yuk UyKOkniBnGrquSdtT3vu02SvtNcZW+xRKpyie512TKCNv44XN1UksBkpEhXnVGrvvPkw xGwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WTxPRlSp8k/tQZEOjjNIb49rT6gGrw+y6fIhsPtqfJw=; b=Q+Ak0pkqsfT3W65t6fcvJDd8HPjUxTjjPFj2V5YWPHV2JtByayCua7NXvJsBp1dFrs Qkfy7r66wjLwSRRKXe98n89ckzHQSQByK2yOwDgUnqp1cA57SOtyKoMVpenYiG/WyDZX wnk4muFir7puk/8kF4C/Pa5oF9lwRypxJuV7z7zvPr5ZU1jN2775f6FM2lO0rpXVl/E1 7Ayq6tkUyoxiNOvsNPAJ5XM2B2zm0p4XF6/MckQaAHykXRSbsdDMxVZuYTTN3z+J+1TS R4B0hIzrgnfjXKqswDmO2wKJO5RNOQ/6w7hqwqgZaI9qAYlpVmK++ykBaK7Aq/RO7aGP 2kXA== X-Gm-Message-State: AOAM530yIrFo/pwFV30voCZQu+sKIasyF7Rk8CiT64x+l093w2+yEBOU B1P/qyKF1SYpd1BWT9353JI= X-Google-Smtp-Source: ABdhPJxzLXZX/4fzon2yUiUfry6PLx3nQQFep3+kyJROygcA//BHXoh8imiCaSFh+ETPQxcWCvTyHw== X-Received: by 2002:a05:6402:2204:b0:426:34f1:1d2d with SMTP id cq4-20020a056402220400b0042634f11d2dmr19684916edb.335.1651608501590; Tue, 03 May 2022 13:08:21 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ml11-20020a170906cc0b00b006f3ef214e59sm4967466ejb.191.2022.05.03.13.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:08:21 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v4 4/5] drivers: thermal: tsens: add IPQ8074 support Date: Tue, 3 May 2022 22:08:12 +0200 Message-Id: <20220503200813.4020698-4-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200813.4020698-1-robimarko@gmail.com> References: <20220503200813.4020698-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP it only has one IRQ, that is used for up/low as well as critical. It also does not support negative trip temperatures. Signed-off-by: Robert Marko --- drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 9babc69bfd22..29a61d2d6ca3 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_feat = { .trip_max_temp = 120000, }; +static struct tsens_features ipq8074_feat = { + .ver_major = VER_2_X, + .crit_int = 1, + .combo_int = 1, + .adc = 0, + .srot_split = 1, + .max_sensors = 16, + .trip_min_temp = 0, + .trip_max_temp = 204000, +}; + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* ----- SROT ------ */ /* VERSION */ @@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = { .fields = tsens_v2_regfields, }; +struct tsens_plat_data data_ipq8074 = { + .ops = &ops_generic_v2, + .feat = &ipq8074_feat, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b7701d5efdfc..3624daaaf34b 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -990,6 +990,9 @@ static const struct of_device_id tsens_table[] = { { .compatible = "qcom,ipq8064-tsens", .data = &data_8960, + }, { + .compatible = "qcom,ipq8074-tsens", + .data = &data_ipq8074, }, { .compatible = "qcom,mdm9607-tsens", .data = &data_9607, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 747004476347..8dd990d944ad 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -599,6 +599,6 @@ extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; extern struct tsens_plat_data data_tsens_v1, data_8976; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */ From patchwork Tue May 3 20:08:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12836177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB0E3C433F5 for ; Tue, 3 May 2022 20:08:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242197AbiECUM2 (ORCPT ); Tue, 3 May 2022 16:12:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242251AbiECUMV (ORCPT ); Tue, 3 May 2022 16:12:21 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2100D40A37; Tue, 3 May 2022 13:08:25 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id kq17so35482515ejb.4; Tue, 03 May 2022 13:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7ksfYzQBn7UrcwfXPR8oQDY9eW9oGago9RfblkVMga0=; b=VcB/8mDr7B/QpyxZzzrObUbZ+95m4H+eIVF/wEma6mOfotaINcmvoWBAhG1PaSEjai mohNNrU2nw7CAvy+27KSzxaRXMbiOrnhRdKUysTaJ3IXDRt+e84c3VQCRUBPulxrThc5 GwNixJ9GVCt4MGP/diptbCKM1Pd7lYH3qHuL83P3qm1xdI1+NJOqmmPZWJOU3zCenliB fmRDUhJ5U1cJsUaLAEcbNqxTLXkBpdHFKpLxtsY4UyIQdDWCxjJooTMDkmldF1RHaR9q yONE3sqt/2TeYVltjmIXBSJ75aCWT6wOMwNw638qoDJ+n+C5JxNCK7wUqp18eWZkLoHR OPRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7ksfYzQBn7UrcwfXPR8oQDY9eW9oGago9RfblkVMga0=; b=g8lHItXs+/GGCp0Xp1D0d/JAlSapbNYavaAf+CuN2ts8/28PRwVjslEM1G4zAvXLK+ 31CEM/FJrYVCepl7Uo8PU/4e+uXlDWqNe2mXqeqG/t3pHIb9Mg4CN9jxgjaV1ngnjxEQ vcBoSRr7HplKfkziuWIT0O0ByhlzI7SwE6hMAUboBUDDR8uHxBSq9EU6SUx4g8xnwn2K x+x/LVJgqK9rNlmfUtxcsLyBlczgCyf0GOmlad1fWQSZSxtSdvpbmutTZ6w2IkmXGt3L 6BatYILZ3IyTl8Eys0c1r2I8yoEq71yBqbDqNBfocRL5qQSXhjlSC/e55dkRx0+YHk1A 4Fmw== X-Gm-Message-State: AOAM533QZthNlyuQJfpwORSN23BHiiSLJQS3KW+nXcecR/LNY7IwkPE6 +8LhsIc879uyCe5vVlxsr+Sv+vUFJrQVdw== X-Google-Smtp-Source: ABdhPJw/HLcxIahYk3IaAToNtTuBPKVfrMwHL4jiawxkpG0W6d5ff3I+os9AXFjZIPLhgpVAvN9UAg== X-Received: by 2002:a17:906:58c7:b0:6da:955b:d300 with SMTP id e7-20020a17090658c700b006da955bd300mr17111983ejs.481.1651608503681; Tue, 03 May 2022 13:08:23 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-96-149.xnet.hr. [88.207.96.149]) by smtp.googlemail.com with ESMTPSA id ml11-20020a170906cc0b00b006f3ef214e59sm4967466ejb.191.2022.05.03.13.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 13:08:23 -0700 (PDT) From: Robert Marko To: amitk@kernel.org, thara.gopinath@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org, rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v4 5/5] arm64: dts: ipq8074: add thermal nodes Date: Tue, 3 May 2022 22:08:13 +0200 Message-Id: <20220503200813.4020698-5-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503200813.4020698-1-robimarko@gmail.com> References: <20220503200813.4020698-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the die. So lets add the tsens and thermal zone nodes, passive CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index afbae86cf6d3..76e02490b968 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -332,6 +332,16 @@ prng: rng@e3000 { status = "disabled"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq8074-tsens"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00704000 0x20000>; @@ -1092,4 +1102,90 @@ wifi: wifi@c0000000 { status = "disabled"; }; }; + + thermal-zones { + nss-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + }; + + nss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + }; + + nss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + }; + + wcss-phya0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + }; + + wcss-phya1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + }; + + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 10>; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 11>; + }; + + cpu3_thermal: cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 12>; + }; + + cluster_thermal: cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 13>; + }; + + wcss-phyb0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 14>; + }; + + wcss-phyb1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 15>; + }; + }; };