From patchwork Tue May 3 21:19:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 12836331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A679C433F5 for ; Tue, 3 May 2022 21:17:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239708AbiECVVR (ORCPT ); Tue, 3 May 2022 17:21:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242710AbiECVVQ (ORCPT ); Tue, 3 May 2022 17:21:16 -0400 Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADFDF40A12 for ; Tue, 3 May 2022 14:17:42 -0700 (PDT) Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-e93ff05b23so18457817fac.9 for ; Tue, 03 May 2022 14:17:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yWbhsf8P98l/EiH5gI2ubgolPhW/0b1/YN7RGLxWPF4=; b=vgurpuY/jnW3VAquoYo68gT2IDasRteb+8B5Ot20rlH7g1qC0K73nKWhGCaACAtKrL UC5J14kj4pnvxrI/VU0uCB8iz6lBfGs5bOf9fcv87+N3NJL0hUQcIF+dG4xQuexcend7 JnkzWfUqUz1qjsreJfztWVjVqVBpG3uPBsUWEF6FCWrUwX0pPXrqY1BYQ7c42mOcrcmf Qc7mgFrfAs1H3cx4n4whLgpAPxz4Af4YvVBTOdeEBAJqPiAgsNw5ofkMMOH/m4E2pKQx gwSOc1NbnHhxDGeupZlyyo6UnlbfvVYZySpmUtu+NmFfJqf8OXZagMFfkcQqBl9HXpSs /4dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yWbhsf8P98l/EiH5gI2ubgolPhW/0b1/YN7RGLxWPF4=; b=ahFyDL7ZFgS7Uutdf1tszZ4osMoSKT6dhy/BPJJM4HqQr12Zz/dgiiJJDQKR0vZuWr W8MPJ7whxiehIFjgNVplcHdWaNrEb9jGP3EEMyXzLVOUOupPiy83s9TYXFDCFlcJuCpo 4qnlSSn3Xu9VFa2efmGXzD6tyNQ7JY5+nyoxe6WDRhT4U+FBN5JX+KcyDMyImBp5boeX REY9HS54hpQBYdnA0yxvkkr5VJ8PNiNawBwp39DFI7sKaFUfu7CQq0lQNe2YkSl5cn0F MPrAnlJCiWB5Mv5BVooOJl5aPYDxmLeMUHIUvRpx9/e7uVG8/qXqE2nlmOU/TLmEXRA5 QiwQ== X-Gm-Message-State: AOAM530pCTWphFS88AaG4QZ8GJfp4ROuhFU/xVoK3t+ixXDFEp3n/7M2 CZ8ndNji950qDBvC3MtIBmD9aA== X-Google-Smtp-Source: ABdhPJzQFCROhKyiY4KKxw7AbEgDdlqk3c4Fy++A5wNWSRcnQUbUeP/RfPtsAFmlttK4wQomi2QTvw== X-Received: by 2002:a05:6870:304c:b0:e9:8c5c:3c34 with SMTP id u12-20020a056870304c00b000e98c5c3c34mr2540190oau.169.1651612661997; Tue, 03 May 2022 14:17:41 -0700 (PDT) Received: from ripper.. (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id b3-20020a056830104300b0060603221263sm4305906otp.51.2022.05.03.14.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 14:17:41 -0700 (PDT) From: Bjorn Andersson To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Steev Klimaszewski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: interconnect: Add SC8180X QUP0 virt provider Date: Tue, 3 May 2022 14:19:22 -0700 Message-Id: <20220503211925.1022169-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503211925.1022169-1-bjorn.andersson@linaro.org> References: <20220503211925.1022169-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add compatible for the QUP0 BCM provider found in SC8180X. Signed-off-by: Bjorn Andersson Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index fae3363fed02..cf684640fe6d 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -59,6 +59,7 @@ properties: - qcom,sc8180x-ipa-virt - qcom,sc8180x-mc-virt - qcom,sc8180x-mmss-noc + - qcom,sc8180x-qup-virt - qcom,sc8180x-system-noc - qcom,sc8280xp-aggre1-noc - qcom,sc8280xp-aggre2-noc From patchwork Tue May 3 21:19:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 12836332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AE1CC433EF for ; Tue, 3 May 2022 21:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242710AbiECVVT (ORCPT ); Tue, 3 May 2022 17:21:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242726AbiECVVR (ORCPT ); Tue, 3 May 2022 17:21:17 -0400 Received: from mail-oo1-xc2a.google.com (mail-oo1-xc2a.google.com [IPv6:2607:f8b0:4864:20::c2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A867240921 for ; Tue, 3 May 2022 14:17:43 -0700 (PDT) Received: by mail-oo1-xc2a.google.com with SMTP id q73-20020a4a334c000000b0035eb110dd0dso2503580ooq.10 for ; Tue, 03 May 2022 14:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G/4H8B/Rtj6Gbw/X7Ko9Cs2NaKraCTutfr1bJWw/laU=; b=gPm6e1vXbSqA/vxl+I6ZnWOUs+DAlSqrtdMRd9BZ9hSmXsQD5LSfbbPeHsHZzhDw3B ZVUqAxAKCpQ/xP+hmF/rzAxC/2qGXlKhq0M4uu2J8vIFDDfzz1ZzHnAA0z+dl/dMqHNV +yCz9dsAQDW7q2ogUz8DmoBAJuZyJh3uu4zvGjKjHQI45D44up//9alq+rsm6YsjhuyM sX0mxotyEumP96dbyUnHT/UhIL7P+9OgpWgTDLzG/PmxsZ4Eu8Y9y5yFLJuI0R+g69io KzJeGRodUvLGLTmHqBbzm//sy5Cw9myycGLZRkLzW/cIWelHyPwsW9wJWLI7pJQQozqL FVCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G/4H8B/Rtj6Gbw/X7Ko9Cs2NaKraCTutfr1bJWw/laU=; b=Ad5mHxMTwLfso04mmjeS0IhY3HuiL/5qkTAS7W1LYRvQ04IuRURgWefBlcx4p67t9d pIFRWBfs3pVwa9F6h2ICbR/1tY5Ws4qKFtQmPHHQhUEDndu5yIh7sWC5UttpkT1UrIWH Rustq2ms6oBdvxCCVhIjLu5bMUqQdm8sRPDzY3y+O3gtHH7sYYxMGxEloBb4Mlpcq07U /Rge8zRRP7EBzcFZBbV5b4j5gY3OMFhBBWq4O0GBOh7xHbWITPkToyaA9pIMxdKh+PyE Kl/7mOcWhXwow2hUiKD7crGp9KCh+6dUbIfx591xgVLEQdZC9b3zYFr9DKJ4QqjmF8sm 0J1A== X-Gm-Message-State: AOAM5338N79FNSTJscwbHwUM8Xa+fUbVbA4Fh2vcAhLMHDV+hmlKS+TX PMDa2hds0xxGj+tdvGIDw2otIQ== X-Google-Smtp-Source: ABdhPJyNNYOpSOkCK75gMPnwtMcQXNofLeMQzHCto/3PAuV1Mki7pz2MkqCXA3en8kikedFN1gvXmA== X-Received: by 2002:a4a:e694:0:b0:35e:99e7:80e4 with SMTP id u20-20020a4ae694000000b0035e99e780e4mr6368669oot.97.1651612662998; Tue, 03 May 2022 14:17:42 -0700 (PDT) Received: from ripper.. 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id b3-20020a056830104300b0060603221263sm4305906otp.51.2022.05.03.14.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 14:17:42 -0700 (PDT) From: Bjorn Andersson To: Georgi Djakov , Steev Klimaszewski Cc: Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] interconnect: qcom: sc8180x: Modernize sc8180x probe Date: Tue, 3 May 2022 14:19:23 -0700 Message-Id: <20220503211925.1022169-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503211925.1022169-1-bjorn.andersson@linaro.org> References: <20220503211925.1022169-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The introduction of the Qualcomm SC8180X provider raced with the refactoring of the RPMh common code and SC8180X was left with the old style of duplicating the probe function in each provider driver. Transition the driver to the "new" design. Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/sc8180x.c | 95 +---------------------------- 1 file changed, 2 insertions(+), 93 deletions(-) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 136c62afb3b2..467083661559 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -503,97 +503,6 @@ static const struct qcom_icc_desc sc8180x_system_noc = { .num_bcms = ARRAY_SIZE(system_noc_bcms), }; -static int qnoc_probe(struct platform_device *pdev) -{ - const struct qcom_icc_desc *desc; - struct icc_onecell_data *data; - struct icc_provider *provider; - struct qcom_icc_node * const *qnodes; - struct qcom_icc_provider *qp; - struct icc_node *node; - size_t num_nodes, i; - int ret; - - desc = device_get_match_data(&pdev->dev); - if (!desc) - return -EINVAL; - - qnodes = desc->nodes; - num_nodes = desc->num_nodes; - - qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); - if (!qp) - return -ENOMEM; - - data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); - if (!data) - return -ENOMEM; - - provider = &qp->provider; - provider->dev = &pdev->dev; - provider->set = qcom_icc_set; - provider->pre_aggregate = qcom_icc_pre_aggregate; - provider->aggregate = qcom_icc_aggregate; - provider->xlate = of_icc_xlate_onecell; - INIT_LIST_HEAD(&provider->nodes); - provider->data = data; - - qp->dev = &pdev->dev; - qp->bcms = desc->bcms; - qp->num_bcms = desc->num_bcms; - - qp->voter = of_bcm_voter_get(qp->dev, NULL); - if (IS_ERR(qp->voter)) - return PTR_ERR(qp->voter); - - ret = icc_provider_add(provider); - if (ret) { - dev_err(&pdev->dev, "error adding interconnect provider\n"); - return ret; - } - - for (i = 0; i < qp->num_bcms; i++) - qcom_icc_bcm_init(qp->bcms[i], &pdev->dev); - - for (i = 0; i < num_nodes; i++) { - size_t j; - - if (!qnodes[i]) - continue; - - node = icc_node_create(qnodes[i]->id); - if (IS_ERR(node)) { - ret = PTR_ERR(node); - goto err; - } - - node->name = qnodes[i]->name; - node->data = qnodes[i]; - icc_node_add(node, provider); - - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - - data->nodes[i] = node; - } - data->num_nodes = num_nodes; - - platform_set_drvdata(pdev, qp); - - return 0; -err: - icc_nodes_remove(provider); - icc_provider_del(provider); - return ret; -} - -static int qnoc_remove(struct platform_device *pdev) -{ - struct qcom_icc_provider *qp = platform_get_drvdata(pdev); - - icc_nodes_remove(&qp->provider); - return icc_provider_del(&qp->provider); -} static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc }, @@ -612,8 +521,8 @@ static const struct of_device_id qnoc_of_match[] = { MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { - .probe = qnoc_probe, - .remove = qnoc_remove, + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sc8180x", .of_match_table = qnoc_of_match, From patchwork Tue May 3 21:19:24 2022 Content-Type: text/plain; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id b3-20020a056830104300b0060603221263sm4305906otp.51.2022.05.03.14.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 14:17:43 -0700 (PDT) From: Bjorn Andersson To: Georgi Djakov , Steev Klimaszewski Cc: Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] interconnect: qcom: sc8180x: Fix QUP0 nodes Date: Tue, 3 May 2022 14:19:24 -0700 Message-Id: <20220503211925.1022169-4-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503211925.1022169-1-bjorn.andersson@linaro.org> References: <20220503211925.1022169-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The QUP0 BCM relates to some internal property of the QUPs, and should be configured independently of the path to the QUP. In line with other platforms expose QUP_CORE endpoints in order allow this configuration. Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/sc8180x.c | 30 +++++++++++++++++-- drivers/interconnect/qcom/sc8180x.h | 7 +++++ .../dt-bindings/interconnect/qcom,sc8180x.h | 7 +++++ 3 files changed, 41 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 467083661559..86500d05caa3 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -76,6 +76,9 @@ DEFINE_QNODE(mas_qnm_aggre2_noc, SC8180X_A2NOC_SNOC_MAS, 1, 16, SC8180X_SLAVE_SN DEFINE_QNODE(mas_qnm_gemnoc, SC8180X_MASTER_GEM_NOC_SNOC, 1, 8, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM); DEFINE_QNODE(mas_qxm_pimem, SC8180X_MASTER_PIMEM, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); DEFINE_QNODE(mas_xm_gic, SC8180X_MASTER_GIC, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); +DEFINE_QNODE(mas_qup_core_0, SC8180X_MASTER_QUP_CORE_0, 1, 4, SC8180X_SLAVE_QUP_CORE_0); +DEFINE_QNODE(mas_qup_core_1, SC8180X_MASTER_QUP_CORE_1, 1, 4, SC8180X_SLAVE_QUP_CORE_1); +DEFINE_QNODE(mas_qup_core_2, SC8180X_MASTER_QUP_CORE_2, 1, 4, SC8180X_SLAVE_QUP_CORE_2); DEFINE_QNODE(slv_qns_a1noc_snoc, SC8180X_A1NOC_SNOC_SLV, 1, 32, SC8180X_A1NOC_SNOC_MAS); DEFINE_QNODE(slv_srvc_aggre1_noc, SC8180X_SLAVE_SERVICE_A1NOC, 1, 4); DEFINE_QNODE(slv_qns_a2noc_snoc, SC8180X_A2NOC_SNOC_SLV, 1, 16, SC8180X_A2NOC_SNOC_MAS); @@ -165,6 +168,9 @@ DEFINE_QNODE(slv_xs_pcie_2, SC8180X_SLAVE_PCIE_2, 1, 8); DEFINE_QNODE(slv_xs_pcie_3, SC8180X_SLAVE_PCIE_3, 1, 8); DEFINE_QNODE(slv_xs_qdss_stm, SC8180X_SLAVE_QDSS_STM, 1, 4); DEFINE_QNODE(slv_xs_sys_tcu_cfg, SC8180X_SLAVE_TCU, 1, 8); +DEFINE_QNODE(slv_qup_core_0, SC8180X_SLAVE_QUP_CORE_0, 1, 4); +DEFINE_QNODE(slv_qup_core_1, SC8180X_SLAVE_QUP_CORE_1, 1, 4); +DEFINE_QNODE(slv_qup_core_2, SC8180X_SLAVE_QUP_CORE_2, 1, 4); DEFINE_QBCM(bcm_acv, "ACV", false, &slv_ebi); DEFINE_QBCM(bcm_mc0, "MC0", false, &slv_ebi); @@ -174,7 +180,7 @@ DEFINE_QBCM(bcm_co0, "CO0", false, &slv_qns_cdsp_mem_noc); DEFINE_QBCM(bcm_ce0, "CE0", false, &mas_qxm_crypto); DEFINE_QBCM(bcm_cn0, "CN0", false, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qhs_ahb2phy_refgen_center, &slv_qhs_ahb2phy_refgen_east, &slv_qhs_ahb2phy_refgen_west, &slv_qhs_ahb2phy_south, &slv_qhs_aop, &slv_qhs_aoss, &slv_qhs_camera_cfg, &slv_qhs_clk_ctl, &slv_qhs_compute_dsp, &slv_qhs_cpr_cx, &slv_qhs_cpr_mmcx, &slv_qhs_cpr_mx, &slv_qhs_crypto0_cfg, &slv_qhs_ddrss_cfg, &slv_qhs_display_cfg, &slv_qhs_emac_cfg, &slv_qhs_glm, &slv_qhs_gpuss_cfg, &slv_qhs_imem_cfg, &slv_qhs_ipa, &slv_qhs_mnoc_cfg, &slv_qhs_npu_cfg, &slv_qhs_pcie0_cfg, &slv_qhs_pcie1_cfg, &slv_qhs_pcie2_cfg, &slv_qhs_pcie3_cfg, &slv_qhs_pdm, &slv_qhs_pimem_cfg, &slv_qhs_prng, &slv_qhs_qdss_cfg, &slv_qhs_qspi_0, &slv_qhs_qspi_1, &slv_qhs_qupv3_east0, &slv_qhs_qupv3_east1, &slv_qhs_qupv3_west, &slv_qhs_sdc2, &slv_qhs_sdc4, &slv_qhs_security, &slv_qhs_snoc_cfg, &slv_qhs_spss_cfg, &slv_qhs_tcsr, &slv_qhs_tlmm_east, &slv_qhs_tlmm_south, &slv_qhs_tlmm_west, &slv_qhs_tsif, &slv_qhs_ufs_card_cfg, &slv_qhs_ufs_mem0_cfg, &slv_qhs_ufs_mem1_cfg, &slv_qhs_usb3_0, &slv_qhs_usb3_1, &slv_qhs_usb3_2, &slv_qhs_venus_cfg, &slv_qhs_vsense_ctrl_cfg, &slv_srvc_cnoc); DEFINE_QBCM(bcm_mm1, "MM1", false, &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, &mas_qxm_camnoc_sf_uncomp, &mas_qxm_camnoc_hf0, &mas_qxm_camnoc_hf1, &mas_qxm_mdp0, &mas_qxm_mdp1); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qhm_qup0, &mas_qhm_qup1, &mas_qhm_qup2); +DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qup_core_0, &mas_qup_core_1, &mas_qup_core_2); DEFINE_QBCM(bcm_sh2, "SH2", false, &slv_qns_gem_noc_snoc); DEFINE_QBCM(bcm_mm2, "MM2", false, &mas_qxm_camnoc_sf, &mas_qxm_rot, &mas_qxm_venus0, &mas_qxm_venus1, &mas_qxm_venus_arm9, &slv_qns2_mem_noc); DEFINE_QBCM(bcm_sh3, "SH3", false, &mas_acm_apps); @@ -194,13 +200,11 @@ DEFINE_QBCM(bcm_sn15, "SN15", false, &mas_qnm_gemnoc); static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn3, &bcm_ce0, - &bcm_qup0, }; static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_sn14, &bcm_ce0, - &bcm_qup0, }; static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { @@ -503,6 +507,25 @@ static const struct qcom_icc_desc sc8180x_system_noc = { .num_bcms = ARRAY_SIZE(system_noc_bcms), }; +static struct qcom_icc_bcm * const qup_virt_bcms[] = { + &bcm_qup0, +}; + +static struct qcom_icc_node *qup_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &mas_qup_core_0, + [MASTER_QUP_CORE_1] = &mas_qup_core_1, + [MASTER_QUP_CORE_2] = &mas_qup_core_2, + [SLAVE_QUP_CORE_0] = &slv_qup_core_0, + [SLAVE_QUP_CORE_1] = &slv_qup_core_1, + [SLAVE_QUP_CORE_2] = &slv_qup_core_2, +}; + +static const struct qcom_icc_desc sc8180x_qup_virt = { + .nodes = qup_virt_nodes, + .num_nodes = ARRAY_SIZE(qup_virt_nodes), + .bcms = qup_virt_bcms, + .num_bcms = ARRAY_SIZE(qup_virt_bcms), +}; static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc }, @@ -515,6 +538,7 @@ static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt }, { .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt }, { .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc }, + { .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt }, { .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc }, { } }; diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qcom/sc8180x.h index e70cf7032f80..2eafd35543c7 100644 --- a/drivers/interconnect/qcom/sc8180x.h +++ b/drivers/interconnect/qcom/sc8180x.h @@ -171,4 +171,11 @@ #define SC8180X_MASTER_OSM_L3_APPS 161 #define SC8180X_SLAVE_OSM_L3 162 +#define SC8180X_MASTER_QUP_CORE_0 163 +#define SC8180X_MASTER_QUP_CORE_1 164 +#define SC8180X_MASTER_QUP_CORE_2 165 +#define SC8180X_SLAVE_QUP_CORE_0 166 +#define SC8180X_SLAVE_QUP_CORE_1 167 +#define SC8180X_SLAVE_QUP_CORE_2 168 + #endif diff --git a/include/dt-bindings/interconnect/qcom,sc8180x.h b/include/dt-bindings/interconnect/qcom,sc8180x.h index 235b525d2803..e84cfec5afdd 100644 --- a/include/dt-bindings/interconnect/qcom,sc8180x.h +++ b/include/dt-bindings/interconnect/qcom,sc8180x.h @@ -182,4 +182,11 @@ #define SLAVE_MNOC_SF_MEM_NOC_DISPLAY 3 #define SLAVE_MNOC_HF_MEM_NOC_DISPLAY 4 +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + #endif From patchwork Tue May 3 21:19:25 2022 Content-Type: text/plain; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id b3-20020a056830104300b0060603221263sm4305906otp.51.2022.05.03.14.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 14:17:44 -0700 (PDT) From: Bjorn Andersson To: Georgi Djakov , Steev Klimaszewski Cc: Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] interconnect: qcom: sc8180x: Mark some BCMs keepalive Date: Tue, 3 May 2022 14:19:25 -0700 Message-Id: <20220503211925.1022169-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503211925.1022169-1-bjorn.andersson@linaro.org> References: <20220503211925.1022169-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org In line with other platforms, mark BCMs controlling paths between the CPU, AOSS, GIC and memory as keepalive. Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/sc8180x.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 86500d05caa3..1a9a39ab9c05 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -173,29 +173,29 @@ DEFINE_QNODE(slv_qup_core_1, SC8180X_SLAVE_QUP_CORE_1, 1, 4); DEFINE_QNODE(slv_qup_core_2, SC8180X_SLAVE_QUP_CORE_2, 1, 4); DEFINE_QBCM(bcm_acv, "ACV", false, &slv_ebi); -DEFINE_QBCM(bcm_mc0, "MC0", false, &slv_ebi); -DEFINE_QBCM(bcm_sh0, "SH0", false, &slv_qns_llcc); +DEFINE_QBCM(bcm_mc0, "MC0", true, &slv_ebi); +DEFINE_QBCM(bcm_sh0, "SH0", true, &slv_qns_llcc); DEFINE_QBCM(bcm_mm0, "MM0", false, &slv_qns_mem_noc_hf); DEFINE_QBCM(bcm_co0, "CO0", false, &slv_qns_cdsp_mem_noc); DEFINE_QBCM(bcm_ce0, "CE0", false, &mas_qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", false, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qhs_ahb2phy_refgen_center, &slv_qhs_ahb2phy_refgen_east, &slv_qhs_ahb2phy_refgen_west, &slv_qhs_ahb2phy_south, &slv_qhs_aop, &slv_qhs_aoss, &slv_qhs_camera_cfg, &slv_qhs_clk_ctl, &slv_qhs_compute_dsp, &slv_qhs_cpr_cx, &slv_qhs_cpr_mmcx, &slv_qhs_cpr_mx, &slv_qhs_crypto0_cfg, &slv_qhs_ddrss_cfg, &slv_qhs_display_cfg, &slv_qhs_emac_cfg, &slv_qhs_glm, &slv_qhs_gpuss_cfg, &slv_qhs_imem_cfg, &slv_qhs_ipa, &slv_qhs_mnoc_cfg, &slv_qhs_npu_cfg, &slv_qhs_pcie0_cfg, &slv_qhs_pcie1_cfg, &slv_qhs_pcie2_cfg, &slv_qhs_pcie3_cfg, &slv_qhs_pdm, &slv_qhs_pimem_cfg, &slv_qhs_prng, &slv_qhs_qdss_cfg, &slv_qhs_qspi_0, &slv_qhs_qspi_1, &slv_qhs_qupv3_east0, &slv_qhs_qupv3_east1, &slv_qhs_qupv3_west, &slv_qhs_sdc2, &slv_qhs_sdc4, &slv_qhs_security, &slv_qhs_snoc_cfg, &slv_qhs_spss_cfg, &slv_qhs_tcsr, &slv_qhs_tlmm_east, &slv_qhs_tlmm_south, &slv_qhs_tlmm_west, &slv_qhs_tsif, &slv_qhs_ufs_card_cfg, &slv_qhs_ufs_mem0_cfg, &slv_qhs_ufs_mem1_cfg, &slv_qhs_usb3_0, &slv_qhs_usb3_1, &slv_qhs_usb3_2, &slv_qhs_venus_cfg, &slv_qhs_vsense_ctrl_cfg, &slv_srvc_cnoc); +DEFINE_QBCM(bcm_cn0, "CN0", true, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qhs_ahb2phy_refgen_center, &slv_qhs_ahb2phy_refgen_east, &slv_qhs_ahb2phy_refgen_west, &slv_qhs_ahb2phy_south, &slv_qhs_aop, &slv_qhs_aoss, &slv_qhs_camera_cfg, &slv_qhs_clk_ctl, &slv_qhs_compute_dsp, &slv_qhs_cpr_cx, &slv_qhs_cpr_mmcx, &slv_qhs_cpr_mx, &slv_qhs_crypto0_cfg, &slv_qhs_ddrss_cfg, &slv_qhs_display_cfg, &slv_qhs_emac_cfg, &slv_qhs_glm, &slv_qhs_gpuss_cfg, &slv_qhs_imem_cfg, &slv_qhs_ipa, &slv_qhs_mnoc_cfg, &slv_qhs_npu_cfg, &slv_qhs_pcie0_cfg, &slv_qhs_pcie1_cfg, &slv_qhs_pcie2_cfg, &slv_qhs_pcie3_cfg, &slv_qhs_pdm, &slv_qhs_pimem_cfg, &slv_qhs_prng, &slv_qhs_qdss_cfg, &slv_qhs_qspi_0, &slv_qhs_qspi_1, &slv_qhs_qupv3_east0, &slv_qhs_qupv3_east1, &slv_qhs_qupv3_west, &slv_qhs_sdc2, &slv_qhs_sdc4, &slv_qhs_security, &slv_qhs_snoc_cfg, &slv_qhs_spss_cfg, &slv_qhs_tcsr, &slv_qhs_tlmm_east, &slv_qhs_tlmm_south, &slv_qhs_tlmm_west, &slv_qhs_tsif, &slv_qhs_ufs_card_cfg, &slv_qhs_ufs_mem0_cfg, &slv_qhs_ufs_mem1_cfg, &slv_qhs_usb3_0, &slv_qhs_usb3_1, &slv_qhs_usb3_2, &slv_qhs_venus_cfg, &slv_qhs_vsense_ctrl_cfg, &slv_srvc_cnoc); DEFINE_QBCM(bcm_mm1, "MM1", false, &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, &mas_qxm_camnoc_sf_uncomp, &mas_qxm_camnoc_hf0, &mas_qxm_camnoc_hf1, &mas_qxm_mdp0, &mas_qxm_mdp1); DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qup_core_0, &mas_qup_core_1, &mas_qup_core_2); DEFINE_QBCM(bcm_sh2, "SH2", false, &slv_qns_gem_noc_snoc); DEFINE_QBCM(bcm_mm2, "MM2", false, &mas_qxm_camnoc_sf, &mas_qxm_rot, &mas_qxm_venus0, &mas_qxm_venus1, &mas_qxm_venus_arm9, &slv_qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &mas_acm_apps); +DEFINE_QBCM(bcm_sh3, "SH3", true, &mas_acm_apps); DEFINE_QBCM(bcm_sn0, "SN0", false, &slv_qns_gemnoc_sf); DEFINE_QBCM(bcm_sn1, "SN1", false, &slv_qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &slv_qns_gemnoc_gc); +DEFINE_QBCM(bcm_sn2, "SN2", true, &slv_qns_gemnoc_gc); DEFINE_QBCM(bcm_co2, "CO2", false, &mas_qnm_npu); DEFINE_QBCM(bcm_ip0, "IP0", false, &slv_ipa_core_slave); -DEFINE_QBCM(bcm_sn3, "SN3", false, &slv_srvc_aggre1_noc, &slv_qns_cnoc); +DEFINE_QBCM(bcm_sn3, "SN3", true, &slv_srvc_aggre1_noc, &slv_qns_cnoc); DEFINE_QBCM(bcm_sn4, "SN4", false, &slv_qxs_pimem); DEFINE_QBCM(bcm_sn8, "SN8", false, &slv_xs_pcie_0, &slv_xs_pcie_1, &slv_xs_pcie_2, &slv_xs_pcie_3); DEFINE_QBCM(bcm_sn9, "SN9", false, &mas_qnm_aggre1_noc); DEFINE_QBCM(bcm_sn11, "SN11", false, &mas_qnm_aggre2_noc); DEFINE_QBCM(bcm_sn14, "SN14", false, &slv_qns_pcie_mem_noc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &mas_qnm_gemnoc); +DEFINE_QBCM(bcm_sn15, "SN15", true, &mas_qnm_gemnoc); static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn3, From patchwork Tue May 3 22:53:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 12836507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92632C433F5 for ; Tue, 3 May 2022 22:51:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243883AbiECWyy (ORCPT ); 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(104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id m4-20020a056870030400b000e686d13890sm7298561oaf.42.2022.05.03.15.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 15:51:13 -0700 (PDT) From: Bjorn Andersson To: Georgi Djakov , Steev Klimaszewski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/4] interconnect: qcom: sc8180x: Reformat node and bcm definitions Date: Tue, 3 May 2022 15:53:00 -0700 Message-Id: <20220503225300.1141814-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503211925.1022169-1-bjorn.andersson@linaro.org> References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Qualcomm interconnect providers started off defining nodes and BCMs using the DEFINE_QNODE() and DEFINE_QBCM() macros. Unfortunately this results in a block of long lines that are hard to read, a transition to explicitly stated definition has been made for newly introduced platforms. Transition the SC8180X interconnect provider driver to this style as well, to make it easier to read while debugging interconnect related issues. Signed-off-by: Bjorn Andersson --- Adding this to the series as a bonus. drivers/interconnect/qcom/sc8180x.c | 1740 ++++++++++++++++++++++++--- 1 file changed, 1559 insertions(+), 181 deletions(-) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 6a9d9954905e..0d70062e576e 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -15,187 +15,1565 @@ #include "icc-rpmh.h" #include "sc8180x.h" -DEFINE_QNODE(mas_qhm_a1noc_cfg, SC8180X_MASTER_A1NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(mas_xm_ufs_card, SC8180X_MASTER_UFS_CARD, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_ufs_g4, SC8180X_MASTER_UFS_GEN4, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_ufs_mem, SC8180X_MASTER_UFS_MEM, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_usb3_0, SC8180X_MASTER_USB3, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_usb3_1, SC8180X_MASTER_USB3_1, 1, 8, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_usb3_2, SC8180X_MASTER_USB3_2, 1, 16, SC8180X_A1NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_a2noc_cfg, SC8180X_MASTER_A2NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(mas_qhm_qdss_bam, SC8180X_MASTER_QDSS_BAM, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qspi, SC8180X_MASTER_QSPI_0, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qspi1, SC8180X_MASTER_QSPI_1, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qup0, SC8180X_MASTER_QUP_0, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qup1, SC8180X_MASTER_QUP_1, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_qup2, SC8180X_MASTER_QUP_2, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qhm_sensorss_ahb, SC8180X_MASTER_SENSORS_AHB, 1, 4, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qxm_crypto, SC8180X_MASTER_CRYPTO_CORE_0, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qxm_ipa, SC8180X_MASTER_IPA, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_emac, SC8180X_MASTER_EMAC, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_pcie3_0, SC8180X_MASTER_PCIE, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_pcie3_1, SC8180X_MASTER_PCIE_1, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_pcie3_2, SC8180X_MASTER_PCIE_2, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_pcie3_3, SC8180X_MASTER_PCIE_3, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(mas_xm_qdss_etr, SC8180X_MASTER_QDSS_ETR, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_sdc2, SC8180X_MASTER_SDCC_2, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_xm_sdc4, SC8180X_MASTER_SDCC_4, 1, 8, SC8180X_A2NOC_SNOC_SLV); -DEFINE_QNODE(mas_qxm_camnoc_hf0_uncomp, SC8180X_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(mas_qxm_camnoc_hf1_uncomp, SC8180X_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(mas_qxm_camnoc_sf_uncomp, SC8180X_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(mas_qnm_npu, SC8180X_MASTER_NPU, 1, 32, SC8180X_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(mas_qnm_snoc, SC8180X_SNOC_CNOC_MAS, 1, 8, SC8180X_SLAVE_TLMM_SOUTH, SC8180X_SLAVE_CDSP_CFG, SC8180X_SLAVE_SPSS_CFG, SC8180X_SLAVE_CAMERA_CFG, SC8180X_SLAVE_SDCC_4, SC8180X_SLAVE_AHB2PHY_CENTER, SC8180X_SLAVE_SDCC_2, SC8180X_SLAVE_PCIE_2_CFG, SC8180X_SLAVE_CNOC_MNOC_CFG, SC8180X_SLAVE_EMAC_CFG, SC8180X_SLAVE_QSPI_0, SC8180X_SLAVE_QSPI_1, SC8180X_SLAVE_TLMM_EAST, SC8180X_SLAVE_SNOC_CFG, SC8180X_SLAVE_AHB2PHY_EAST, SC8180X_SLAVE_GLM, SC8180X_SLAVE_PDM, SC8180X_SLAVE_PCIE_1_CFG, SC8180X_SLAVE_A2NOC_CFG, SC8180X_SLAVE_QDSS_CFG, SC8180X_SLAVE_DISPLAY_CFG, SC8180X_SLAVE_TCSR, SC8180X_SLAVE_UFS_MEM_0_CFG, SC8180X_SLAVE_CNOC_DDRSS, SC8180X_SLAVE_PCIE_0_CFG, SC8180X_SLAVE_QUP_1, SC8180X_SLAVE_QUP_2, SC8180X_SLAVE_NPU_CFG, SC8180X_SLAVE_CRYPTO_0_CFG, SC8180X_SLAVE_GRAPHICS_3D_CFG, SC8180X_SLAVE_VENUS_CFG, SC8180X_SLAVE_TSIF, SC8180X_SLAVE_IPA_CFG, SC8180X_SLAVE_CLK_CTL, SC8180X_SLAVE_SECURITY, SC8180X_SLAVE_AOP, SC8180X_SLAVE_AHB2PHY_WEST, SC8180X_SLAVE_AHB2PHY_SOUTH, SC8180X_SLAVE_SERVICE_CNOC, SC8180X_SLAVE_UFS_CARD_CFG, SC8180X_SLAVE_USB3_1, SC8180X_SLAVE_USB3_2, SC8180X_SLAVE_PCIE_3_CFG, SC8180X_SLAVE_RBCPR_CX_CFG, SC8180X_SLAVE_TLMM_WEST, SC8180X_SLAVE_A1NOC_CFG, SC8180X_SLAVE_AOSS, SC8180X_SLAVE_PRNG, SC8180X_SLAVE_VSENSE_CTRL_CFG, SC8180X_SLAVE_QUP_0, SC8180X_SLAVE_USB3, SC8180X_SLAVE_RBCPR_MMCX_CFG, SC8180X_SLAVE_PIMEM_CFG, SC8180X_SLAVE_UFS_MEM_1_CFG, SC8180X_SLAVE_RBCPR_MX_CFG, SC8180X_SLAVE_IMEM_CFG); -DEFINE_QNODE(mas_qhm_cnoc_dc_noc, SC8180X_MASTER_CNOC_DC_NOC, 1, 4, SC8180X_SLAVE_LLCC_CFG, SC8180X_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(mas_acm_apps, SC8180X_MASTER_AMPSS_M0, 4, 64, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_acm_gpu_tcu, SC8180X_MASTER_GPU_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_acm_sys_tcu, SC8180X_MASTER_SYS_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qhm_gemnoc_cfg, SC8180X_MASTER_GEM_NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_GEM_NOC_1, SC8180X_SLAVE_SERVICE_GEM_NOC, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(mas_qnm_cmpnoc, SC8180X_MASTER_COMPUTE_NOC, 2, 32, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_gpu, SC8180X_MASTER_GRAPHICS_3D, 4, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_mnoc_hf, SC8180X_MASTER_MNOC_HF_MEM_NOC, 2, 32, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_qnm_mnoc_sf, SC8180X_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_pcie, SC8180X_MASTER_GEM_NOC_PCIE_SNOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(mas_qnm_snoc_gc, SC8180X_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_qnm_snoc_sf, SC8180X_MASTER_SNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_qxm_ecc, SC8180X_MASTER_ECC, 2, 32, SC8180X_SLAVE_LLCC); -DEFINE_QNODE(mas_ipa_core_master, SC8180X_MASTER_IPA_CORE, 1, 8, SC8180X_SLAVE_IPA_CORE); -DEFINE_QNODE(mas_llcc_mc, SC8180X_MASTER_LLCC, 8, 4, SC8180X_SLAVE_EBI_CH0); -DEFINE_QNODE(mas_qhm_mnoc_cfg, SC8180X_MASTER_CNOC_MNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(mas_qxm_camnoc_hf0, SC8180X_MASTER_CAMNOC_HF0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_camnoc_hf1, SC8180X_MASTER_CAMNOC_HF1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_camnoc_sf, SC8180X_MASTER_CAMNOC_SF, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_mdp0, SC8180X_MASTER_MDP_PORT0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_mdp1, SC8180X_MASTER_MDP_PORT1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(mas_qxm_rot, SC8180X_MASTER_ROTATOR, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_venus0, SC8180X_MASTER_VIDEO_P0, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_venus1, SC8180X_MASTER_VIDEO_P1, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qxm_venus_arm9, SC8180X_MASTER_VIDEO_PROC, 1, 8, SC8180X_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(mas_qhm_snoc_cfg, SC8180X_MASTER_SNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(mas_qnm_aggre1_noc, SC8180X_A1NOC_SNOC_MAS, 1, 32, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_QDSS_STM); -DEFINE_QNODE(mas_qnm_aggre2_noc, SC8180X_A2NOC_SNOC_MAS, 1, 16, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_PCIE_3, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SLAVE_PCIE_2, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_PCIE_0, SC8180X_SLAVE_PCIE_1, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM); -DEFINE_QNODE(mas_qnm_gemnoc, SC8180X_MASTER_GEM_NOC_SNOC, 1, 8, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM); -DEFINE_QNODE(mas_qxm_pimem, SC8180X_MASTER_PIMEM, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); -DEFINE_QNODE(mas_xm_gic, SC8180X_MASTER_GIC, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); -DEFINE_QNODE(mas_qup_core_0, SC8180X_MASTER_QUP_CORE_0, 1, 4, SC8180X_SLAVE_QUP_CORE_0); -DEFINE_QNODE(mas_qup_core_1, SC8180X_MASTER_QUP_CORE_1, 1, 4, SC8180X_SLAVE_QUP_CORE_1); -DEFINE_QNODE(mas_qup_core_2, SC8180X_MASTER_QUP_CORE_2, 1, 4, SC8180X_SLAVE_QUP_CORE_2); -DEFINE_QNODE(slv_qns_a1noc_snoc, SC8180X_A1NOC_SNOC_SLV, 1, 32, SC8180X_A1NOC_SNOC_MAS); -DEFINE_QNODE(slv_srvc_aggre1_noc, SC8180X_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(slv_qns_a2noc_snoc, SC8180X_A2NOC_SNOC_SLV, 1, 16, SC8180X_A2NOC_SNOC_MAS); -DEFINE_QNODE(slv_qns_pcie_mem_noc, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, 1, 32, SC8180X_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(slv_srvc_aggre2_noc, SC8180X_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(slv_qns_camnoc_uncomp, SC8180X_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(slv_qns_cdsp_mem_noc, SC8180X_SLAVE_CDSP_MEM_NOC, 2, 32, SC8180X_MASTER_COMPUTE_NOC); -DEFINE_QNODE(slv_qhs_a1_noc_cfg, SC8180X_SLAVE_A1NOC_CFG, 1, 4, SC8180X_MASTER_A1NOC_CFG); -DEFINE_QNODE(slv_qhs_a2_noc_cfg, SC8180X_SLAVE_A2NOC_CFG, 1, 4, SC8180X_MASTER_A2NOC_CFG); -DEFINE_QNODE(slv_qhs_ahb2phy_refgen_center, SC8180X_SLAVE_AHB2PHY_CENTER, 1, 4); -DEFINE_QNODE(slv_qhs_ahb2phy_refgen_east, SC8180X_SLAVE_AHB2PHY_EAST, 1, 4); -DEFINE_QNODE(slv_qhs_ahb2phy_refgen_west, SC8180X_SLAVE_AHB2PHY_WEST, 1, 4); -DEFINE_QNODE(slv_qhs_ahb2phy_south, SC8180X_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(slv_qhs_aop, SC8180X_SLAVE_AOP, 1, 4); -DEFINE_QNODE(slv_qhs_aoss, SC8180X_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(slv_qhs_camera_cfg, SC8180X_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_clk_ctl, SC8180X_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(slv_qhs_compute_dsp, SC8180X_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_cpr_cx, SC8180X_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_cpr_mmcx, SC8180X_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_cpr_mx, SC8180X_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_crypto0_cfg, SC8180X_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ddrss_cfg, SC8180X_SLAVE_CNOC_DDRSS, 1, 4, SC8180X_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(slv_qhs_display_cfg, SC8180X_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_emac_cfg, SC8180X_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_glm, SC8180X_SLAVE_GLM, 1, 4); -DEFINE_QNODE(slv_qhs_gpuss_cfg, SC8180X_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(slv_qhs_imem_cfg, SC8180X_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ipa, SC8180X_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_mnoc_cfg, SC8180X_SLAVE_CNOC_MNOC_CFG, 1, 4, SC8180X_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(slv_qhs_npu_cfg, SC8180X_SLAVE_NPU_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie0_cfg, SC8180X_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie1_cfg, SC8180X_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie2_cfg, SC8180X_SLAVE_PCIE_2_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pcie3_cfg, SC8180X_SLAVE_PCIE_3_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_pdm, SC8180X_SLAVE_PDM, 1, 4); -DEFINE_QNODE(slv_qhs_pimem_cfg, SC8180X_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_prng, SC8180X_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(slv_qhs_qdss_cfg, SC8180X_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_qspi_0, SC8180X_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(slv_qhs_qspi_1, SC8180X_SLAVE_QSPI_1, 1, 4); -DEFINE_QNODE(slv_qhs_qupv3_east0, SC8180X_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(slv_qhs_qupv3_east1, SC8180X_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(slv_qhs_qupv3_west, SC8180X_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(slv_qhs_sdc2, SC8180X_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(slv_qhs_sdc4, SC8180X_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(slv_qhs_security, SC8180X_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(slv_qhs_snoc_cfg, SC8180X_SLAVE_SNOC_CFG, 1, 4, SC8180X_MASTER_SNOC_CFG); -DEFINE_QNODE(slv_qhs_spss_cfg, SC8180X_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_tcsr, SC8180X_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(slv_qhs_tlmm_east, SC8180X_SLAVE_TLMM_EAST, 1, 4); -DEFINE_QNODE(slv_qhs_tlmm_south, SC8180X_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(slv_qhs_tlmm_west, SC8180X_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(slv_qhs_tsif, SC8180X_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(slv_qhs_ufs_card_cfg, SC8180X_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ufs_mem0_cfg, SC8180X_SLAVE_UFS_MEM_0_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_ufs_mem1_cfg, SC8180X_SLAVE_UFS_MEM_1_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_usb3_0, SC8180X_SLAVE_USB3, 1, 4); -DEFINE_QNODE(slv_qhs_usb3_1, SC8180X_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(slv_qhs_usb3_2, SC8180X_SLAVE_USB3_2, 1, 4); -DEFINE_QNODE(slv_qhs_venus_cfg, SC8180X_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_vsense_ctrl_cfg, SC8180X_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(slv_srvc_cnoc, SC8180X_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(slv_qhs_gemnoc, SC8180X_SLAVE_GEM_NOC_CFG, 1, 4, SC8180X_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(slv_qhs_llcc, SC8180X_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(slv_qhs_mdsp_ms_mpu_cfg, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(slv_qns_ecc, SC8180X_SLAVE_ECC, 1, 32); -DEFINE_QNODE(slv_qns_gem_noc_snoc, SC8180X_SLAVE_GEM_NOC_SNOC, 1, 8, SC8180X_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(slv_qns_llcc, SC8180X_SLAVE_LLCC, 8, 16, SC8180X_MASTER_LLCC); -DEFINE_QNODE(slv_srvc_gemnoc, SC8180X_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(slv_srvc_gemnoc1, SC8180X_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(slv_ipa_core_slave, SC8180X_SLAVE_IPA_CORE, 1, 8); -DEFINE_QNODE(slv_ebi, SC8180X_SLAVE_EBI_CH0, 8, 4); -DEFINE_QNODE(slv_qns2_mem_noc, SC8180X_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC8180X_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(slv_qns_mem_noc_hf, SC8180X_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SC8180X_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(slv_srvc_mnoc, SC8180X_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(slv_qhs_apss, SC8180X_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(slv_qns_cnoc, SC8180X_SNOC_CNOC_SLV, 1, 8, SC8180X_SNOC_CNOC_MAS); -DEFINE_QNODE(slv_qns_gemnoc_gc, SC8180X_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC8180X_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(slv_qns_gemnoc_sf, SC8180X_SLAVE_SNOC_GEM_NOC_SF, 1, 32, SC8180X_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(slv_qxs_imem, SC8180X_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(slv_qxs_pimem, SC8180X_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(slv_srvc_snoc, SC8180X_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(slv_xs_pcie_0, SC8180X_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(slv_xs_pcie_1, SC8180X_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(slv_xs_pcie_2, SC8180X_SLAVE_PCIE_2, 1, 8); -DEFINE_QNODE(slv_xs_pcie_3, SC8180X_SLAVE_PCIE_3, 1, 8); -DEFINE_QNODE(slv_xs_qdss_stm, SC8180X_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(slv_xs_sys_tcu_cfg, SC8180X_SLAVE_TCU, 1, 8); -DEFINE_QNODE(slv_qup_core_0, SC8180X_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(slv_qup_core_1, SC8180X_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(slv_qup_core_2, SC8180X_SLAVE_QUP_CORE_2, 1, 4); - -DEFINE_QBCM(bcm_acv, "ACV", false, &slv_ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &slv_ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &slv_qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &slv_qns_mem_noc_hf); -DEFINE_QBCM(bcm_co0, "CO0", false, &slv_qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &mas_qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qhs_ahb2phy_refgen_center, &slv_qhs_ahb2phy_refgen_east, &slv_qhs_ahb2phy_refgen_west, &slv_qhs_ahb2phy_south, &slv_qhs_aop, &slv_qhs_aoss, &slv_qhs_camera_cfg, &slv_qhs_clk_ctl, &slv_qhs_compute_dsp, &slv_qhs_cpr_cx, &slv_qhs_cpr_mmcx, &slv_qhs_cpr_mx, &slv_qhs_crypto0_cfg, &slv_qhs_ddrss_cfg, &slv_qhs_display_cfg, &slv_qhs_emac_cfg, &slv_qhs_glm, &slv_qhs_gpuss_cfg, &slv_qhs_imem_cfg, &slv_qhs_ipa, &slv_qhs_mnoc_cfg, &slv_qhs_npu_cfg, &slv_qhs_pcie0_cfg, &slv_qhs_pcie1_cfg, &slv_qhs_pcie2_cfg, &slv_qhs_pcie3_cfg, &slv_qhs_pdm, &slv_qhs_pimem_cfg, &slv_qhs_prng, &slv_qhs_qdss_cfg, &slv_qhs_qspi_0, &slv_qhs_qspi_1, &slv_qhs_qupv3_east0, &slv_qhs_qupv3_east1, &slv_qhs_qupv3_west, &slv_qhs_sdc2, &slv_qhs_sdc4, &slv_qhs_security, &slv_qhs_snoc_cfg, &slv_qhs_spss_cfg, &slv_qhs_tcsr, &slv_qhs_tlmm_east, &slv_qhs_tlmm_south, &slv_qhs_tlmm_west, &slv_qhs_tsif, &slv_qhs_ufs_card_cfg, &slv_qhs_ufs_mem0_cfg, &slv_qhs_ufs_mem1_cfg, &slv_qhs_usb3_0, &slv_qhs_usb3_1, &slv_qhs_usb3_2, &slv_qhs_venus_cfg, &slv_qhs_vsense_ctrl_cfg, &slv_srvc_cnoc); -DEFINE_QBCM(bcm_mm1, "MM1", false, &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, &mas_qxm_camnoc_sf_uncomp, &mas_qxm_camnoc_hf0, &mas_qxm_camnoc_hf1, &mas_qxm_mdp0, &mas_qxm_mdp1); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qup_core_0, &mas_qup_core_1, &mas_qup_core_2); -DEFINE_QBCM(bcm_sh2, "SH2", false, &slv_qns_gem_noc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &mas_qxm_camnoc_sf, &mas_qxm_rot, &mas_qxm_venus0, &mas_qxm_venus1, &mas_qxm_venus_arm9, &slv_qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", true, &mas_acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", false, &slv_qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn1, "SN1", false, &slv_qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", true, &slv_qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &mas_qnm_npu); -DEFINE_QBCM(bcm_ip0, "IP0", false, &slv_ipa_core_slave); -DEFINE_QBCM(bcm_sn3, "SN3", true, &slv_srvc_aggre1_noc, &slv_qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &slv_qxs_pimem); -DEFINE_QBCM(bcm_sn8, "SN8", false, &slv_xs_pcie_0, &slv_xs_pcie_1, &slv_xs_pcie_2, &slv_xs_pcie_3); -DEFINE_QBCM(bcm_sn9, "SN9", false, &mas_qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &mas_qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn14, "SN14", false, &slv_qns_pcie_mem_noc); -DEFINE_QBCM(bcm_sn15, "SN15", true, &mas_qnm_gemnoc); +static struct qcom_icc_node mas_qhm_a1noc_cfg = { + .name = "mas_qhm_a1noc_cfg", + .id = SC8180X_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_A1NOC } +}; + +static struct qcom_icc_node mas_xm_ufs_card = { + .name = "mas_xm_ufs_card", + .id = SC8180X_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_ufs_g4 = { + .name = "mas_xm_ufs_g4", + .id = SC8180X_MASTER_UFS_GEN4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_ufs_mem = { + .name = "mas_xm_ufs_mem", + .id = SC8180X_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_usb3_0 = { + .name = "mas_xm_usb3_0", + .id = SC8180X_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_usb3_1 = { + .name = "mas_xm_usb3_1", + .id = SC8180X_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_usb3_2 = { + .name = "mas_xm_usb3_2", + .id = SC8180X_MASTER_USB3_2, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_a2noc_cfg = { + .name = "mas_qhm_a2noc_cfg", + .id = SC8180X_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_A2NOC } +}; + +static struct qcom_icc_node mas_qhm_qdss_bam = { + .name = "mas_qhm_qdss_bam", + .id = SC8180X_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qspi = { + .name = "mas_qhm_qspi", + .id = SC8180X_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qspi1 = { + .name = "mas_qhm_qspi1", + .id = SC8180X_MASTER_QSPI_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qup0 = { + .name = "mas_qhm_qup0", + .id = SC8180X_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qup1 = { + .name = "mas_qhm_qup1", + .id = SC8180X_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_qup2 = { + .name = "mas_qhm_qup2", + .id = SC8180X_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qhm_sensorss_ahb = { + .name = "mas_qhm_sensorss_ahb", + .id = SC8180X_MASTER_SENSORS_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qxm_crypto = { + .name = "mas_qxm_crypto", + .id = SC8180X_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qxm_ipa = { + .name = "mas_qxm_ipa", + .id = SC8180X_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_emac = { + .name = "mas_xm_emac", + .id = SC8180X_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_pcie3_0 = { + .name = "mas_xm_pcie3_0", + .id = SC8180X_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_pcie3_1 = { + .name = "mas_xm_pcie3_1", + .id = SC8180X_MASTER_PCIE_1, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_pcie3_2 = { + .name = "mas_xm_pcie3_2", + .id = SC8180X_MASTER_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_pcie3_3 = { + .name = "mas_xm_pcie3_3", + .id = SC8180X_MASTER_PCIE_3, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_SLAVE_ANOC_PCIE_GEM_NOC } +}; + +static struct qcom_icc_node mas_xm_qdss_etr = { + .name = "mas_xm_qdss_etr", + .id = SC8180X_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_sdc2 = { + .name = "mas_xm_sdc2", + .id = SC8180X_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_xm_sdc4 = { + .name = "mas_xm_sdc4", + .id = SC8180X_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_SLV } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = { + .name = "mas_qxm_camnoc_hf0_uncomp", + .id = SC8180X_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = { + .name = "mas_qxm_camnoc_hf1_uncomp", + .id = SC8180X_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } +}; + +static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = { + .name = "mas_qxm_camnoc_sf_uncomp", + .id = SC8180X_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CAMNOC_UNCOMP } +}; + +static struct qcom_icc_node mas_qnm_npu = { + .name = "mas_qnm_npu", + .id = SC8180X_MASTER_NPU, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_CDSP_MEM_NOC } +}; + +static struct qcom_icc_node mas_qnm_snoc = { + .name = "mas_qnm_snoc", + .id = SC8180X_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 56, + .links = { SC8180X_SLAVE_TLMM_SOUTH, + SC8180X_SLAVE_CDSP_CFG, + SC8180X_SLAVE_SPSS_CFG, + SC8180X_SLAVE_CAMERA_CFG, + SC8180X_SLAVE_SDCC_4, + SC8180X_SLAVE_AHB2PHY_CENTER, + SC8180X_SLAVE_SDCC_2, + SC8180X_SLAVE_PCIE_2_CFG, + SC8180X_SLAVE_CNOC_MNOC_CFG, + SC8180X_SLAVE_EMAC_CFG, + SC8180X_SLAVE_QSPI_0, + SC8180X_SLAVE_QSPI_1, + SC8180X_SLAVE_TLMM_EAST, + SC8180X_SLAVE_SNOC_CFG, + SC8180X_SLAVE_AHB2PHY_EAST, + SC8180X_SLAVE_GLM, + SC8180X_SLAVE_PDM, + SC8180X_SLAVE_PCIE_1_CFG, + SC8180X_SLAVE_A2NOC_CFG, + SC8180X_SLAVE_QDSS_CFG, + SC8180X_SLAVE_DISPLAY_CFG, + SC8180X_SLAVE_TCSR, + SC8180X_SLAVE_UFS_MEM_0_CFG, + SC8180X_SLAVE_CNOC_DDRSS, + SC8180X_SLAVE_PCIE_0_CFG, + SC8180X_SLAVE_QUP_1, + SC8180X_SLAVE_QUP_2, + SC8180X_SLAVE_NPU_CFG, + SC8180X_SLAVE_CRYPTO_0_CFG, + SC8180X_SLAVE_GRAPHICS_3D_CFG, + SC8180X_SLAVE_VENUS_CFG, + SC8180X_SLAVE_TSIF, + SC8180X_SLAVE_IPA_CFG, + SC8180X_SLAVE_CLK_CTL, + SC8180X_SLAVE_SECURITY, + SC8180X_SLAVE_AOP, + SC8180X_SLAVE_AHB2PHY_WEST, + SC8180X_SLAVE_AHB2PHY_SOUTH, + SC8180X_SLAVE_SERVICE_CNOC, + SC8180X_SLAVE_UFS_CARD_CFG, + SC8180X_SLAVE_USB3_1, + SC8180X_SLAVE_USB3_2, + SC8180X_SLAVE_PCIE_3_CFG, + SC8180X_SLAVE_RBCPR_CX_CFG, + SC8180X_SLAVE_TLMM_WEST, + SC8180X_SLAVE_A1NOC_CFG, + SC8180X_SLAVE_AOSS, + SC8180X_SLAVE_PRNG, + SC8180X_SLAVE_VSENSE_CTRL_CFG, + SC8180X_SLAVE_QUP_0, + SC8180X_SLAVE_USB3, + SC8180X_SLAVE_RBCPR_MMCX_CFG, + SC8180X_SLAVE_PIMEM_CFG, + SC8180X_SLAVE_UFS_MEM_1_CFG, + SC8180X_SLAVE_RBCPR_MX_CFG, + SC8180X_SLAVE_IMEM_CFG } +}; + +static struct qcom_icc_node mas_qhm_cnoc_dc_noc = { + .name = "mas_qhm_cnoc_dc_noc", + .id = SC8180X_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC_CFG, + SC8180X_SLAVE_GEM_NOC_CFG } +}; + +static struct qcom_icc_node mas_acm_apps = { + .name = "mas_acm_apps", + .id = SC8180X_MASTER_AMPSS_M0, + .channels = 4, + .buswidth = 64, + .num_links = 3, + .links = { SC8180X_SLAVE_ECC, + SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_acm_gpu_tcu = { + .name = "mas_acm_gpu_tcu", + .id = SC8180X_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_acm_sys_tcu = { + .name = "mas_acm_sys_tcu", + .id = SC8180X_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qhm_gemnoc_cfg = { + .name = "mas_qhm_gemnoc_cfg", + .id = SC8180X_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SC8180X_SLAVE_SERVICE_GEM_NOC_1, + SC8180X_SLAVE_SERVICE_GEM_NOC, + SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG } +}; + +static struct qcom_icc_node mas_qnm_cmpnoc = { + .name = "mas_qnm_cmpnoc", + .id = SC8180X_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SC8180X_SLAVE_ECC, + SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_gpu = { + .name = "mas_qnm_gpu", + .id = SC8180X_MASTER_GRAPHICS_3D, + .channels = 4, + .buswidth = 32, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_mnoc_hf = { + .name = "mas_qnm_mnoc_hf", + .id = SC8180X_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_qnm_mnoc_sf = { + .name = "mas_qnm_mnoc_sf", + .id = SC8180X_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_pcie = { + .name = "mas_qnm_pcie", + .id = SC8180X_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC8180X_SLAVE_LLCC, + SC8180X_SLAVE_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node mas_qnm_snoc_gc = { + .name = "mas_qnm_snoc_gc", + .id = SC8180X_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_qnm_snoc_sf = { + .name = "mas_qnm_snoc_sf", + .id = SC8180X_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_qxm_ecc = { + .name = "mas_qxm_ecc", + .id = SC8180X_MASTER_ECC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_LLCC } +}; + +static struct qcom_icc_node mas_ipa_core_master = { + .name = "mas_ipa_core_master", + .id = SC8180X_MASTER_IPA_CORE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_IPA_CORE } +}; + +static struct qcom_icc_node mas_llcc_mc = { + .name = "mas_llcc_mc", + .id = SC8180X_MASTER_LLCC, + .channels = 8, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_EBI_CH0 } +}; + +static struct qcom_icc_node mas_qhm_mnoc_cfg = { + .name = "mas_qhm_mnoc_cfg", + .id = SC8180X_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_MNOC } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf0 = { + .name = "mas_qxm_camnoc_hf0", + .id = SC8180X_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_camnoc_hf1 = { + .name = "mas_qxm_camnoc_hf1", + .id = SC8180X_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_camnoc_sf = { + .name = "mas_qxm_camnoc_sf", + .id = SC8180X_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_mdp0 = { + .name = "mas_qxm_mdp0", + .id = SC8180X_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_mdp1 = { + .name = "mas_qxm_mdp1", + .id = SC8180X_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_rot = { + .name = "mas_qxm_rot", + .id = SC8180X_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_venus0 = { + .name = "mas_qxm_venus0", + .id = SC8180X_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_venus1 = { + .name = "mas_qxm_venus1", + .id = SC8180X_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qxm_venus_arm9 = { + .name = "mas_qxm_venus_arm9", + .id = SC8180X_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SLAVE_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node mas_qhm_snoc_cfg = { + .name = "mas_qhm_snoc_cfg", + .id = SC8180X_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_SERVICE_SNOC } +}; + +static struct qcom_icc_node mas_qnm_aggre1_noc = { + .name = "mas_qnm_aggre1_noc", + .id = SC8180X_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 32, + .num_links = 6, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, + SC8180X_SLAVE_PIMEM, + SC8180X_SLAVE_OCIMEM, + SC8180X_SLAVE_APPSS, + SC8180X_SNOC_CNOC_SLV, + SC8180X_SLAVE_QDSS_STM } +}; + +static struct qcom_icc_node mas_qnm_aggre2_noc = { + .name = "mas_qnm_aggre2_noc", + .id = SC8180X_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 11, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_SF, + SC8180X_SLAVE_PIMEM, + SC8180X_SLAVE_PCIE_3, + SC8180X_SLAVE_OCIMEM, + SC8180X_SLAVE_APPSS, + SC8180X_SLAVE_PCIE_2, + SC8180X_SNOC_CNOC_SLV, + SC8180X_SLAVE_PCIE_0, + SC8180X_SLAVE_PCIE_1, + SC8180X_SLAVE_TCU, + SC8180X_SLAVE_QDSS_STM } +}; + +static struct qcom_icc_node mas_qnm_gemnoc = { + .name = "mas_qnm_gemnoc", + .id = SC8180X_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SC8180X_SLAVE_PIMEM, + SC8180X_SLAVE_OCIMEM, + SC8180X_SLAVE_APPSS, + SC8180X_SNOC_CNOC_SLV, + SC8180X_SLAVE_TCU, + SC8180X_SLAVE_QDSS_STM } +}; + +static struct qcom_icc_node mas_qxm_pimem = { + .name = "mas_qxm_pimem", + .id = SC8180X_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, + SC8180X_SLAVE_OCIMEM } +}; + +static struct qcom_icc_node mas_xm_gic = { + .name = "mas_xm_gic", + .id = SC8180X_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC8180X_SLAVE_SNOC_GEM_NOC_GC, + SC8180X_SLAVE_OCIMEM } +}; + +static struct qcom_icc_node mas_qup_core_0 = { + .name = "mas_qup_core_0", + .id = SC8180X_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_QUP_CORE_0 } +}; + +static struct qcom_icc_node mas_qup_core_1 = { + .name = "mas_qup_core_1", + .id = SC8180X_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_QUP_CORE_1 } +}; + +static struct qcom_icc_node mas_qup_core_2 = { + .name = "mas_qup_core_2", + .id = SC8180X_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_SLAVE_QUP_CORE_2 } +}; + +static struct qcom_icc_node slv_qns_a1noc_snoc = { + .name = "slv_qns_a1noc_snoc", + .id = SC8180X_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_A1NOC_SNOC_MAS } +}; + +static struct qcom_icc_node slv_srvc_aggre1_noc = { + .name = "slv_srvc_aggre1_noc", + .id = SC8180X_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns_a2noc_snoc = { + .name = "slv_qns_a2noc_snoc", + .id = SC8180X_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_A2NOC_SNOC_MAS } +}; + +static struct qcom_icc_node slv_qns_pcie_mem_noc = { + .name = "slv_qns_pcie_mem_noc", + .id = SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_GEM_NOC_PCIE_SNOC } +}; + +static struct qcom_icc_node slv_srvc_aggre2_noc = { + .name = "slv_srvc_aggre2_noc", + .id = SC8180X_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns_camnoc_uncomp = { + .name = "slv_qns_camnoc_uncomp", + .id = SC8180X_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32 +}; + +static struct qcom_icc_node slv_qns_cdsp_mem_noc = { + .name = "slv_qns_cdsp_mem_noc", + .id = SC8180X_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_COMPUTE_NOC } +}; + +static struct qcom_icc_node slv_qhs_a1_noc_cfg = { + .name = "slv_qhs_a1_noc_cfg", + .id = SC8180X_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_A1NOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_a2_noc_cfg = { + .name = "slv_qhs_a2_noc_cfg", + .id = SC8180X_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_A2NOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = { + .name = "slv_qhs_ahb2phy_refgen_center", + .id = SC8180X_SLAVE_AHB2PHY_CENTER, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = { + .name = "slv_qhs_ahb2phy_refgen_east", + .id = SC8180X_SLAVE_AHB2PHY_EAST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = { + .name = "slv_qhs_ahb2phy_refgen_west", + .id = SC8180X_SLAVE_AHB2PHY_WEST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ahb2phy_south = { + .name = "slv_qhs_ahb2phy_south", + .id = SC8180X_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_aop = { + .name = "slv_qhs_aop", + .id = SC8180X_SLAVE_AOP, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_aoss = { + .name = "slv_qhs_aoss", + .id = SC8180X_SLAVE_AOSS, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_camera_cfg = { + .name = "slv_qhs_camera_cfg", + .id = SC8180X_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_clk_ctl = { + .name = "slv_qhs_clk_ctl", + .id = SC8180X_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_compute_dsp = { + .name = "slv_qhs_compute_dsp", + .id = SC8180X_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_cpr_cx = { + .name = "slv_qhs_cpr_cx", + .id = SC8180X_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_cpr_mmcx = { + .name = "slv_qhs_cpr_mmcx", + .id = SC8180X_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_cpr_mx = { + .name = "slv_qhs_cpr_mx", + .id = SC8180X_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_crypto0_cfg = { + .name = "slv_qhs_crypto0_cfg", + .id = SC8180X_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ddrss_cfg = { + .name = "slv_qhs_ddrss_cfg", + .id = SC8180X_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_CNOC_DC_NOC } +}; + +static struct qcom_icc_node slv_qhs_display_cfg = { + .name = "slv_qhs_display_cfg", + .id = SC8180X_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_emac_cfg = { + .name = "slv_qhs_emac_cfg", + .id = SC8180X_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_glm = { + .name = "slv_qhs_glm", + .id = SC8180X_SLAVE_GLM, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_gpuss_cfg = { + .name = "slv_qhs_gpuss_cfg", + .id = SC8180X_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qhs_imem_cfg = { + .name = "slv_qhs_imem_cfg", + .id = SC8180X_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ipa = { + .name = "slv_qhs_ipa", + .id = SC8180X_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_mnoc_cfg = { + .name = "slv_qhs_mnoc_cfg", + .id = SC8180X_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_CNOC_MNOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_npu_cfg = { + .name = "slv_qhs_npu_cfg", + .id = SC8180X_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie0_cfg = { + .name = "slv_qhs_pcie0_cfg", + .id = SC8180X_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie1_cfg = { + .name = "slv_qhs_pcie1_cfg", + .id = SC8180X_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie2_cfg = { + .name = "slv_qhs_pcie2_cfg", + .id = SC8180X_SLAVE_PCIE_2_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pcie3_cfg = { + .name = "slv_qhs_pcie3_cfg", + .id = SC8180X_SLAVE_PCIE_3_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pdm = { + .name = "slv_qhs_pdm", + .id = SC8180X_SLAVE_PDM, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_pimem_cfg = { + .name = "slv_qhs_pimem_cfg", + .id = SC8180X_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_prng = { + .name = "slv_qhs_prng", + .id = SC8180X_SLAVE_PRNG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qdss_cfg = { + .name = "slv_qhs_qdss_cfg", + .id = SC8180X_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qspi_0 = { + .name = "slv_qhs_qspi_0", + .id = SC8180X_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qspi_1 = { + .name = "slv_qhs_qspi_1", + .id = SC8180X_SLAVE_QSPI_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qupv3_east0 = { + .name = "slv_qhs_qupv3_east0", + .id = SC8180X_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qupv3_east1 = { + .name = "slv_qhs_qupv3_east1", + .id = SC8180X_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_qupv3_west = { + .name = "slv_qhs_qupv3_west", + .id = SC8180X_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_sdc2 = { + .name = "slv_qhs_sdc2", + .id = SC8180X_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_sdc4 = { + .name = "slv_qhs_sdc4", + .id = SC8180X_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_security = { + .name = "slv_qhs_security", + .id = SC8180X_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_snoc_cfg = { + .name = "slv_qhs_snoc_cfg", + .id = SC8180X_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_SNOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_spss_cfg = { + .name = "slv_qhs_spss_cfg", + .id = SC8180X_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tcsr = { + .name = "slv_qhs_tcsr", + .id = SC8180X_SLAVE_TCSR, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tlmm_east = { + .name = "slv_qhs_tlmm_east", + .id = SC8180X_SLAVE_TLMM_EAST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tlmm_south = { + .name = "slv_qhs_tlmm_south", + .id = SC8180X_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tlmm_west = { + .name = "slv_qhs_tlmm_west", + .id = SC8180X_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_tsif = { + .name = "slv_qhs_tsif", + .id = SC8180X_SLAVE_TSIF, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ufs_card_cfg = { + .name = "slv_qhs_ufs_card_cfg", + .id = SC8180X_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = { + .name = "slv_qhs_ufs_mem0_cfg", + .id = SC8180X_SLAVE_UFS_MEM_0_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = { + .name = "slv_qhs_ufs_mem1_cfg", + .id = SC8180X_SLAVE_UFS_MEM_1_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_usb3_0 = { + .name = "slv_qhs_usb3_0", + .id = SC8180X_SLAVE_USB3, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_usb3_1 = { + .name = "slv_qhs_usb3_1", + .id = SC8180X_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_usb3_2 = { + .name = "slv_qhs_usb3_2", + .id = SC8180X_SLAVE_USB3_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_venus_cfg = { + .name = "slv_qhs_venus_cfg", + .id = SC8180X_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = { + .name = "slv_qhs_vsense_ctrl_cfg", + .id = SC8180X_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_srvc_cnoc = { + .name = "slv_srvc_cnoc", + .id = SC8180X_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_gemnoc = { + .name = "slv_qhs_gemnoc", + .id = SC8180X_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC8180X_MASTER_GEM_NOC_CFG } +}; + +static struct qcom_icc_node slv_qhs_llcc = { + .name = "slv_qhs_llcc", + .id = SC8180X_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = { + .name = "slv_qhs_mdsp_ms_mpu_cfg", + .id = SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns_ecc = { + .name = "slv_qns_ecc", + .id = SC8180X_SLAVE_ECC, + .channels = 1, + .buswidth = 32 +}; + +static struct qcom_icc_node slv_qns_gem_noc_snoc = { + .name = "slv_qns_gem_noc_snoc", + .id = SC8180X_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_MASTER_GEM_NOC_SNOC } +}; + +static struct qcom_icc_node slv_qns_llcc = { + .name = "slv_qns_llcc", + .id = SC8180X_SLAVE_LLCC, + .channels = 8, + .buswidth = 16, + .num_links = 1, + .links = { SC8180X_MASTER_LLCC } +}; + +static struct qcom_icc_node slv_srvc_gemnoc = { + .name = "slv_srvc_gemnoc", + .id = SC8180X_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_srvc_gemnoc1 = { + .name = "slv_srvc_gemnoc1", + .id = SC8180X_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_ipa_core_slave = { + .name = "slv_ipa_core_slave", + .id = SC8180X_SLAVE_IPA_CORE, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_ebi = { + .name = "slv_ebi", + .id = SC8180X_SLAVE_EBI_CH0, + .channels = 8, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qns2_mem_noc = { + .name = "slv_qns2_mem_noc", + .id = SC8180X_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_MNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node slv_qns_mem_noc_hf = { + .name = "slv_qns_mem_noc_hf", + .id = SC8180X_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_MNOC_HF_MEM_NOC } +}; + +static struct qcom_icc_node slv_srvc_mnoc = { + .name = "slv_srvc_mnoc", + .id = SC8180X_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qhs_apss = { + .name = "slv_qhs_apss", + .id = SC8180X_SLAVE_APPSS, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qns_cnoc = { + .name = "slv_qns_cnoc", + .id = SC8180X_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_SNOC_CNOC_MAS } +}; + +static struct qcom_icc_node slv_qns_gemnoc_gc = { + .name = "slv_qns_gemnoc_gc", + .id = SC8180X_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC8180X_MASTER_SNOC_GC_MEM_NOC } +}; + +static struct qcom_icc_node slv_qns_gemnoc_sf = { + .name = "slv_qns_gemnoc_sf", + .id = SC8180X_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC8180X_MASTER_SNOC_SF_MEM_NOC } +}; + +static struct qcom_icc_node slv_qxs_imem = { + .name = "slv_qxs_imem", + .id = SC8180X_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qxs_pimem = { + .name = "slv_qxs_pimem", + .id = SC8180X_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_srvc_snoc = { + .name = "slv_srvc_snoc", + .id = SC8180X_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_xs_pcie_0 = { + .name = "slv_xs_pcie_0", + .id = SC8180X_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_pcie_1 = { + .name = "slv_xs_pcie_1", + .id = SC8180X_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_pcie_2 = { + .name = "slv_xs_pcie_2", + .id = SC8180X_SLAVE_PCIE_2, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_pcie_3 = { + .name = "slv_xs_pcie_3", + .id = SC8180X_SLAVE_PCIE_3, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_xs_qdss_stm = { + .name = "slv_xs_qdss_stm", + .id = SC8180X_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_xs_sys_tcu_cfg = { + .name = "slv_xs_sys_tcu_cfg", + .id = SC8180X_SLAVE_TCU, + .channels = 1, + .buswidth = 8 +}; + +static struct qcom_icc_node slv_qup_core_0 = { + .name = "slv_qup_core_0", + .id = SC8180X_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qup_core_1 = { + .name = "slv_qup_core_1", + .id = SC8180X_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_node slv_qup_core_2 = { + .name = "slv_qup_core_2", + .id = SC8180X_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4 +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &slv_ebi } +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &slv_ebi } +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &slv_qns_llcc } +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .num_nodes = 1, + .nodes = { &slv_qns_mem_noc_hf } +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .num_nodes = 1, + .nodes = { &slv_qns_cdsp_mem_noc } +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 1, + .nodes = { &mas_qxm_crypto } +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 57, + .nodes = { &mas_qnm_snoc, + &slv_qhs_a1_noc_cfg, + &slv_qhs_a2_noc_cfg, + &slv_qhs_ahb2phy_refgen_center, + &slv_qhs_ahb2phy_refgen_east, + &slv_qhs_ahb2phy_refgen_west, + &slv_qhs_ahb2phy_south, + &slv_qhs_aop, + &slv_qhs_aoss, + &slv_qhs_camera_cfg, + &slv_qhs_clk_ctl, + &slv_qhs_compute_dsp, + &slv_qhs_cpr_cx, + &slv_qhs_cpr_mmcx, + &slv_qhs_cpr_mx, + &slv_qhs_crypto0_cfg, + &slv_qhs_ddrss_cfg, + &slv_qhs_display_cfg, + &slv_qhs_emac_cfg, + &slv_qhs_glm, + &slv_qhs_gpuss_cfg, + &slv_qhs_imem_cfg, + &slv_qhs_ipa, + &slv_qhs_mnoc_cfg, + &slv_qhs_npu_cfg, + &slv_qhs_pcie0_cfg, + &slv_qhs_pcie1_cfg, + &slv_qhs_pcie2_cfg, + &slv_qhs_pcie3_cfg, + &slv_qhs_pdm, + &slv_qhs_pimem_cfg, + &slv_qhs_prng, + &slv_qhs_qdss_cfg, + &slv_qhs_qspi_0, + &slv_qhs_qspi_1, + &slv_qhs_qupv3_east0, + &slv_qhs_qupv3_east1, + &slv_qhs_qupv3_west, + &slv_qhs_sdc2, + &slv_qhs_sdc4, + &slv_qhs_security, + &slv_qhs_snoc_cfg, + &slv_qhs_spss_cfg, + &slv_qhs_tcsr, + &slv_qhs_tlmm_east, + &slv_qhs_tlmm_south, + &slv_qhs_tlmm_west, + &slv_qhs_tsif, + &slv_qhs_ufs_card_cfg, + &slv_qhs_ufs_mem0_cfg, + &slv_qhs_ufs_mem1_cfg, + &slv_qhs_usb3_0, + &slv_qhs_usb3_1, + &slv_qhs_usb3_2, + &slv_qhs_venus_cfg, + &slv_qhs_vsense_ctrl_cfg, + &slv_srvc_cnoc } +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .num_nodes = 7, + .nodes = { &mas_qxm_camnoc_hf0_uncomp, + &mas_qxm_camnoc_hf1_uncomp, + &mas_qxm_camnoc_sf_uncomp, + &mas_qxm_camnoc_hf0, + &mas_qxm_camnoc_hf1, + &mas_qxm_mdp0, + &mas_qxm_mdp1 } +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .num_nodes = 3, + .nodes = { &mas_qup_core_0, + &mas_qup_core_1, + &mas_qup_core_2 } +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .num_nodes = 1, + .nodes = { &slv_qns_gem_noc_snoc } +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .num_nodes = 6, + .nodes = { &mas_qxm_camnoc_sf, + &mas_qxm_rot, + &mas_qxm_venus0, + &mas_qxm_venus1, + &mas_qxm_venus_arm9, + &slv_qns2_mem_noc } +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = true, + .num_nodes = 1, + .nodes = { &mas_acm_apps } +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .nodes = { &slv_qns_gemnoc_sf } +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .nodes = { &slv_qxs_imem } +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = true, + .nodes = { &slv_qns_gemnoc_gc } +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .nodes = { &mas_qnm_npu } +}; + +static struct qcom_icc_bcm bcm_ip0 = { + .name = "IP0", + .nodes = { &slv_ipa_core_slave } +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = true, + .nodes = { &slv_srvc_aggre1_noc, + &slv_qns_cnoc } +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .nodes = { &slv_qxs_pimem } +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .num_nodes = 4, + .nodes = { &slv_xs_pcie_0, + &slv_xs_pcie_1, + &slv_xs_pcie_2, + &slv_xs_pcie_3 } +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .num_nodes = 1, + .nodes = { &mas_qnm_aggre1_noc } +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .num_nodes = 1, + .nodes = { &mas_qnm_aggre2_noc } +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .num_nodes = 1, + .nodes = { &slv_qns_pcie_mem_noc } +}; + +static struct qcom_icc_bcm bcm_sn15 = { + .name = "SN15", + .keepalive = true, + .num_nodes = 1, + .nodes = { &mas_qnm_gemnoc } +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn3,