From patchwork Wed May 4 12:07:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12837785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28A5BC433F5 for ; Wed, 4 May 2022 12:07:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ADA6010E504; Wed, 4 May 2022 12:07:26 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 09D6A10E504; Wed, 4 May 2022 12:07:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651666045; x=1683202045; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=iaezcSeYVIajnw3eytjqvvlic5Jpbz2ugcO6Nhfv8X0=; b=XpWddH4RPRtGWlSIVdIlNBZWGO32bP2TfjWCuebaBCzHDsuvUh3L6oIA sMXHJINrxacL2Dl74cDWvcn2U/8Pqg/XPhlj8e5Cx5CBgQsz8GbWUc9qD 3Vimkxzv6CeYvxdAibWJYoKUC20vcDpDcUH6SCryuixYJil2f0UDD9P9z A4r09+ld6lyBOcugkK54dTOcFyfhWCjmOAOElD/tkzwa8dwV+vT1eS13A BCc5Uj8+wRwySHcEsFYpDPAqGBe4xM+DxrTGR4Kylj42TOBkHQaoaZhzT j4ZwEsOKJ9tP70gCKG5CzV1zT1DcKiJZaYGUMERmaoN3E5IMjde/cFvcs g==; X-IronPort-AV: E=McAfee;i="6400,9594,10336"; a="267343595" X-IronPort-AV: E=Sophos;i="5.91,198,1647327600"; d="scan'208";a="267343595" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2022 05:07:24 -0700 X-IronPort-AV: E=Sophos;i="5.91,198,1647327600"; d="scan'208";a="693884056" Received: from gidaly-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.236.183]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2022 05:07:22 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 4 May 2022 13:07:14 +0100 Message-Id: <20220504120715.911045-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed to exercise a certain code path, so in case of values coming from MMIO reads we cannot be sure CI will have all the possible SKUs and parts. Use drm_warn instead and move logging to init phase while at it. Signed-off-by: Tvrtko Ursulin Cc: Matt Roper Cc: Jani Nikula Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 53307ca0eed0..c474e5c3ea5e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt) * An mslice is unavailable only if both the meml3 for the slice is * disabled *and* all of the DSS in the slice (quadrant) are disabled. */ - if (HAS_MSLICES(i915)) + if (HAS_MSLICES(i915)) { gt->info.mslice_mask = slicemask(gt, GEN_DSS_PER_MSLICE) | (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & GEN12_MEML3_EN_MASK); + if (!gt->info.mslice_mask) /* should be impossible! */ + drm_warn(&i915->drm, "mslice mask all zero!\n"); + } if (IS_DG2(i915)) { gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt) gt->info.l3bank_mask = ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & GEN10_L3BANK_MASK; + if (!gt->info.l3bank_mask) /* should be impossible! */ + drm_warn(&i915->drm, "L3 bank mask is all zero!\n"); } else if (HAS_MSLICES(i915)) { MISSING_CASE(INTEL_INFO(i915)->platform); } @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt, { switch (type) { case L3BANK: - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */ - *sliceid = 0; /* unused */ *subsliceid = __ffs(gt->info.l3bank_mask); break; case MSLICE: - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */ - *sliceid = __ffs(gt->info.mslice_mask); *subsliceid = 0; /* unused */ break; case LNCF: - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */ - /* * An LNCF is always present if its mslice is present, so we * can safely just steer to LNCF 0 in all cases. From patchwork Wed May 4 12:07:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 12837786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46328C433F5 for ; Wed, 4 May 2022 12:07:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 323F010E74C; Wed, 4 May 2022 12:07:27 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1870C10E504; Wed, 4 May 2022 12:07:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651666046; x=1683202046; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ls4UJiHxXQ/mgV/gf1ness9dRnHLG43SWX6OfTqbmbw=; b=Dc8vCg9w2fOnGO8VGsP89VZm1RvmpViSfVxgLXemJGVqJlwsc32mRuOk 9g33OPXSrSwCJfr6UUQBnQoptdlvI1TBc457xxoLo5m9vXoe+LtC8/dSD 4Ke+VlOUAaMpEnRbWcovY8SBs3AgNBTdE4fPsXALqIifDLy7EXoICvNkq yS4Aq1GV3nfCDokkjlvLfeNB3tBWkBpPePe1YFlRNeY4VtlzwyEGE8GhP qKN2QoRb9IbNFc77pqWXqcb7z5qdDkUvzPxItYRXyV42mm9TMV9QyPt9V 2afJm3eq9vnB7qcHvqVrX1wcarF8txIEU8qZ1tL/tOo2r1gZeO8AWWh/F w==; X-IronPort-AV: E=McAfee;i="6400,9594,10336"; a="267343600" X-IronPort-AV: E=Sophos;i="5.91,198,1647327600"; d="scan'208";a="267343600" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2022 05:07:25 -0700 X-IronPort-AV: E=Sophos;i="5.91,198,1647327600"; d="scan'208";a="693884095" Received: from gidaly-mobl1.ger.corp.intel.com (HELO tursulin-mobl2.home) ([10.213.236.183]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2022 05:07:24 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 4 May 2022 13:07:15 +0100 Message-Id: <20220504120715.911045-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220504120715.911045-1-tvrtko.ursulin@linux.intel.com> References: <20220504120715.911045-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tvrtko Ursulin DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed to exercise a certain code path, so in case of values coming from MMIO reads we cannot be sure CI will have all the possible SKUs and parts, or that it will catch all possible error conditions. Use drm_warn instead. Signed-off-by: Tvrtko Ursulin Cc: Mika Kuoppala Cc: Jani Nikula Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 5423bfd301ad..f8f279a195c0 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -117,7 +117,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine) return; /* ring should be idle before issuing a sync flush*/ - GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); + if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0) + drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n", + engine->name); ENGINE_WRITE_FW(engine, RING_INSTPM, _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |