From patchwork Thu May 5 09:12:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12839256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20845C43219 for ; Thu, 5 May 2022 09:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351713AbiEEJQP (ORCPT ); Thu, 5 May 2022 05:16:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351836AbiEEJQN (ORCPT ); Thu, 5 May 2022 05:16:13 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 658144BFF7 for ; Thu, 5 May 2022 02:12:34 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id w1so6445796lfa.4 for ; Thu, 05 May 2022 02:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pL/05pqvORVzFnLhsNkYW/L7SMLwKtI/1exh83l2l2w=; b=PcJrZNjIBzOY6uCuOZrSTjLjLS0QKWt2UN6H8v8dLSsAjoUjHpsyZ4Qgi1q5VVc4ct HqJEQp+wn92GBb3NND9H1W3wEv3tk46O00EXHur/NVTMpbB5cyj03DNIecz7B0SZRar6 cUULVSRl07B33yQu6LXGPzuBSdyxwp0cg9rKnpCIHL4qcPjVuPngZs4/lahneNOQ1R/p uMi28Jj9StylkS8D22WDVzaFK2BetcFayNOUKDbQSbsYm19EfvX50xU6LawcdMYDnxoP IUbNw6ED/YdN3VoSVhc+A2PQCiPgRsmWC60ygY5eobNFv4n1gJ7MpZWNf7TDAP8x/+tF nPdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pL/05pqvORVzFnLhsNkYW/L7SMLwKtI/1exh83l2l2w=; b=HPdrupaQQjIJMj/dQpNKbD+WV8pL4NeDahinVXUxExf+uHwVgqcJhsnXr+f1aIVyno B33spYDBHX4pBsdfPgKCIEqlmvRdximZRC46VMok0cOSMdxlwwF+jn6REEYGcU+5gb+T f7ixkFIF+sEv33rX+upE5Cx8PmjG7OLtE2Bk/myJaZdqWjGTTF3gAXjLr41B0jJsaVEA HxObMPb4h13jaFRvCBf3bEngft0XAtWKvMoQeJAbaJL40DrAKR1BpshzyqX1awRiqys7 bfJ1EEG2xiiB4MDP9WI570JeK5PFwYgPe3SgeKYg2iIe6ah9SyC/lPhVoRf2pKOG/gi+ RGWg== X-Gm-Message-State: AOAM5332Lvcw1D7kFsmx3Q8/dr5BZ9FXKYLXISNcVvY8zpV83Chi1ZJ8 Jev+cdWVzUY0qGvrOB4P/2dgdQ== X-Google-Smtp-Source: ABdhPJwdzu563dhjl+3cJ2aaAn3xADSLKZwH/Xd4gw0xIPDPGkEWRqD0M4TWktJGH828jf0vOkWEbg== X-Received: by 2002:a05:6512:2622:b0:448:27b9:5299 with SMTP id bt34-20020a056512262200b0044827b95299mr16741190lfb.86.1651741952706; Thu, 05 May 2022 02:12:32 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v26-20020ac2593a000000b0047255d211e8sm133564lfi.279.2022.05.05.02.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 1/7] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Date: Thu, 5 May 2022 12:12:25 +0300 Message-Id: <20220505091231.1308963-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org I have replied with my Tested-by to the patch at [2], which has landed in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints"). However lately I noticed that during the tests I still had 'pcie_pme=nomsi', so the device was not forced to use higher MSI vectors. After removing this option I noticed that hight MSI vectors are not delivered on tested platforms. Additional research pointed to a patch in msm-4.14 ([1]), which describes that each group of MSI vectors is mapped to the separate interrupt. Without these changes specifying num_verctors can lead to missing MSI interrupts and thus to devices malfunction. Fixes: 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints") Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index c940e67d831c..375f27ab9403 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1593,7 +1593,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; pp = &pci->pp; - pp->num_vectors = MAX_MSI_IRQS; pcie->pci = pci; From patchwork Thu May 5 09:12:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12839257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79680C41535 for ; Thu, 5 May 2022 09:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351836AbiEEJQQ (ORCPT ); Thu, 5 May 2022 05:16:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346224AbiEEJQO (ORCPT ); Thu, 5 May 2022 05:16:14 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BE5E4C403 for ; Thu, 5 May 2022 02:12:35 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id w1so6445833lfa.4 for ; Thu, 05 May 2022 02:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WbPm7wPFz42k3w9HjVTRf/Wo4cb2U+ygFCZJLREQuWI=; b=lYJ4qoHTvAqPOqdl117lhEV53qwVUf1MnS7+7HtyGmc35mpqGBLqJnZmf7MiEOIVLh MNcqTgYPNBA8jEK3oGxvCxvLyQferb3nnxTx5TLIdkzCDXsBGmpOCnDhZzVRe9l/dgov +vMolSGp2E9wpVLHHYJpY+m7socXec8ggC/3wUALnhwkwnBGqaFX8e//emXSjdI+nVEd S2WGjs1w80lA7NYJbBPqHQYaXP25FEITR1F9f0xsBM9rYkM7ERe8aQIOjv5714c02O+O bGZkSHSXDzTf+Qd3Cgp5E8rHZHFvynKQP4ANesAjikQyBPfsDMP1UN9qK8RCxCLsf5q1 SNjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WbPm7wPFz42k3w9HjVTRf/Wo4cb2U+ygFCZJLREQuWI=; b=U9laaG4ahZugsFyN/z+0aKv/0pBKDfIb+uqOZX/doW8udaUeJXc/LZxjoTI4zSbwyD 3K+dY+VTZW/OOAlZKA/2JYc82wpq1jTOvbgzeRBw8E8UwsFmzz0q7PE9/0I75xGwhYqQ tFlB/J/C9FcKpqOwtyxGzE3qQXBj7yGpRFCxxaLjwLRtxsi2IOwODEnQCmTGGjoCpOmm +mzUnGOEtDvuPonWDu0hERRala4Q3gqat/d5P1WUdeRZoBircvEMnMhEM+dLbC4cCfP/ uCbyLTOBDsUm6lSt1M5yoND4xt7PH9q9GUF32vbbVX04u0bLm8DBVsYUR9sj9QtOPoQC xRLw== X-Gm-Message-State: AOAM531YOqxmTLryYoYEA06ptbqTPMn+5FvrGveyPV2SIvIYkrlb76Vy HjTo5KpEpijuTWMgnXvjZCy24w== X-Google-Smtp-Source: ABdhPJxDCxyeY3ldnLiGjJq7eNDoD+Gcj981AvOQx96OACeIr0VRCatY4RW3MqiFDGcvre7SrrUQOw== X-Received: by 2002:a05:6512:ace:b0:473:ba5b:8e06 with SMTP id n14-20020a0565120ace00b00473ba5b8e06mr5227621lfu.614.1651741953418; Thu, 05 May 2022 02:12:33 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v26-20020ac2593a000000b0047255d211e8sm133564lfi.279.2022.05.05.02.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:33 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 2/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Date: Thu, 5 May 2022 12:12:26 +0300 Message-Id: <20220505091231.1308963-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The subdrivers pass -ESOMETHING if they do not want the core to touch MSI IRQ. dw_pcie_host_init() also checks if (msi_irq > 0) rather than just if (msi_irq). So let's make dw_pcie_free_msi() also check that msi_irq is greater than zero. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f32d964..43d1d6116007 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,7 +257,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq) + if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); irq_domain_remove(pp->msi_domain); From patchwork Thu May 5 09:12:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12839258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1006FC46467 for ; Thu, 5 May 2022 09:12:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346070AbiEEJQR (ORCPT ); Thu, 5 May 2022 05:16:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351872AbiEEJQP (ORCPT ); Thu, 5 May 2022 05:16:15 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF4FF4BFCB for ; Thu, 5 May 2022 02:12:35 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id x17so6422358lfa.10 for ; Thu, 05 May 2022 02:12:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5fpTEUNCvgnc9AMwKVJD3wLMKlj8TQ48QZUL6p2NQR8=; b=aStDZhXoHaHsQskhisuS1in5V+S+1Pj9TNHgy7QB15Nv1NP4wYjoH/jzUj1HTe7ct4 oDPa/+uQ8lgfr4Fh8S8osXYUoTNmzrtiEVk+Jp0zhSGKAWD2nshHGj/pvriF/GQ+H+eL ILX8FA25Ma255iCSD5fVuuYOm20qmV2afmEeLwFruSxNpP0ZM+4+NWpBYpYbca1B8dZM 4dljL+fe2dXhyc5UliaS6HhQK7DWTDFhMyEH+FCwgVwDhYDCqoNQhRPB5oqSqkVJdHqd XOZmf5ZXqVU/ECUipJPbtcAQPfM0C4WYYLshblAnXQMeijq+v0yynSRs8fSbuaZs7/ak sh1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5fpTEUNCvgnc9AMwKVJD3wLMKlj8TQ48QZUL6p2NQR8=; b=iyeCXIdkIcoohkr0mJPPm/T4XR6BiDPeWbztKA/uC5HjJLCSVr+uZo56HZSAzhIwjX Pv4DEhgOV6dU9v8LmlHFMo35KJLTwg/52G6YR7VSAqfAbcO7BgoETCbYagFmgTFb/pNu +DI2PADwtUF4366u1PMUXo+liBe5hNPdOXyV+wB5/lCms9HXKTv+Pp1K1bJaC8CuedcP sIMdURTJu7T1rfX4+lSWkTuS7iicVmAIH1+vbF44UPzuT47wnzJMVNhNY9fDCrAJT1wM HLmR+B9asau6+aNymu4F0Ry9NiZ7MrWyplIB8MbrJjdTYnsnPYjuGzU+5NL+4k4Uz/WP P7Jw== X-Gm-Message-State: AOAM5326gt6QuLJ/L9F4PyXEBRI3CMmEEiN84vjcJ96a9Njy9Nx/t/nT iw0vZCQpe+I7X4DCwBRhpTervA== X-Google-Smtp-Source: ABdhPJyDOzYizTE65HxMKlAObhHhsydD59/aI2ct3w2qud0gjNmE0lvd7l1OW4pnb9pWi6uO+4NRbQ== X-Received: by 2002:ac2:57c7:0:b0:472:208d:926f with SMTP id k7-20020ac257c7000000b00472208d926fmr16627243lfo.224.1651741954093; Thu, 05 May 2022 02:12:34 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v26-20020ac2593a000000b0047255d211e8sm133564lfi.279.2022.05.05.02.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:33 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 3/7] PCI: dwc: Add msi_host_deinit callback Date: Thu, 5 May 2022 12:12:27 +0300 Message-Id: <20220505091231.1308963-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add msi_host_deinit() callback as a counterpart to msi_host_init(). It will tear down MSI support in case host has to run host-specific ops. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 43d1d6116007..92dcaeabe2bf 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -424,7 +424,9 @@ int dw_pcie_host_init(struct pcie_port *pp) return 0; err_free_msi: - if (pp->has_msi_ctrl) + if (pp->ops->msi_host_deinit) + pp->ops->msi_host_deinit(pp); + else if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); return ret; } @@ -434,7 +436,9 @@ void dw_pcie_host_deinit(struct pcie_port *pp) { pci_stop_root_bus(pp->bridge->bus); pci_remove_root_bus(pp->bridge->bus); - if (pp->has_msi_ctrl) + if (pp->ops->msi_host_deinit) + pp->ops->msi_host_deinit(pp); + else if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 7d6e9b7576be..e1c48b71e0d2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -175,6 +175,7 @@ enum dw_pcie_device_mode { struct dw_pcie_host_ops { int (*host_init)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); + void (*msi_host_deinit)(struct pcie_port *pp); }; struct pcie_port { From patchwork Thu May 5 09:12:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12839259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D3CFC4321E for ; Thu, 5 May 2022 09:12:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351904AbiEEJQR (ORCPT ); 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Thu, 05 May 2022 02:12:34 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 4/7] PCI: dwc: Export several functions useful for MSI implentations Date: Thu, 5 May 2022 12:12:28 +0300 Message-Id: <20220505091231.1308963-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Supporting multiple MSI interrupts on Qualcomm hardware would benefit from having these functions being exported rather than static. Note that both designware and qcom driver can not be built as modules, so no need to use EXPORT_SYMBOL here. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 62 ++++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 11 ++++ 2 files changed, 49 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 92dcaeabe2bf..c3b8ab278a00 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -255,7 +255,39 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) return 0; } -static void dw_pcie_free_msi(struct pcie_port *pp) +int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + int ret; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + if (pp->msi_irq > 0) + irq_set_chained_handler_and_data(pp->msi_irq, + dw_chained_msi_isr, + pp); + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + return ret; + } + + return 0; +} + +void dw_pcie_free_msi(struct pcie_port *pp) { if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); @@ -357,6 +389,9 @@ int dw_pcie_host_init(struct pcie_port *pp) return -EINVAL; } + /* this can be overridden by msi_host_init() if necessary */ + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + if (pp->ops->msi_host_init) { ret = pp->ops->msi_host_init(pp); if (ret < 0) @@ -377,30 +412,9 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_allocate_msi(pp); + if (ret < 0) return ret; - - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, - dw_chained_msi_isr, - pp); - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - if (dma_mapping_error(pci->dev, pp->msi_data)) { - dev_err(pci->dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - goto err_free_msi; - } } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e1c48b71e0d2..f72447f15dc5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -374,6 +374,8 @@ void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int dw_pcie_allocate_msi(struct pcie_port *pp); +void dw_pcie_free_msi(struct pcie_port *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { @@ -403,6 +405,15 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, { return NULL; } + +static int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + return -EINVAL; +} + +static void dw_pcie_free_msi(struct pcie_port *pp) +{ +} #endif #ifdef CONFIG_PCIE_DW_EP From patchwork Thu May 5 09:12:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12839262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 748B4C3527A for ; Thu, 5 May 2022 09:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351957AbiEEJQT (ORCPT ); Thu, 5 May 2022 05:16:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351970AbiEEJQR (ORCPT ); Thu, 5 May 2022 05:16:17 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7013C4C787 for ; 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Thu, 05 May 2022 02:12:35 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v26-20020ac2593a000000b0047255d211e8sm133564lfi.279.2022.05.05.02.12.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 5/7] PCI: qcom: Handle MSIs routed to multiple GIC interrupts Date: Thu, 5 May 2022 12:12:29 +0300 Message-Id: <20220505091231.1308963-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On some of Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Thus to receive higher MSI vectors properly, add separate msi_host_init()/msi_host_deinit() handling additional host IRQs. Note, that if DT doesn't list extra MSI interrupts, the driver will limit the amount of supported MSI vectors accordingly (to 32). Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 137 ++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 375f27ab9403..6cd1c2cc6d9e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -194,6 +194,7 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + unsigned int has_split_msi_irqs:1; unsigned int pipe_clk_need_muxing:1; unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; @@ -209,6 +210,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_cfg *cfg; + int msi_irqs[MAX_MSI_CTRLS]; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -1387,6 +1389,124 @@ static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) return 0; } +static void qcom_chained_msi_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + int irq = irq_desc_get_irq(desc); + struct pcie_port *pp; + int i, pos; + unsigned long val; + u32 status, num_ctrls; + struct dw_pcie *pci; + struct qcom_pcie *pcie; + + chained_irq_enter(chip, desc); + + pp = irq_desc_get_handler_data(desc); + pci = to_dw_pcie_from_pp(pp); + pcie = to_qcom_pcie(pci); + + /* + * Unlike generic dw_handle_msi_irq(), we can determine which group of + * MSIs triggered the IRQ, so process just that group. + */ + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + for (i = 0; i < num_ctrls; i++) { + if (pcie->msi_irqs[i] == irq) + break; + } + + if (WARN_ON_ONCE(unlikely(i == num_ctrls))) + goto out; + + status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE)); + if (!status) + goto out; + + val = status; + pos = 0; + while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, + pos)) != MAX_MSI_IRQS_PER_CTRL) { + generic_handle_domain_irq(pp->irq_domain, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); + pos++; + } + +out: + chained_irq_exit(chip, desc); +} + +static int qcom_pcie_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + struct platform_device *pdev = to_platform_device(pci->dev); + char irq_name[] = "msiXXX"; + unsigned int ctrl, num_ctrls; + int msi_irq, ret; + + pp->msi_irq = -EINVAL; + + /* + * We provide our own implementation of MSI init/deinit, but rely on + * using the rest of DWC MSI functionality. + */ + pp->has_msi_ctrl = true; + + msi_irq = platform_get_irq_byname_optional(pdev, "msi"); + if (msi_irq < 0) { + msi_irq = platform_get_irq(pdev, 0); + if (msi_irq < 0) + return msi_irq; + } + + pcie->msi_irqs[0] = msi_irq; + + for (num_ctrls = 1; num_ctrls < MAX_MSI_CTRLS; num_ctrls++) { + snprintf(irq_name, sizeof(irq_name), "msi%d", num_ctrls + 1); + msi_irq = platform_get_irq_byname_optional(pdev, irq_name); + if (msi_irq == -ENXIO) + break; + + pcie->msi_irqs[num_ctrls] = msi_irq; + } + + pp->num_vectors = num_ctrls * MAX_MSI_IRQS_PER_CTRL; + dev_info(&pdev->dev, "Using %d MSI vectors\n", pp->num_vectors); + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + pp->irq_mask[ctrl] = ~0; + + ret = dw_pcie_allocate_msi(pp); + if (ret) + return ret; + + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + irq_set_chained_handler_and_data(pcie->msi_irqs[ctrl], + qcom_chained_msi_isr, + pp); + + return 0; +} + +static void qcom_pcie_msi_host_deinit(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie = to_qcom_pcie(pci); + unsigned int ctrl, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + irq_set_chained_handler_and_data(pcie->msi_irqs[ctrl], + NULL, + NULL); + + dw_pcie_free_msi(pp); +} + static int qcom_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1435,6 +1555,12 @@ static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { .host_init = qcom_pcie_host_init, }; +static const struct dw_pcie_host_ops qcom_pcie_msi_dw_ops = { + .host_init = qcom_pcie_host_init, + .msi_host_init = qcom_pcie_msi_host_init, + .msi_host_deinit = qcom_pcie_msi_host_deinit, +}; + /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ static const struct qcom_pcie_ops ops_2_1_0 = { .get_resources = qcom_pcie_get_resources_2_1_0, @@ -1508,6 +1634,7 @@ static const struct qcom_pcie_cfg ipq8064_cfg = { static const struct qcom_pcie_cfg msm8996_cfg = { .ops = &ops_2_3_2, + .has_split_msi_irqs = true, }; static const struct qcom_pcie_cfg ipq8074_cfg = { @@ -1520,6 +1647,7 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_split_msi_irqs = true, .has_tbu_clk = true, }; @@ -1532,12 +1660,14 @@ static const struct qcom_pcie_cfg sm8150_cfg = { static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irqs = true, .has_tbu_clk = true, .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irqs = true, .has_ddrss_sf_tbu_clk = true, .pipe_clk_need_muxing = true, .has_aggre0_clk = true, @@ -1546,6 +1676,7 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irqs = true, .has_ddrss_sf_tbu_clk = true, .pipe_clk_need_muxing = true, .has_aggre1_clk = true, @@ -1553,6 +1684,7 @@ static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_split_msi_irqs = true, .has_tbu_clk = true, .pipe_clk_need_muxing = true, }; @@ -1626,7 +1758,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (ret) goto err_pm_runtime_put; - pp->ops = &qcom_pcie_dw_ops; + if (pcie->cfg->has_split_msi_irqs) + pp->ops = &qcom_pcie_msi_dw_ops; + else + pp->ops = &qcom_pcie_dw_ops; ret = phy_init(pcie->phy); if (ret) { From patchwork Thu May 5 09:12:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12839261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF329C4167D for ; Thu, 5 May 2022 09:12:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351855AbiEEJQU (ORCPT ); Thu, 5 May 2022 05:16:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351987AbiEEJQR (ORCPT ); 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Thu, 05 May 2022 02:12:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v6 6/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Date: Thu, 5 May 2022 12:12:30 +0300 Message-Id: <20220505091231.1308963-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..fd3290e0e220 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,20 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: + minItems: 1 items: - const: msi + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: msi8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +632,40 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + - properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + unevaluatedProperties: false examples: From patchwork Thu May 5 09:12:31 2022 Content-Type: text/plain; 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Thu, 05 May 2022 02:12:37 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v26-20020ac2593a000000b0047255d211e8sm133564lfi.279.2022.05.05.02.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 7/7] arm64: dts: qcom: sm8250: provide additional MSI interrupts Date: Thu, 5 May 2022 12:12:31 +0300 Message-Id: <20220505091231.1308963-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> References: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On SM8250 each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe0 host. Tested on Qualcomm RB5 platform with first group of MSI interrupts being used by the PME and attached ath11k WiFi chip using second group of MSI interrupts. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 410272a1e19b..0659ac45c651 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1807,8 +1807,15 @@ pcie0: pci@1c00000 { ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */