From patchwork Thu May 5 19:35:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12840069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84610C433F5 for ; Thu, 5 May 2022 19:34:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0191610E775; Thu, 5 May 2022 19:34:43 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 552EE10E775 for ; Thu, 5 May 2022 19:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651779281; x=1683315281; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=BvVlNr0Sq03rHwyQO1/jwxZgKJnwX3tctqYJuB8X4as=; b=KiMmqj59UQwtRvbG77x1Hs+GO3beHzm5r+bFxzlaoK+HODy89NYOUORl wauuxdBYG2YVepHegYVaX8a1yTapyKioI3GdRXSHVf6CCqPyRXU/NIMxp 4xJxW+PprVlPD8flubQHECSnGnavfKKGpzuZ4DWc0hQNx3aNY/we7SlBF 50BPx6JT8w9kWza9CnpffBRz7bYOD2QV5C+kPGsqcFwmGkd60ZNYwJjdM hxyQaJxvVWxaHhwD5bCT5IZ9L+3fWzcoMHT6GC4YFeFaFj7+MtQahXLp1 JXWlFOaCZKwIFUNyA+BE50dV1ilNjlsxHfz273bzg5Ygo0A/cCD36jF15 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="265823117" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="265823117" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:40 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="665116653" Received: from josouza-mobl2.fso.intel.com ([10.230.18.139]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:39 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 5 May 2022 12:35:18 -0700 Message-Id: <20220505193524.276400-1-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 1/7] drm/i915: Drop has_gt_uc from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as all platforms with graphics version 9 or newer has graphics microcontroller. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 1 - 4 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2dddc27a1b0ed..af3967149b2d2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1355,7 +1355,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, */ #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs) -#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) +#define HAS_GT_UC(dev_priv) (GRAPHICS_VER(dev_priv) >= 9) #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 0512c66fa4f3f..5bd9cb8998527 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -2008,7 +2008,7 @@ __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 du return ERR_PTR(-ENOMEM); } - if (INTEL_INFO(i915)->has_gt_uc) { + if (HAS_GT_UC(i915)) { error->gt->uc = gt_record_uc(error->gt, compress); if (error->gt->uc) { if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 498708b33924f..6d4e2c4292f3b 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -644,7 +644,6 @@ static const struct intel_device_info chv_info = { GEN(9), \ GEN9_DEFAULT_PAGE_SIZES, \ .display.has_dmc = 1, \ - .has_gt_uc = 1, \ .display.has_hdcp = 1, \ .display.has_ipc = 1, \ .display.has_psr = 1, \ @@ -705,7 +704,6 @@ static const struct intel_device_info skl_gt4_info = { .has_rps = true, \ .display.has_dp_mst = 1, \ .has_logical_ring_contexts = 1, \ - .has_gt_uc = 1, \ .dma_mask_size = 39, \ .ppgtt_type = INTEL_PPGTT_FULL, \ .ppgtt_size = 48, \ @@ -1008,7 +1006,6 @@ static const struct intel_device_info adl_p_info = { .has_64bit_reloc = 1, \ .has_flat_ccs = 1, \ .has_global_mocs = 1, \ - .has_gt_uc = 1, \ .has_llc = 1, \ .has_logical_ring_contexts = 1, \ .has_logical_ring_elsq = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index e7d2cf7d65c85..dcc8c63ae6ed4 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -146,7 +146,6 @@ enum intel_ppgtt_type { func(has_4tile); \ func(has_flat_ccs); \ func(has_global_mocs); \ - func(has_gt_uc); \ func(has_heci_pxp); \ func(has_heci_gscfi); \ func(has_guc_deprivilege); \ From patchwork Thu May 5 19:35:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12840070 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA10EC433EF for ; Thu, 5 May 2022 19:34:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E556C10E897; Thu, 5 May 2022 19:34:43 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4B54C10E775 for ; Thu, 5 May 2022 19:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651779282; x=1683315282; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QQ1m96K81HWmmIDMEDXrsUnC68Y+lsvdBk2l29CjSjw=; b=GDtQGJRvZy8rOIxOIPb+UdRB9eM1N1i9Myhyxk0JFq4Gf+wGCnQIkFkP N7LoU3rBdqvUTYQ2kMOFfNq3CkP3iWPp/Hh64r/qoeYsGdjdveXFpNwan vTq+4YLUE+6TvdDdV3pu0Atzuy3d8+ouqcvvXtU4Qd69SZOeZvIrEJC0t hRZM79ByCEe886Hm5UkckCAr+aE6eH4xkx1YjZOHORMZT91FmlD8t9fRB HfO573nMT5n+GN3lKrvE0sd7Lxg766nH/p6kgGy5Bt/XauUOGGuDu/xEC LNrTRC9cJAzjLE7gGYXqVL1kXegkHbJEaSclIiUaiYsJvoe7sWyufF1US g==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="265823119" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="265823119" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:42 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="665116662" Received: from josouza-mobl2.fso.intel.com ([10.230.18.139]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:41 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 5 May 2022 12:35:19 -0700 Message-Id: <20220505193524.276400-2-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505193524.276400-1-jose.souza@intel.com> References: <20220505193524.276400-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 2/7] drm/i915: Drop has_rc6 from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as all platforms with graphics version 6 or newer have software support for this feature. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_pci.c | 8 -------- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index af3967149b2d2..806bd6328383b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1307,7 +1307,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0) -#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) +/* ilk does support rc6, but we do not implement [power] contexts */ +#define HAS_RC6(dev_priv) (GRAPHICS_VER(dev_priv) >= 6) #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6d4e2c4292f3b..e21d08375b25d 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -376,8 +376,6 @@ static const struct intel_device_info gm45_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \ .has_snoop = true, \ .has_coherent_ggtt = true, \ - /* ilk does support rc6, but we do not implement [power] contexts */ \ - .has_rc6 = 0, \ .dma_mask_size = 36, \ I9XX_PIPE_OFFSETS, \ I9XX_CURSOR_OFFSETS, \ @@ -407,7 +405,6 @@ static const struct intel_device_info ilk_m_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .has_rc6 = 1, \ .has_rc6p = 1, \ .has_rps = true, \ .dma_mask_size = 40, \ @@ -458,7 +455,6 @@ static const struct intel_device_info snb_m_gt2_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .has_rc6 = 1, \ .has_rc6p = 1, \ .has_reset_engine = true, \ .has_rps = true, \ @@ -518,7 +514,6 @@ static const struct intel_device_info vlv_info = { .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), .has_runtime_pm = 1, - .has_rc6 = 1, .has_reset_engine = true, .has_rps = true, .display.has_gmch = 1, @@ -617,7 +612,6 @@ static const struct intel_device_info chv_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), .has_64bit_reloc = 1, .has_runtime_pm = 1, - .has_rc6 = 1, .has_rps = true, .has_logical_ring_contexts = 1, .display.has_gmch = 1, @@ -700,7 +694,6 @@ static const struct intel_device_info skl_gt4_info = { .display.has_psr_hw_tracking = 1, \ .has_runtime_pm = 1, \ .display.has_dmc = 1, \ - .has_rc6 = 1, \ .has_rps = true, \ .display.has_dp_mst = 1, \ .has_logical_ring_contexts = 1, \ @@ -1010,7 +1003,6 @@ static const struct intel_device_info adl_p_info = { .has_logical_ring_contexts = 1, \ .has_logical_ring_elsq = 1, \ .has_mslices = 1, \ - .has_rc6 = 1, \ .has_reset_engine = 1, \ .has_rps = 1, \ .has_runtime_pm = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index dcc8c63ae6ed4..ab283d88461e0 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -156,7 +156,6 @@ enum intel_ppgtt_type { func(has_mslices); \ func(has_pooled_eu); \ func(has_pxp); \ - func(has_rc6); \ func(has_rc6p); \ func(has_rps); \ func(has_runtime_pm); \ From patchwork Thu May 5 19:35:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12840071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 502EAC433F5 for ; Thu, 5 May 2022 19:34:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 398B310EF3E; Thu, 5 May 2022 19:34:46 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8E45510E897 for ; Thu, 5 May 2022 19:34:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651779283; x=1683315283; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m3kEs6h8cNzXVLPtQmPGnx2xl/MBRli954a2q2Mh4A0=; b=HJZ1pOWl2CE7YNL5bVNoxFMkqXzaLqZyC+K4aRSGfuGX3cI0ry/VmAZ6 jFsXgJ+x8qBAiaa/AUeY5lmk/CpQS/+AXa0fiQ4eqedFo4kFieplrzBAA eWpcuYvqaSSDX7eJVAMKfmBnRbzijfCagPVy56XLnX9FJmBwljOB3Jntp aWj5yvnrimHQ6+n7/klFotBZ5EXZ7iuo/iC6KQCyavCld8Y7W4HQBmegr QMaLEMmFr3nh1hQhds5sZ+R/ToV95vZf0p+iHfnr5vLdoPUilOzM/+yvi ixsGNX7xfiF/55Jvkq4JKLtzRhSzayVY1DYFbF++4v8zqYJhXABc8VWL2 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="265823124" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="265823124" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:43 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="665116670" Received: from josouza-mobl2.fso.intel.com ([10.230.18.139]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:42 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 5 May 2022 12:35:20 -0700 Message-Id: <20220505193524.276400-3-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505193524.276400-1-jose.souza@intel.com> References: <20220505193524.276400-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 3/7] drm/i915: Drop has_reset_engine from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as all platforms with graphics version 7 or newer can reset engines. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 5 ----- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 5422a3b84bd44..894f17f8b4cea 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -699,7 +699,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt) if (gt->i915->params.reset < 2) return false; - return INTEL_INFO(gt->i915)->has_reset_engine; + return GRAPHICS_VER(gt->i915) >= 7; } int intel_reset_guc(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index e21d08375b25d..6f8bc9008fe02 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -456,7 +456,6 @@ static const struct intel_device_info snb_m_gt2_info = { .has_coherent_ggtt = true, \ .has_llc = 1, \ .has_rc6p = 1, \ - .has_reset_engine = true, \ .has_rps = true, \ .dma_mask_size = 40, \ .ppgtt_type = INTEL_PPGTT_ALIASING, \ @@ -514,7 +513,6 @@ static const struct intel_device_info vlv_info = { .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), .has_runtime_pm = 1, - .has_reset_engine = true, .has_rps = true, .display.has_gmch = 1, .display.has_hotplug = 1, @@ -618,7 +616,6 @@ static const struct intel_device_info chv_info = { .dma_mask_size = 39, .ppgtt_type = INTEL_PPGTT_FULL, .ppgtt_size = 32, - .has_reset_engine = 1, .has_snoop = true, .has_coherent_ggtt = false, .display_mmio_offset = VLV_DISPLAY_BASE, @@ -700,7 +697,6 @@ static const struct intel_device_info skl_gt4_info = { .dma_mask_size = 39, \ .ppgtt_type = INTEL_PPGTT_FULL, \ .ppgtt_size = 48, \ - .has_reset_engine = 1, \ .has_snoop = true, \ .has_coherent_ggtt = false, \ .display.has_ipc = 1, \ @@ -1003,7 +999,6 @@ static const struct intel_device_info adl_p_info = { .has_logical_ring_contexts = 1, \ .has_logical_ring_elsq = 1, \ .has_mslices = 1, \ - .has_reset_engine = 1, \ .has_rps = 1, \ .has_runtime_pm = 1, \ .ppgtt_size = 48, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index ab283d88461e0..52460093c76e6 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -142,7 +142,6 @@ enum intel_ppgtt_type { func(has_64k_pages); \ func(needs_compact_pt); \ func(gpu_reset_clobbers_display); \ - func(has_reset_engine); \ func(has_4tile); \ func(has_flat_ccs); \ func(has_global_mocs); \ From patchwork Thu May 5 19:35:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12840072 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D043C433EF for ; Thu, 5 May 2022 19:34:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6936F10EF62; Thu, 5 May 2022 19:34:46 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id E983B10EEFA for ; Thu, 5 May 2022 19:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651779284; x=1683315284; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lJEycotpGMotN8PxfHyeDW00dG8xFzScYfsyLWqhR1A=; b=VP7o1ZkECUEIJA870XadRrRB2alngo+rRyAw7ryEO/ZS+0taFpJe4l8X I63lAxNPnGYzQQkISgXub32hdalwcqWtfcj7XoaEJ+Fb18zx6EqsH3Kkg PqVvHYcUs/R6d9l6T6wvC7GzrsXeX17AmxNKGWIwquzKmQzPigaKiCfo6 POP9W+14bOqRvrnQumpi4BMArjaKw1S8PSpt2N+v3VYEiJ0+BDv62jUrY Q31xHIseQys0WCKRwev2X3J0wR7ITZfLUzKZ1ArQfU/FrlNwTThLMxuI6 rfnpgM9ArBsFFroAtqnXGMPV5WW+6cEBliR+WfDVLTqxmuS5yFsSkbg8v g==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="265823128" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="265823128" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:44 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="665116679" Received: from josouza-mobl2.fso.intel.com ([10.230.18.139]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:43 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 5 May 2022 12:35:21 -0700 Message-Id: <20220505193524.276400-4-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505193524.276400-1-jose.souza@intel.com> References: <20220505193524.276400-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 4/7] drm/i915: Drop has_logical_ring_elsq from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as all platforms with graphics version 11 or newer has this feature. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 3 +-- drivers/gpu/drm/i915/i915_pci.c | 4 +--- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 806bd6328383b..5538564bc1d25 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1246,8 +1246,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ (INTEL_INFO(dev_priv)->has_logical_ring_contexts) -#define HAS_LOGICAL_RING_ELSQ(dev_priv) \ - (INTEL_INFO(dev_priv)->has_logical_ring_elsq) +#define HAS_LOGICAL_RING_ELSQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11) #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6f8bc9008fe02..2dc0284629d30 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -809,8 +809,7 @@ static const struct intel_device_info cml_gt2_info = { .dbuf.size = 2048, \ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ .display.has_dsc = 1, \ - .has_coherent_ggtt = false, \ - .has_logical_ring_elsq = 1 + .has_coherent_ggtt = false static const struct intel_device_info icl_info = { GEN11_FEATURES, @@ -997,7 +996,6 @@ static const struct intel_device_info adl_p_info = { .has_global_mocs = 1, \ .has_llc = 1, \ .has_logical_ring_contexts = 1, \ - .has_logical_ring_elsq = 1, \ .has_mslices = 1, \ .has_rps = 1, \ .has_runtime_pm = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 52460093c76e6..bef65e3f02c55 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -151,7 +151,6 @@ enum intel_ppgtt_type { func(has_l3_dpf); \ func(has_llc); \ func(has_logical_ring_contexts); \ - func(has_logical_ring_elsq); \ func(has_mslices); \ func(has_pooled_eu); \ func(has_pxp); \ From patchwork Thu May 5 19:35:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12840073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B047C433F5 for ; Thu, 5 May 2022 19:34:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0451710EEFA; Thu, 5 May 2022 19:34:48 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3100A10EEFA for ; Thu, 5 May 2022 19:34:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651779286; x=1683315286; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=efkgSh+9vSYDS+2DTStwZVlMHikSdx+Mp2r+8QDQTAY=; b=Qc22KK+et0/C6/qrKGUhf4rZu6oYR8JYoOZipQj3oLbhcxWyU2g+Tfac p6h18KmhtvKwVqIqhnjHVFMs2VYCSlUDbebIolqYgRCdBQkKdYU3LTUQM irgu77NGAOnKaF/rlGXMEqiT87gUcwtxYETyhuAsWKkwN54/fncE41SdV ZvhRrbYyYPbD2E3Ej8uJoxm6bSK2PCjmaVCJVdMZrADlfYMPRe98ZjNUT +cgoOXgOL4zRhPGqzhdzRsZKT57lA/S26+uXY4qhY9QBTyAnjld0KwMc8 ZcdmepbVVjviPBQLdpuTjMNUna+rPSFwbl69tNV/MNR06MBfugUZj17pI g==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="265823131" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="265823131" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:46 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="665116685" Received: from josouza-mobl2.fso.intel.com ([10.230.18.139]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:44 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 5 May 2022 12:35:22 -0700 Message-Id: <20220505193524.276400-5-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505193524.276400-1-jose.souza@intel.com> References: <20220505193524.276400-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 5/7] drm/i915: Drop has_ddi from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as all platforms with display version 9 or newer, haswell or broadwell supports it. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_pci.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5538564bc1d25..600d8cee272da 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1298,7 +1298,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) -#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) +#define HAS_DDI(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || \ + IS_BROADWELL(dev_priv) || \ + IS_HASWELL(dev_priv)) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) #define HAS_PSR_HW_TRACKING(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 2dc0284629d30..a0693d9ff9cee 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -535,7 +535,6 @@ static const struct intel_device_info vlv_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ - .display.has_ddi = 1, \ .display.has_fpga_dbg = 1, \ .display.has_dp_mst = 1, \ .has_rc6p = 0 /* RC6p removed-by HSW */, \ @@ -683,7 +682,6 @@ static const struct intel_device_info skl_gt4_info = { BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ .has_64bit_reloc = 1, \ - .display.has_ddi = 1, \ .display.has_fpga_dbg = 1, \ .display.fbc_mask = BIT(INTEL_FBC_A), \ .display.has_hdcp = 1, \ @@ -932,7 +930,6 @@ static const struct intel_device_info adl_s_info = { .dbuf.size = 4096, \ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ BIT(DBUF_S4), \ - .display.has_ddi = 1, \ .display.has_dmc = 1, \ .display.has_dp_mst = 1, \ .display.has_dsb = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index bef65e3f02c55..bc71ce48763ad 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -167,7 +167,6 @@ enum intel_ppgtt_type { func(cursor_needs_physical); \ func(has_cdclk_crawl); \ func(has_dmc); \ - func(has_ddi); \ func(has_dp_mst); \ func(has_dsb); \ func(has_dsc); \ From patchwork Thu May 5 19:35:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12840074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12515C433EF for ; Thu, 5 May 2022 19:34:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A22710EF7F; Thu, 5 May 2022 19:34:49 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 66B5910EEFA for ; Thu, 5 May 2022 19:34:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651779287; x=1683315287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T0uYsoByWi4EQfWUnkltUh/77iK321tWVbw86+rVe5M=; b=Hisj1TbwnXXZAjRPeSmnpT9o6ybMotrS+GmAOZ9pEg4qYZlqueokWJux UR0+sYEW18RDDfvUHrdnlQyTGcOpD69HIe0AhhLaAvk1X74q2tIgkT1lX Yqq9bqIcpn1RUZTfIxFfyE9b7URyZ7LOk4UIbZ6Bzr457aBr46bkeDeEe rv/AVnNjE+BHMAvSbRreto5hmvurAN022FLZtplJNXHeI2KutByDIHX6X +SK/QA1YkY6paPcVJPBcrcHFHMYdtLprCW/UyMy+njsgejFfChVoGLaki BX43FSfs9kaChJd4WnkPyqL5i8yHlIPuPLWYhtynwXPTAR1m31HkljndJ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="265823135" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="265823135" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:47 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="665116694" Received: from josouza-mobl2.fso.intel.com ([10.230.18.139]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:46 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 5 May 2022 12:35:23 -0700 Message-Id: <20220505193524.276400-6-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505193524.276400-1-jose.souza@intel.com> References: <20220505193524.276400-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 6/7] drm/i915: Drop has_dp_mst from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as the requirement to support it is the DDI support. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 600d8cee272da..af840fbd6c33c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1294,13 +1294,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) -#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) #define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) #define HAS_DDI(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || \ IS_BROADWELL(dev_priv) || \ IS_HASWELL(dev_priv)) +#define HAS_DP_MST(dev_priv) (HAS_DDI(dev_priv)) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) #define HAS_PSR_HW_TRACKING(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a0693d9ff9cee..3c4ce836bb99a 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -536,7 +536,6 @@ static const struct intel_device_info vlv_info = { .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ .display.has_fpga_dbg = 1, \ - .display.has_dp_mst = 1, \ .has_rc6p = 0 /* RC6p removed-by HSW */, \ HSW_PIPE_OFFSETS, \ .has_runtime_pm = 1 @@ -690,7 +689,6 @@ static const struct intel_device_info skl_gt4_info = { .has_runtime_pm = 1, \ .display.has_dmc = 1, \ .has_rps = true, \ - .display.has_dp_mst = 1, \ .has_logical_ring_contexts = 1, \ .dma_mask_size = 39, \ .ppgtt_type = INTEL_PPGTT_FULL, \ @@ -931,7 +929,6 @@ static const struct intel_device_info adl_s_info = { .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ BIT(DBUF_S4), \ .display.has_dmc = 1, \ - .display.has_dp_mst = 1, \ .display.has_dsb = 1, \ .display.has_dsc = 1, \ .display.fbc_mask = BIT(INTEL_FBC_A), \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index bc71ce48763ad..7fb90f6c43b78 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -167,7 +167,6 @@ enum intel_ppgtt_type { func(cursor_needs_physical); \ func(has_cdclk_crawl); \ func(has_dmc); \ - func(has_dp_mst); \ func(has_dsb); \ func(has_dsc); \ func(has_fpga_dbg); \ From patchwork Thu May 5 19:35:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12840075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2AE7FC433FE for ; Thu, 5 May 2022 19:34:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9381810EF90; Thu, 5 May 2022 19:34:50 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id A7B1110EF7F for ; Thu, 5 May 2022 19:34:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651779288; x=1683315288; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lA+KJxXURNuI7tsKQeojrr7QtX91oVkcjhxbSVQH99s=; b=LCC4GB5Dy3E5Jtz8OHiBjTQg6PRFLHAc+zPvjN8yds9RMRzh/KiCZPpA JYjecplgt3lXM8DO+dBLoIRksRfNN10qycaM2YpLfYq/tNI6loO6obCTP noDn8fJX/pGTzx+AcgWOlgbrVJIACjmDVWZPX2dgDQ62Xvm1MWhVsh0hx TKikyf5ZhwbPBTDyQiUnGKoRXWz0kzbiu8uC45W1+I1z0Zq5KLGfMncrs PS2//HSiDT5y4yY0URGFo8GdwEf2LmIi89qv7l589Hir2FIRZuHB3/sVp 06YSLSa4hMDV+W08nWagi3f4a4Unlh5++KXZ1Tsb96bvZ2gviNs0dBfZn Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="265823136" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="265823136" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:48 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="665116701" Received: from josouza-mobl2.fso.intel.com ([10.230.18.139]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 12:34:47 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 5 May 2022 12:35:24 -0700 Message-Id: <20220505193524.276400-7-jose.souza@intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505193524.276400-1-jose.souza@intel.com> References: <20220505193524.276400-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH CI 7/7] drm/i915: Drop has_psr from device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" No need to have this parameter in intel_device_info struct as all platforms with display version 9 or newer has this feature. As a side effect of the of removal this flag, it will not be printed in dmesg during driver load anymore and developers will have to rely on to check the macro and compare with platform being used and IP versions of it. Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index af840fbd6c33c..bd0a9b5fc53f4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1302,7 +1302,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_HASWELL(dev_priv)) #define HAS_DP_MST(dev_priv) (HAS_DDI(dev_priv)) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) -#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) +#define HAS_PSR(dev_priv) (DISPLAY_VER(dev_priv) >= 9) #define HAS_PSR_HW_TRACKING(dev_priv) \ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 3c4ce836bb99a..799573a5e5a6f 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -635,7 +635,6 @@ static const struct intel_device_info chv_info = { .display.has_dmc = 1, \ .display.has_hdcp = 1, \ .display.has_ipc = 1, \ - .display.has_psr = 1, \ .display.has_psr_hw_tracking = 1, \ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ .dbuf.slice_mask = BIT(DBUF_S1) @@ -684,7 +683,6 @@ static const struct intel_device_info skl_gt4_info = { .display.has_fpga_dbg = 1, \ .display.fbc_mask = BIT(INTEL_FBC_A), \ .display.has_hdcp = 1, \ - .display.has_psr = 1, \ .display.has_psr_hw_tracking = 1, \ .has_runtime_pm = 1, \ .display.has_dmc = 1, \ @@ -936,7 +934,6 @@ static const struct intel_device_info adl_s_info = { .display.has_hdcp = 1, \ .display.has_hotplug = 1, \ .display.has_ipc = 1, \ - .display.has_psr = 1, \ .display.ver = 13, \ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .pipe_offsets = { \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 7fb90f6c43b78..a2e53b8683285 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -177,7 +177,6 @@ enum intel_ppgtt_type { func(has_ipc); \ func(has_modular_fia); \ func(has_overlay); \ - func(has_psr); \ func(has_psr_hw_tracking); \ func(overlay_needs_physical); \ func(supports_tv);