From patchwork Sat May 7 19:06:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFD54C433FE for ; Sat, 7 May 2022 19:08:43 +0000 (UTC) Received: from localhost ([::1]:59456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPnG-0007XM-PK for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:08:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPlG-0004h2-53; Sat, 07 May 2022 15:06:38 -0400 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]:41520) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nnPlE-0001XM-Gh; Sat, 07 May 2022 15:06:37 -0400 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-edf9ddb312so9612740fac.8; Sat, 07 May 2022 12:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7IGWV3nomi2hRzL2w+japFtQez8lN0OWE2s3gRdwtpo=; b=VanFztx6S/5XXK5SX6vDwCI0EnH6nYRBB4qv9mJtWAW5lM2K1LLNP4ch7fHkeeB7wV 085ulbHuFUB3VAF0bUyR1DiuuEQnrhsxkymazk8Gugo32tRebd9FaOMf88gWsJ4KhzvB azZWYP8YQOf6J916I8dO3i18W9a1fqQybrTtPZtUGEauNT33nNvMbIOEpLT+fjLXs7vc Ye1c+JsM6qN8i0lMS8vpQRcEh5G5NrqDJGbELsEU9E+dBcJ4fcVotVyOccaEfMxXKIC6 Fi8Nh5gt1zRz2mdW00wZxlI7Mk68QUy3YWDDaIZm/WrX8hX1eSRrK5eNvzJQJTfr5/UL +I5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7IGWV3nomi2hRzL2w+japFtQez8lN0OWE2s3gRdwtpo=; b=CNSQlFiTRdxoL3LF9hrcb+Ct4qIGPOrMkSe+j0KNJTyNSqU3jjXrL0oclQwmZ6zK4j MqrnK1sL2Y2mo+G4BjQSGAmGny5gzbci7SnTc9s1gB2BX+0l8ixEsq95fAhsML3InUSo 0e7t3Nq+7oQl0ZUm+rRQHR75AYOApCb82RODyBuRir5z+awBTb3qdZENI2d4Qp0MRuNK 226vgUlwLMsQ4hL4Nw+U3jrSyK/pt2PKzUBj4kDBqdEEIjBB4LURYByFO/4aMSV7tL1l qDST0klQXaxRVi6eAHptUBfyYKxsvKLQ/E+XKpvAZt2RaDAdhVQoMcCrs1P1AAnT1Eyz +O5Q== X-Gm-Message-State: AOAM532uyG09EHlCG3W6CgQGwvq+FntaCcHqw/BwGewPDBY91JwOViwy IFnIRfhXAgmlNy5NOjTq57EIXlUppGU= X-Google-Smtp-Source: ABdhPJwE3h2VYRoje/uIquzctSjzZEYCA5nr5N3QFceZKpSU0cFsP+vfRJu3zK+Z95Z3wj7Kd7iv1Q== X-Received: by 2002:a05:6870:3b85:b0:ee:4232:a0c3 with SMTP id gi5-20020a0568703b8500b000ee4232a0c3mr2654719oab.29.1651950394775; Sat, 07 May 2022 12:06:34 -0700 (PDT) Received: from balboa.ibmmodules.com (201-1-57-208.dsl.telesp.net.br. [201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:34 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 01/17] ppc/pnv: rename PnvPHB3.ioda* to PnvPHB3.ioda2* Date: Sat, 7 May 2022 16:06:08 -0300 Message-Id: <20220507190624.507419-2-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We're going to merge all the existing pnv-phb models into a single pnv-phb model. Users will be able to add phbs by using the same pnv-phb device, regardless of which powernv machine is being used, and internally we'll handle which PHB version the device needs to have. The unified pnv-phb model needs to be usable by the existing pnv_phb3 and pnv_phb4 code base. One way of accomplishing that is to merge PnvPHB3 and PnvPHB4 into a single PnvPHB struct. To do that we need to handle the cases where the same attribute might have different meaning/semantics depending on the version. One of these attributes is the 'ioda' arrays. This patch renames PnvPHB3.ioda* arrays to PnvPHB3.ioda2*. The reason why we're calling 'ioda2' is because PnvPHB3 uses IODA version 2. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb3.c | 18 +++++++++--------- include/hw/pci-host/pnv_phb3.h | 12 ++++++------ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 3f03467dde..860f8846df 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -165,7 +165,7 @@ static void pnv_phb3_check_m64(PnvPHB3 *phb, uint32_t index) } /* Get table entry */ - m64 = phb->ioda_M64BT[index]; + m64 = phb->ioda2_M64BT[index]; if (!(m64 & IODA2_M64BT_ENABLE)) { return; @@ -215,7 +215,7 @@ static void pnv_phb3_lxivt_write(PnvPHB3 *phb, unsigned idx, uint64_t val) { uint8_t server, prio; - phb->ioda_LXIVT[idx] = val & (IODA2_LXIVT_SERVER | + phb->ioda2_LXIVT[idx] = val & (IODA2_LXIVT_SERVER | IODA2_LXIVT_PRIORITY | IODA2_LXIVT_NODE_ID); server = GETFIELD(IODA2_LXIVT_SERVER, val); @@ -241,11 +241,11 @@ static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, switch (table) { case IODA2_TBL_LIST: - tptr = phb->ioda_LIST; + tptr = phb->ioda2_LIST; mask = 7; break; case IODA2_TBL_LXIVT: - tptr = phb->ioda_LXIVT; + tptr = phb->ioda2_LXIVT; mask = 7; break; case IODA2_TBL_IVC_CAM: @@ -263,7 +263,7 @@ static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, mask = 255; break; case IODA2_TBL_TVT: - tptr = phb->ioda_TVT; + tptr = phb->ioda2_TVT; mask = 511; break; case IODA2_TBL_TCAM: @@ -271,15 +271,15 @@ static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, mask = 63; break; case IODA2_TBL_M64BT: - tptr = phb->ioda_M64BT; + tptr = phb->ioda2_M64BT; mask = 15; break; case IODA2_TBL_M32DT: - tptr = phb->ioda_MDT; + tptr = phb->ioda2_MDT; mask = 255; break; case IODA2_TBL_PEEV: - tptr = phb->ioda_PEEV; + tptr = phb->ioda2_PEEV; mask = 3; break; default: @@ -869,7 +869,7 @@ static IOMMUTLBEntry pnv_phb3_translate_iommu(IOMMUMemoryRegion *iommu, } /* Choose TVE XXX Use PHB3 Control Register */ tve_sel = (addr >> 59) & 1; - tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel]; + tve = ds->phb->ioda2_TVT[ds->pe_num * 2 + tve_sel]; pnv_phb3_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret); break; case 01: diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index af6ec83cf6..73da31fbd2 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -141,12 +141,12 @@ struct PnvPHB3 { MemoryRegion pci_mmio; MemoryRegion pci_io; - uint64_t ioda_LIST[8]; - uint64_t ioda_LXIVT[8]; - uint64_t ioda_TVT[512]; - uint64_t ioda_M64BT[16]; - uint64_t ioda_MDT[256]; - uint64_t ioda_PEEV[4]; + uint64_t ioda2_LIST[8]; + uint64_t ioda2_LXIVT[8]; + uint64_t ioda2_TVT[512]; + uint64_t ioda2_M64BT[16]; + uint64_t ioda2_MDT[256]; + uint64_t ioda2_PEEV[4]; uint32_t total_irq; ICSState lsis; From patchwork Sat May 7 19:06:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A4D9C433F5 for ; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 02/17] ppc/pnv: rename PnvPHB3.regs[] to PnvPHB3.regs3[] Date: Sat, 7 May 2022 16:06:09 -0300 Message-Id: <20220507190624.507419-3-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Another redundancy between PnvPHB3 and PnvPHB4 that we should take care before merging all together in an unified model is the regs[] array. Rename the regs[] array used by the PHB3 code to 'regs3'. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb3.c | 54 +++++++++++++++++----------------- hw/pci-host/pnv_phb3_msi.c | 6 ++-- include/hw/pci-host/pnv_phb3.h | 4 +-- 3 files changed, 32 insertions(+), 32 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 860f8846df..77ee2325be 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -27,7 +27,7 @@ static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb) { PCIHostState *pci = PCI_HOST_BRIDGE(phb); - uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; + uint64_t addr = phb->regs3[PHB_CONFIG_ADDRESS >> 3]; uint8_t bus, devfn; if (!(addr >> 63)) { @@ -53,7 +53,7 @@ static void pnv_phb3_config_write(PnvPHB3 *phb, unsigned off, if (!pdev) { return; } - cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; + cfg_addr = (phb->regs3[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; cfg_addr |= off; limit = pci_config_size(pdev); if (limit <= cfg_addr) { @@ -89,7 +89,7 @@ static uint64_t pnv_phb3_config_read(PnvPHB3 *phb, unsigned off, if (!pdev) { return ~0ull; } - cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; + cfg_addr = (phb->regs3[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; cfg_addr |= off; limit = pci_config_size(pdev); if (limit <= cfg_addr) { @@ -122,14 +122,14 @@ static void pnv_phb3_check_m32(PnvPHB3 *phb) memory_region_del_subregion(phb->mr_m32.container, &phb->mr_m32); } - if (!(phb->regs[PHB_PHB3_CONFIG >> 3] & PHB_PHB3C_M32_EN)) { + if (!(phb->regs3[PHB_PHB3_CONFIG >> 3] & PHB_PHB3C_M32_EN)) { return; } /* Grab geometry from registers */ - base = phb->regs[PHB_M32_BASE_ADDR >> 3]; - start = phb->regs[PHB_M32_START_ADDR >> 3]; - size = ~(phb->regs[PHB_M32_BASE_MASK >> 3] | 0xfffc000000000000ull) + 1; + base = phb->regs3[PHB_M32_BASE_ADDR >> 3]; + start = phb->regs3[PHB_M32_START_ADDR >> 3]; + size = ~(phb->regs3[PHB_M32_BASE_MASK >> 3] | 0xfffc000000000000ull) + 1; /* Check if it matches an enabled MMIO region in the PBCQ */ if (memory_region_is_mapped(&pbcq->mmbar0) && @@ -179,7 +179,7 @@ static void pnv_phb3_check_m64(PnvPHB3 *phb, uint32_t index) size = GETFIELD(IODA2_M64BT_MASK, m64) << 20; size |= 0xfffc000000000000ull; size = ~size + 1; - start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]); + start = base | (phb->regs3[PHB_M64_UPPER_BITS >> 3]); /* Check if it matches an enabled MMIO region in the PBCQ */ if (memory_region_is_mapped(&pbcq->mmbar0) && @@ -233,7 +233,7 @@ static void pnv_phb3_lxivt_write(PnvPHB3 *phb, unsigned idx, uint64_t val) static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, unsigned *out_table, unsigned *out_idx) { - uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3]; + uint64_t adreg = phb->regs3[PHB_IODA_ADDR >> 3]; unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg); unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg); unsigned int mask; @@ -300,7 +300,7 @@ static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, index = (index + 1) & mask; adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index); } - phb->regs[PHB_IODA_ADDR >> 3] = adreg; + phb->regs3[PHB_IODA_ADDR >> 3] = adreg; return tptr; } @@ -364,7 +364,7 @@ void pnv_phb3_remap_irqs(PnvPHB3 *phb) } /* Grab local LSI source ID */ - local = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]) << 3; + local = GETFIELD(PHB_LSI_SRC_ID, phb->regs3[PHB_LSI_SOURCE_ID >> 3]) << 3; /* Grab global one and compare */ global = GETFIELD(PBCQ_NEST_LSI_SRC, @@ -412,7 +412,7 @@ static void pnv_phb3_lsi_src_id_write(PnvPHB3 *phb, uint64_t val) { /* Sanitize content */ val &= PHB_LSI_SRC_ID; - phb->regs[PHB_LSI_SOURCE_ID >> 3] = val; + phb->regs3[PHB_LSI_SOURCE_ID >> 3] = val; pnv_phb3_remap_irqs(phb); } @@ -429,7 +429,7 @@ static void pnv_phb3_rtc_invalidate(PnvPHB3 *phb, uint64_t val) static void pnv_phb3_update_msi_regions(PnvPhb3DMASpace *ds) { - uint64_t cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3]; + uint64_t cfg = ds->phb->regs3[PHB_PHB3_CONFIG >> 3]; if (cfg & PHB_PHB3C_32BIT_MSI_EN) { if (!memory_region_is_mapped(&ds->msi32_mr)) { @@ -501,16 +501,16 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) break; /* LEM stuff */ case PHB_LEM_FIR_AND_MASK: - phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val; + phb->regs3[PHB_LEM_FIR_ACCUM >> 3] &= val; return; case PHB_LEM_FIR_OR_MASK: - phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val; + phb->regs3[PHB_LEM_FIR_ACCUM >> 3] |= val; return; case PHB_LEM_ERROR_AND_MASK: - phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val; + phb->regs3[PHB_LEM_ERROR_MASK >> 3] &= val; return; case PHB_LEM_ERROR_OR_MASK: - phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val; + phb->regs3[PHB_LEM_ERROR_MASK >> 3] |= val; return; case PHB_LEM_WOF: val = 0; @@ -518,10 +518,10 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) } /* Record whether it changed */ - changed = phb->regs[off >> 3] != val; + changed = phb->regs3[off >> 3] != val; /* Store in register cache first */ - phb->regs[off >> 3] = val; + phb->regs3[off >> 3] = val; /* Handle side effects */ switch (off) { @@ -605,7 +605,7 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size) } /* Default read from cache */ - val = phb->regs[off >> 3]; + val = phb->regs3[off >> 3]; switch (off) { /* Simulate venice DD2.0 */ @@ -628,7 +628,7 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size) /* FFI Lock */ case PHB_FFI_LOCK: /* Set lock and return previous value */ - phb->regs[off >> 3] |= PHB_FFI_LOCK_STATE; + phb->regs3[off >> 3] |= PHB_FFI_LOCK_STATE; return val; /* DMA read sync: make it look like it's complete */ @@ -704,7 +704,7 @@ static bool pnv_phb3_resolve_pe(PnvPhb3DMASpace *ds) } /* We need to lookup the RTT */ - rtt = ds->phb->regs[PHB_RTT_BAR >> 3]; + rtt = ds->phb->regs3[PHB_RTT_BAR >> 3]; if (!(rtt & PHB_RTT_BAR_ENABLE)) { phb3_error(ds->phb, "DMA with RTT BAR disabled !"); /* Set error bits ? fence ? ... */ @@ -861,7 +861,7 @@ static IOMMUTLBEntry pnv_phb3_translate_iommu(IOMMUMemoryRegion *iommu, switch (addr >> 60) { case 00: /* DMA or 32-bit MSI ? */ - cfg = ds->phb->regs[PHB_PHB3_CONFIG >> 3]; + cfg = ds->phb->regs3[PHB_PHB3_CONFIG >> 3]; if ((cfg & PHB_PHB3C_32BIT_MSI_EN) && ((addr & 0xffffffffffff0000ull) == 0xffff0000ull)) { phb3_error(phb, "xlate on 32-bit MSI region"); @@ -1032,7 +1032,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) } /* Controller Registers */ - memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb, + memory_region_init_io(&phb->mr_regs3, OBJECT(phb), &pnv_phb3_reg_ops, phb, "phb3-regs", 0x1000); /* @@ -1060,14 +1060,14 @@ void pnv_phb3_update_regions(PnvPHB3 *phb) PnvPBCQState *pbcq = &phb->pbcq; /* Unmap first always */ - if (memory_region_is_mapped(&phb->mr_regs)) { - memory_region_del_subregion(&pbcq->phbbar, &phb->mr_regs); + if (memory_region_is_mapped(&phb->mr_regs3)) { + memory_region_del_subregion(&pbcq->phbbar, &phb->mr_regs3); } /* Map registers if enabled */ if (memory_region_is_mapped(&pbcq->phbbar)) { /* TODO: We should use the PHB BAR 2 register but we don't ... */ - memory_region_add_subregion(&pbcq->phbbar, 0, &phb->mr_regs); + memory_region_add_subregion(&pbcq->phbbar, 0, &phb->mr_regs3); } /* Check/update m32 */ diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index 2f4112907b..d8534376f8 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -20,8 +20,8 @@ static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno) { - uint64_t ivtbar = phb->regs[PHB_IVT_BAR >> 3]; - uint64_t phbctl = phb->regs[PHB_CONTROL >> 3]; + uint64_t ivtbar = phb->regs3[PHB_IVT_BAR >> 3]; + uint64_t phbctl = phb->regs3[PHB_CONTROL >> 3]; if (!(ivtbar & PHB_IVT_BAR_ENABLE)) { qemu_log_mask(LOG_GUEST_ERROR, "Failed access to disable IVT BAR !"); @@ -188,7 +188,7 @@ void pnv_phb3_msi_ffi(Phb3MsiState *msi, uint64_t val) pnv_phb3_msi_send(msi, val, 0, -1); /* Clear FFI lock */ - msi->phb->regs[PHB_FFI_LOCK >> 3] = 0; + msi->phb->regs3[PHB_FFI_LOCK >> 3] = 0; } static void phb3_msi_reject(ICSState *ics, uint32_t nr) diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index 73da31fbd2..486dbbefee 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -133,8 +133,8 @@ struct PnvPHB3 { uint32_t phb_id; char bus_path[8]; - uint64_t regs[PNV_PHB3_NUM_REGS]; - MemoryRegion mr_regs; + uint64_t regs3[PNV_PHB3_NUM_REGS]; + MemoryRegion mr_regs3; MemoryRegion mr_m32; MemoryRegion mr_m64[PNV_PHB3_NUM_M64]; From patchwork Sat May 7 19:06:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5A71C433EF for ; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 03/17] ppc/pnv: rename PnvPHB3.dma_spaces to PnvPHB3.v3_dma_spaces Date: Sat, 7 May 2022 16:06:10 -0300 Message-Id: <20220507190624.507419-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The last common attribute that has a different meaning/semantic between PnvPHB3 and PnvPHB4 devices is the 'dma_spaces' QLIST. Rename the PHB3 version to 'v3_dma_spaces'. The reason why we chose that instead of 'dma3_spaces' or similar is to avoid any misunderstanding about this being related to DMA version 3. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb3.c | 10 +++++----- include/hw/pci-host/pnv_phb3.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 77ee2325be..70d92edd94 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -421,7 +421,7 @@ static void pnv_phb3_rtc_invalidate(PnvPHB3 *phb, uint64_t val) PnvPhb3DMASpace *ds; /* Always invalidate all for now ... */ - QLIST_FOREACH(ds, &phb->dma_spaces, list) { + QLIST_FOREACH(ds, &phb->v3_dma_spaces, list) { ds->pe_num = PHB_INVALID_PE; } } @@ -460,7 +460,7 @@ static void pnv_phb3_update_all_msi_regions(PnvPHB3 *phb) { PnvPhb3DMASpace *ds; - QLIST_FOREACH(ds, &phb->dma_spaces, list) { + QLIST_FOREACH(ds, &phb->v3_dma_spaces, list) { pnv_phb3_update_msi_regions(ds); } } @@ -938,7 +938,7 @@ static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn) PnvPHB3 *phb = opaque; PnvPhb3DMASpace *ds; - QLIST_FOREACH(ds, &phb->dma_spaces, list) { + QLIST_FOREACH(ds, &phb->v3_dma_spaces, list) { if (ds->bus == bus && ds->devfn == devfn) { break; } @@ -961,7 +961,7 @@ static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn) ds, "msi64", 0x100000); pnv_phb3_update_msi_regions(ds); - QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list); + QLIST_INSERT_HEAD(&phb->v3_dma_spaces, ds, list); } return &ds->dma_as; } @@ -970,7 +970,7 @@ static void pnv_phb3_instance_init(Object *obj) { PnvPHB3 *phb = PNV_PHB3(obj); - QLIST_INIT(&phb->dma_spaces); + QLIST_INIT(&phb->v3_dma_spaces); /* LSI sources */ object_initialize_child(obj, "lsi", &phb->lsis, TYPE_ICS); diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index 486dbbefee..35483e59c3 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -155,7 +155,7 @@ struct PnvPHB3 { PnvPBCQState pbcq; - QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; + QLIST_HEAD(, PnvPhb3DMASpace) v3_dma_spaces; PnvChip *chip; }; From patchwork Sat May 7 19:06:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC7F7C433EF for ; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:41 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 04/17] ppc/pnv: add unified pnv-phb header Date: Sat, 7 May 2022 16:06:11 -0300 Message-Id: <20220507190624.507419-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch adds the pnv_phb.h header with the declarations we're going to use in this soon to be added device. It consists of an union between all attributes of PnvPHB3 and PnvPHB4 devices. This will allow for the same PnvPHB device to be used for PHB3 and PHB4 code. Some struct definitions from PnvPHB3 had to be moved to the new header due to scope constraints. Signed-off-by: Daniel Henrique Barboza --- include/hw/pci-host/pnv_phb.h | 211 +++++++++++++++++++++++++++++++++ include/hw/pci-host/pnv_phb3.h | 65 +--------- 2 files changed, 212 insertions(+), 64 deletions(-) create mode 100644 include/hw/pci-host/pnv_phb.h diff --git a/include/hw/pci-host/pnv_phb.h b/include/hw/pci-host/pnv_phb.h new file mode 100644 index 0000000000..2a8bf9a66d --- /dev/null +++ b/include/hw/pci-host/pnv_phb.h @@ -0,0 +1,211 @@ +/* + * QEMU PowerPC PowerNV Unified PHB model + * + * Copyright (c) 2022, IBM Corporation. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#ifndef PCI_HOST_PNV_PHB_H +#define PCI_HOST_PNV_PHB_H + +#include "hw/pci/pcie_host.h" +#include "hw/pci/pcie_port.h" +#include "hw/ppc/xics.h" +#include "hw/ppc/xive.h" +#include "qom/object.h" + +/* pnv_phb3.h types */ +#define PNV_PHB3_NUM_M64 16 +#define PNV_PHB3_NUM_REGS (0x1000 >> 3) +#define PHB3_MAX_MSI 2048 + +typedef struct PnvPHB3 PnvPHB3; +typedef struct PnvChip PnvChip; + +typedef struct Phb3MsiState { + ICSState ics; + qemu_irq *qirqs; + + PnvPHB3 *phb; + uint64_t rba[PHB3_MAX_MSI / 64]; + uint32_t rba_sum; +} Phb3MsiState; + +typedef struct PnvPBCQState { + DeviceState parent; + + uint32_t nest_xbase; + uint32_t spci_xbase; + uint32_t pci_xbase; +#define PBCQ_NEST_REGS_COUNT 0x46 +#define PBCQ_PCI_REGS_COUNT 0x15 +#define PBCQ_SPCI_REGS_COUNT 0x5 + + uint64_t nest_regs[PBCQ_NEST_REGS_COUNT]; + uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT]; + uint64_t pci_regs[PBCQ_PCI_REGS_COUNT]; + MemoryRegion mmbar0; + MemoryRegion mmbar1; + MemoryRegion phbbar; + uint64_t mmio0_base; + uint64_t mmio0_size; + uint64_t mmio1_base; + uint64_t mmio1_size; + PnvPHB3 *phb; + + MemoryRegion xscom_nest_regs; + MemoryRegion xscom_pci_regs; + MemoryRegion xscom_spci_regs; +} PnvPBCQState; + +/* + * We have one such address space wrapper per possible device under + * the PHB since they need to be assigned statically at qemu device + * creation time. The relationship to a PE is done later dynamically. + * This means we can potentially create a lot of these guys. Q35 + * stores them as some kind of radix tree but we never really need to + * do fast lookups so instead we simply keep a QLIST of them for now, + * we can add the radix if needed later on. + * + * We do cache the PE number to speed things up a bit though. + */ +typedef struct PnvPhb3DMASpace { + PCIBus *bus; + uint8_t devfn; + int pe_num; /* Cached PE number */ +#define PHB_INVALID_PE (-1) + PnvPHB3 *phb; + AddressSpace dma_as; + IOMMUMemoryRegion dma_mr; + MemoryRegion msi32_mr; + MemoryRegion msi64_mr; + QLIST_ENTRY(PnvPhb3DMASpace) list; +} PnvPhb3DMASpace; + +/* pnv_phb4.h types */ +#define PNV_PHB4_MAX_LSIs 8 +#define PNV_PHB4_MAX_INTs 4096 +#define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) +#define PNV_PHB4_MAX_MMIO_WINDOWS 32 +#define PNV_PHB4_MIN_MMIO_WINDOWS 16 +#define PNV_PHB4_NUM_REGS (0x3000 >> 3) +#define PNV_PHB4_MAX_PEs 512 +#define PNV_PHB4_MAX_TVEs (PNV_PHB4_MAX_PEs * 2) +#define PNV_PHB4_MAX_PEEVs (PNV_PHB4_MAX_PEs / 64) +#define PNV_PHB4_MAX_MBEs (PNV_PHB4_MAX_MMIO_WINDOWS * 2) +typedef struct PnvPhb4PecState PnvPhb4PecState; + +/* + * Unified PHB PCIe Host Bridge for PowerNV machines + */ +typedef struct PnvPHB PnvPHB; +#define TYPE_PNV_PHB "pnv-phb" +OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB, PNV_PHB) + +struct PnvPHB { + PCIExpressHost parent_obj; + + uint32_t chip_id; + uint32_t phb_id; + char bus_path[8]; + MemoryRegion pci_mmio; + MemoryRegion pci_io; + qemu_irq *qirqs; + + /* + * PnvPHB3 attributes + */ + uint64_t regs3[PNV_PHB3_NUM_REGS]; + MemoryRegion mr_regs3; + + MemoryRegion mr_m32; + MemoryRegion mr_m64[PNV_PHB3_NUM_M64]; + + uint64_t ioda2_LIST[8]; + uint64_t ioda2_LXIVT[8]; + uint64_t ioda2_TVT[512]; + uint64_t ioda2_M64BT[16]; + uint64_t ioda2_MDT[256]; + uint64_t ioda2_PEEV[4]; + + uint32_t total_irq; + ICSState lsis; + Phb3MsiState msis; + + PnvPBCQState pbcq; + + QLIST_HEAD(, PnvPhb3DMASpace) v3_dma_spaces; + + PnvChip *chip; + + /* + * PnvPHB4 attributes + */ + uint64_t version; + + /* The owner PEC */ + PnvPhb4PecState *pec; + + /* Main register images */ + uint64_t regs[PNV_PHB4_NUM_REGS]; + MemoryRegion mr_regs; + + /* Extra SCOM-only register */ + uint64_t scom_hv_ind_addr_reg; + + /* + * Geometry of the PHB. There are two types, small and big PHBs, a + * number of resources (number of PEs, windows etc...) are doubled + * for a big PHB + */ + bool big_phb; + + /* Memory regions for MMIO space */ + MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS]; + + /* PCI registers (excluding pass-through) */ +#define PHB4_PEC_PCI_STK_REGS_COUNT 0xf + uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; + MemoryRegion pci_regs_mr; + + /* Nest registers */ +#define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 + uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; + MemoryRegion nest_regs_mr; + + /* PHB pass-through XSCOM */ + MemoryRegion phb_regs_mr; + + /* Memory windows from PowerBus to PHB */ + MemoryRegion phbbar; + MemoryRegion intbar; + MemoryRegion mmbar0; + MemoryRegion mmbar1; + uint64_t mmio0_base; + uint64_t mmio0_size; + uint64_t mmio1_base; + uint64_t mmio1_size; + + /* On-chip IODA tables */ + uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; + uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; + uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; + uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; + uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; + uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs]; + + /* + * The internal PESTA/B is 2 bits per PE split into two tables, we + * store them in a single array here to avoid wasting space. + */ + uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs]; + + /* P9 Interrupt generation */ + XiveSource xsrc; + + QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; +}; + +#endif /* PCI_HOST_PNV_PHB_H */ diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index 35483e59c3..b6b5f91684 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -12,6 +12,7 @@ #include "hw/pci/pcie_host.h" #include "hw/pci/pcie_port.h" +#include "hw/pci-host/pnv_phb.h" #include "hw/ppc/xics.h" #include "qom/object.h" @@ -22,21 +23,9 @@ typedef struct PnvChip PnvChip; * PHB3 XICS Source for MSIs */ #define TYPE_PHB3_MSI "phb3-msi" -typedef struct Phb3MsiState Phb3MsiState; DECLARE_INSTANCE_CHECKER(Phb3MsiState, PHB3_MSI, TYPE_PHB3_MSI) -#define PHB3_MAX_MSI 2048 - -struct Phb3MsiState { - ICSState ics; - qemu_irq *qirqs; - - PnvPHB3 *phb; - uint64_t rba[PHB3_MAX_MSI / 64]; - uint32_t rba_sum; -}; - void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base, uint32_t count); void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data, @@ -44,64 +33,12 @@ void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data, void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val); void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon); - -/* - * We have one such address space wrapper per possible device under - * the PHB since they need to be assigned statically at qemu device - * creation time. The relationship to a PE is done later dynamically. - * This means we can potentially create a lot of these guys. Q35 - * stores them as some kind of radix tree but we never really need to - * do fast lookups so instead we simply keep a QLIST of them for now, - * we can add the radix if needed later on. - * - * We do cache the PE number to speed things up a bit though. - */ -typedef struct PnvPhb3DMASpace { - PCIBus *bus; - uint8_t devfn; - int pe_num; /* Cached PE number */ -#define PHB_INVALID_PE (-1) - PnvPHB3 *phb; - AddressSpace dma_as; - IOMMUMemoryRegion dma_mr; - MemoryRegion msi32_mr; - MemoryRegion msi64_mr; - QLIST_ENTRY(PnvPhb3DMASpace) list; -} PnvPhb3DMASpace; - /* * PHB3 Power Bus Common Queue */ #define TYPE_PNV_PBCQ "pnv-pbcq" OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ) -struct PnvPBCQState { - DeviceState parent; - - uint32_t nest_xbase; - uint32_t spci_xbase; - uint32_t pci_xbase; -#define PBCQ_NEST_REGS_COUNT 0x46 -#define PBCQ_PCI_REGS_COUNT 0x15 -#define PBCQ_SPCI_REGS_COUNT 0x5 - - uint64_t nest_regs[PBCQ_NEST_REGS_COUNT]; - uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT]; - uint64_t pci_regs[PBCQ_PCI_REGS_COUNT]; - MemoryRegion mmbar0; - MemoryRegion mmbar1; - MemoryRegion phbbar; - uint64_t mmio0_base; - uint64_t mmio0_size; - uint64_t mmio1_base; - uint64_t mmio1_size; - PnvPHB3 *phb; - - MemoryRegion xscom_nest_regs; - MemoryRegion xscom_pci_regs; - MemoryRegion xscom_spci_regs; -}; - /* * PHB3 PCIe Root port */ From patchwork Sat May 7 19:06:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 032F3C433EF for ; Sat, 7 May 2022 19:12:25 +0000 (UTC) Received: from localhost ([::1]:40408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPqq-0005LP-Ok for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:12:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPlP-00059O-EL; Sat, 07 May 2022 15:06:47 -0400 Received: from mail-oo1-xc31.google.com ([2607:f8b0:4864:20::c31]:44598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nnPlN-0001YN-LO; Sat, 07 May 2022 15:06:47 -0400 Received: by mail-oo1-xc31.google.com with SMTP id o10-20020a4abe8a000000b0035eac0a004aso1831427oop.11; Sat, 07 May 2022 12:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dpaTjFiYrghI3JitsDctayMbtGiCYEaddztQT51dquM=; b=fNVECFjzwy50cehAI/MVQ0ERPNUt5DVwEWOtTWevHGEYQJWZfEupf6rpJGVuULOu9t 4wlcVyEToTlrNFu25nXLXMMxIFPUkuAs37DSSicusLKD8kiWMWzbAdFV+Fu6eScOUnaR brN6FuXgJEUwlBkAycHsjjj8rFKKxASzvuyGF60OTWWvUVW056bQkrBqpOvrhkJgHN0o 2aINRcLpgAOarPXnDYZFbViLPjuxGV2G1InKXOz3PlzDczjiDCFqcOU8lkv8Whci78NR 1M8tFox/cNcPmH+sXxC0lBi1Hk/xlrn4bQCv128AWuZi02b77mt6mYthOOpfeWlbaWIQ f9tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dpaTjFiYrghI3JitsDctayMbtGiCYEaddztQT51dquM=; b=WQyvLxMLxN2o1H3QHe3l1ID4t3K+WNei0krAFdwaSWqa3bfDqdgdCCj5YrHc7hT4yU Jq0QKMYWF8Mjgrtw+EdlNmGwYPNyOAWmzqogck3rp3z2LDKJg5/Y3xHYEySjX6vn9TKp n8DPWp6oXYUjfswp/pgfdsFIXMSotcZTYxRvHmi4Wr9jfh6HxszgNLZYe2RHI5Dtvx/o +b19z+dwsfR7K0OitOQTXEILVL+ORuDTqcvJiNydg9OpaMRuR+ibLTnbEKU9yxzBhY8I Q2Badpi0N8yxxjGO0YKp7IdtNqiiW5pdCtdEczkXgLP9fqXBMpDrYdK2j21J9WBebQsi 6FWQ== X-Gm-Message-State: AOAM530CWnBFbh8dWjcclKj6NqlHBQjM4l0gKChQp0h30n+QZhH7ARdv 8l8y5s3YOsk5CFksrLnuMi3QQrC/CwQ= X-Google-Smtp-Source: ABdhPJyJnH5XfOyx8DUxXZE3Ndr/TFL8+u33MxQA6A4d0t/Q9CG7aLoSwmUxrNLrL4MaxjKHT+ZFzA== X-Received: by 2002:a05:6820:1517:b0:35f:5a69:8cc0 with SMTP id ay23-20020a056820151700b0035f5a698cc0mr2498903oob.72.1651950404196; Sat, 07 May 2022 12:06:44 -0700 (PDT) Received: from balboa.ibmmodules.com (201-1-57-208.dsl.telesp.net.br. [201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:43 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 05/17] ppc/pnv: add pnv-phb device Date: Sat, 7 May 2022 16:06:12 -0300 Message-Id: <20220507190624.507419-6-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=danielhb413@gmail.com; helo=mail-oo1-xc31.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This device works as a generic pnv-phb that redirects the control flow to one of the implemented PHB versions (PHB3 and PHB4 at this moment). The control redirection happens in the instance_init() and realize() callbacks, where we check which powernv machine we're running and execute the PnvPHB3 callbacks if running powernv8 or PnvPHB4 if running powernv9/10. This will allow us to keep the existing PHB3 and PHB4 code as is, just changing their device type to PnvPHB3/PnvPHB4 to PnvPHB when we're ready. For now we're putting logic to handle the PHB3 version. We'll add PHB4 later on. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/meson.build | 3 +- hw/pci-host/pnv_phb.c | 116 +++++++++++++++++++++++++++++++++ hw/pci-host/pnv_phb3.c | 4 +- include/hw/pci-host/pnv_phb3.h | 3 + 4 files changed, 123 insertions(+), 3 deletions(-) create mode 100644 hw/pci-host/pnv_phb.c diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index 4c4f39c15c..b4107b7a2a 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -32,5 +32,6 @@ specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files( 'pnv_phb3_msi.c', 'pnv_phb3_pbcq.c', 'pnv_phb4.c', - 'pnv_phb4_pec.c' + 'pnv_phb4_pec.c', + 'pnv_phb.c', )) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c new file mode 100644 index 0000000000..3dd08f768f --- /dev/null +++ b/hw/pci-host/pnv_phb.c @@ -0,0 +1,116 @@ +/* + * QEMU PowerPC PowerNV Unified PHB model + * + * Copyright (c) 2022, IBM Corporation. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/visitor.h" +#include "qapi/error.h" +#include "hw/pci-host/pnv_phb.h" +#include "hw/pci/pcie_host.h" +#include "hw/pci/pcie_port.h" +#include "hw/ppc/pnv.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "qom/object.h" +#include "sysemu/sysemu.h" + + +static char *pnv_phb_get_chip_typename(void) +{ + Object *qdev_machine = qdev_get_machine(); + PnvMachineState *pnv = PNV_MACHINE(qdev_machine); + MachineState *machine = MACHINE(pnv); + g_autofree char *chip_typename = NULL; + int i; + + if (!machine->cpu_type) { + return NULL; + } + + i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); + chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), + i, machine->cpu_type); + + return g_steal_pointer(&chip_typename); +} + +static void pnv_phb_instance_init(Object *obj) +{ + g_autofree char *chip_typename = pnv_phb_get_chip_typename(); + + /* + * When doing command line instrospection we won't have + * a valid machine->cpu_type value. + */ + if (!chip_typename) { + return; + } + + if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER8) || + !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8E) || + !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8NVL)) { + pnv_phb3_instance_init(obj); + } +} + +static void pnv_phb_realize(DeviceState *dev, Error **errp) +{ + g_autofree char *chip_typename = pnv_phb_get_chip_typename(); + + g_assert(chip_typename != NULL); + + if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER8) || + !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8E) || + !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8NVL)) { + /* PnvPHB3 */ + pnv_phb3_realize(dev, errp); + } +} + +static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, + PCIBus *rootbus) +{ + PnvPHB *phb = PNV_PHB(host_bridge); + + snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", + phb->chip_id, phb->phb_id); + return phb->bus_path; +} + +static Property pnv_phb_properties[] = { + DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), + DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_phb_class_init(ObjectClass *klass, void *data) +{ + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + hc->root_bus_path = pnv_phb_root_bus_path; + dc->realize = pnv_phb_realize; + device_class_set_props(dc, pnv_phb_properties); + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->user_creatable = true; +} + +static const TypeInfo pnv_phb_type_info = { + .name = TYPE_PNV_PHB, + .parent = TYPE_PCIE_HOST_BRIDGE, + .instance_size = sizeof(PnvPHB), + .class_init = pnv_phb_class_init, + .instance_init = pnv_phb_instance_init, +}; + +static void pnv_phb_register_types(void) +{ + type_register_static(&pnv_phb_type_info); +} + +type_init(pnv_phb_register_types) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 70d92edd94..8e31a69083 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -966,7 +966,7 @@ static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn) return &ds->dma_as; } -static void pnv_phb3_instance_init(Object *obj) +void pnv_phb3_instance_init(Object *obj) { PnvPHB3 *phb = PNV_PHB3(obj); @@ -986,7 +986,7 @@ static void pnv_phb3_instance_init(Object *obj) } -static void pnv_phb3_realize(DeviceState *dev, Error **errp) +void pnv_phb3_realize(DeviceState *dev, Error **errp) { PnvPHB3 *phb = PNV_PHB3(dev); PCIHostState *pci = PCI_HOST_BRIDGE(dev); diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index b6b5f91684..aba26f4f7c 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -102,4 +102,7 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size); void pnv_phb3_update_regions(PnvPHB3 *phb); void pnv_phb3_remap_irqs(PnvPHB3 *phb); +void pnv_phb3_instance_init(Object *obj); +void pnv_phb3_realize(DeviceState *dev, Error **errp); + #endif /* PCI_HOST_PNV_PHB3_H */ From patchwork Sat May 7 19:06:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7801C433EF for ; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 06/17] ppc/pnv: remove PnvPHB3 Date: Sat, 7 May 2022 16:06:13 -0300 Message-Id: <20220507190624.507419-7-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The unified PnvPHB model is able to replace PnvPHB3 in all PHB3 related code. Let's do that while also removing the PnvPHB3 device entirely. The device wasn't user creatable in any QEMU release so there's no ABI concerns in doing so. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb.c | 1 + hw/pci-host/pnv_phb3.c | 92 ++++++++++------------------------ hw/pci-host/pnv_phb3_msi.c | 6 +-- hw/pci-host/pnv_phb3_pbcq.c | 8 +-- hw/ppc/pnv.c | 12 ++--- include/hw/pci-host/pnv_phb.h | 9 ++-- include/hw/pci-host/pnv_phb3.h | 43 +--------------- include/hw/ppc/pnv.h | 2 +- 8 files changed, 48 insertions(+), 125 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 3dd08f768f..e4c4cca311 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -85,6 +85,7 @@ static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, static Property pnv_phb_properties[] = { DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), + DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 8e31a69083..d2405d4f5a 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -24,7 +24,7 @@ qemu_log_mask(LOG_GUEST_ERROR, "phb3[%d:%d]: " fmt "\n", \ (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__) -static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb) +static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB *phb) { PCIHostState *pci = PCI_HOST_BRIDGE(phb); uint64_t addr = phb->regs3[PHB_CONFIG_ADDRESS >> 3]; @@ -43,7 +43,7 @@ static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb) * The CONFIG_DATA register expects little endian accesses, but as the * region is big endian, we have to swap the value. */ -static void pnv_phb3_config_write(PnvPHB3 *phb, unsigned off, +static void pnv_phb3_config_write(PnvPHB *phb, unsigned off, unsigned size, uint64_t val) { uint32_t cfg_addr, limit; @@ -78,7 +78,7 @@ static void pnv_phb3_config_write(PnvPHB3 *phb, unsigned off, pci_host_config_write_common(pdev, cfg_addr, limit, val, size); } -static uint64_t pnv_phb3_config_read(PnvPHB3 *phb, unsigned off, +static uint64_t pnv_phb3_config_read(PnvPHB *phb, unsigned off, unsigned size) { uint32_t cfg_addr, limit; @@ -112,7 +112,7 @@ static uint64_t pnv_phb3_config_read(PnvPHB3 *phb, unsigned off, } } -static void pnv_phb3_check_m32(PnvPHB3 *phb) +static void pnv_phb3_check_m32(PnvPHB *phb) { uint64_t base, start, size; MemoryRegion *parent; @@ -152,7 +152,7 @@ static void pnv_phb3_check_m32(PnvPHB3 *phb) memory_region_add_subregion(parent, base, &phb->mr_m32); } -static void pnv_phb3_check_m64(PnvPHB3 *phb, uint32_t index) +static void pnv_phb3_check_m64(PnvPHB *phb, uint32_t index) { uint64_t base, start, size, m64; MemoryRegion *parent; @@ -202,7 +202,7 @@ static void pnv_phb3_check_m64(PnvPHB3 *phb, uint32_t index) memory_region_add_subregion(parent, base, &phb->mr_m64[index]); } -static void pnv_phb3_check_all_m64s(PnvPHB3 *phb) +static void pnv_phb3_check_all_m64s(PnvPHB *phb) { uint64_t i; @@ -211,7 +211,7 @@ static void pnv_phb3_check_all_m64s(PnvPHB3 *phb) } } -static void pnv_phb3_lxivt_write(PnvPHB3 *phb, unsigned idx, uint64_t val) +static void pnv_phb3_lxivt_write(PnvPHB *phb, unsigned idx, uint64_t val) { uint8_t server, prio; @@ -230,7 +230,7 @@ static void pnv_phb3_lxivt_write(PnvPHB3 *phb, unsigned idx, uint64_t val) ics_write_xive(&phb->lsis, idx, server, prio, prio); } -static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, +static uint64_t *pnv_phb3_ioda_access(PnvPHB *phb, unsigned *out_table, unsigned *out_idx) { uint64_t adreg = phb->regs3[PHB_IODA_ADDR >> 3]; @@ -304,7 +304,7 @@ static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb, return tptr; } -static uint64_t pnv_phb3_ioda_read(PnvPHB3 *phb) +static uint64_t pnv_phb3_ioda_read(PnvPHB *phb) { unsigned table; uint64_t *tptr; @@ -317,7 +317,7 @@ static uint64_t pnv_phb3_ioda_read(PnvPHB3 *phb) return *tptr; } -static void pnv_phb3_ioda_write(PnvPHB3 *phb, uint64_t val) +static void pnv_phb3_ioda_write(PnvPHB *phb, uint64_t val) { unsigned table, idx; uint64_t *tptr; @@ -345,7 +345,7 @@ static void pnv_phb3_ioda_write(PnvPHB3 *phb, uint64_t val) * This is called whenever the PHB LSI, MSI source ID register or * the PBCQ irq filters are written. */ -void pnv_phb3_remap_irqs(PnvPHB3 *phb) +void pnv_phb3_remap_irqs(PnvPHB *phb) { ICSState *ics = &phb->lsis; uint32_t local, global, count, mask, comp; @@ -408,7 +408,7 @@ void pnv_phb3_remap_irqs(PnvPHB3 *phb) pnv_phb3_msi_update_config(&phb->msis, comp, count - PNV_PHB3_NUM_LSI); } -static void pnv_phb3_lsi_src_id_write(PnvPHB3 *phb, uint64_t val) +static void pnv_phb3_lsi_src_id_write(PnvPHB *phb, uint64_t val) { /* Sanitize content */ val &= PHB_LSI_SRC_ID; @@ -416,7 +416,7 @@ static void pnv_phb3_lsi_src_id_write(PnvPHB3 *phb, uint64_t val) pnv_phb3_remap_irqs(phb); } -static void pnv_phb3_rtc_invalidate(PnvPHB3 *phb, uint64_t val) +static void pnv_phb3_rtc_invalidate(PnvPHB *phb, uint64_t val) { PnvPhb3DMASpace *ds; @@ -456,7 +456,7 @@ static void pnv_phb3_update_msi_regions(PnvPhb3DMASpace *ds) } } -static void pnv_phb3_update_all_msi_regions(PnvPHB3 *phb) +static void pnv_phb3_update_all_msi_regions(PnvPHB *phb) { PnvPhb3DMASpace *ds; @@ -467,7 +467,7 @@ static void pnv_phb3_update_all_msi_regions(PnvPHB3 *phb) void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) { - PnvPHB3 *phb = opaque; + PnvPHB *phb = opaque; bool changed; /* Special case configuration data */ @@ -589,7 +589,7 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size) { - PnvPHB3 *phb = opaque; + PnvPHB *phb = opaque; PCIHostState *pci = PCI_HOST_BRIDGE(phb); uint64_t val; @@ -683,7 +683,7 @@ static int pnv_phb3_map_irq(PCIDevice *pci_dev, int irq_num) static void pnv_phb3_set_irq(void *opaque, int irq_num, int level) { - PnvPHB3 *phb = opaque; + PnvPHB *phb = opaque; /* LSI only ... */ if (irq_num > 3) { @@ -741,7 +741,7 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds, hwaddr addr, int32_t lev = GETFIELD(IODA2_TVT_NUM_LEVELS, tve); uint32_t tts = GETFIELD(IODA2_TVT_TCE_TABLE_SIZE, tve); uint32_t tps = GETFIELD(IODA2_TVT_IO_PSIZE, tve); - PnvPHB3 *phb = ds->phb; + PnvPHB *phb = ds->phb; /* Invalid levels */ if (lev > 4) { @@ -848,7 +848,7 @@ static IOMMUTLBEntry pnv_phb3_translate_iommu(IOMMUMemoryRegion *iommu, .addr_mask = ~(hwaddr)0, .perm = IOMMU_NONE, }; - PnvPHB3 *phb = ds->phb; + PnvPHB *phb = ds->phb; /* Resolve PE# */ if (!pnv_phb3_resolve_pe(ds)) { @@ -935,7 +935,7 @@ static const MemoryRegionOps pnv_phb3_msi_ops = { static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn) { - PnvPHB3 *phb = opaque; + PnvPHB *phb = opaque; PnvPhb3DMASpace *ds; QLIST_FOREACH(ds, &phb->v3_dma_spaces, list) { @@ -968,7 +968,7 @@ static AddressSpace *pnv_phb3_dma_iommu(PCIBus *bus, void *opaque, int devfn) void pnv_phb3_instance_init(Object *obj) { - PnvPHB3 *phb = PNV_PHB3(obj); + PnvPHB *phb = PNV_PHB(obj); QLIST_INIT(&phb->v3_dma_spaces); @@ -988,7 +988,7 @@ void pnv_phb3_instance_init(Object *obj) void pnv_phb3_realize(DeviceState *dev, Error **errp) { - PnvPHB3 *phb = PNV_PHB3(dev); + PnvPHB *phb = PNV_PHB(dev); PCIHostState *pci = PCI_HOST_BRIDGE(dev); PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; @@ -1055,7 +1055,7 @@ void pnv_phb3_realize(DeviceState *dev, Error **errp) pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), TYPE_PNV_PHB3_ROOT_PORT); } -void pnv_phb3_update_regions(PnvPHB3 *phb) +void pnv_phb3_update_regions(PnvPHB *phb) { PnvPBCQState *pbcq = &phb->pbcq; @@ -1077,43 +1077,6 @@ void pnv_phb3_update_regions(PnvPHB3 *phb) pnv_phb3_check_all_m64s(phb); } -static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, - PCIBus *rootbus) -{ - PnvPHB3 *phb = PNV_PHB3(host_bridge); - - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", - phb->chip_id, phb->phb_id); - return phb->bus_path; -} - -static Property pnv_phb3_properties[] = { - DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), - DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), - DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_END_OF_LIST(), -}; - -static void pnv_phb3_class_init(ObjectClass *klass, void *data) -{ - PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); - DeviceClass *dc = DEVICE_CLASS(klass); - - hc->root_bus_path = pnv_phb3_root_bus_path; - dc->realize = pnv_phb3_realize; - device_class_set_props(dc, pnv_phb3_properties); - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable = false; -} - -static const TypeInfo pnv_phb3_type_info = { - .name = TYPE_PNV_PHB3, - .parent = TYPE_PCIE_HOST_BRIDGE, - .instance_size = sizeof(PnvPHB3), - .class_init = pnv_phb3_class_init, - .instance_init = pnv_phb3_instance_init, -}; - static void pnv_phb3_root_bus_class_init(ObjectClass *klass, void *data) { BusClass *k = BUS_CLASS(klass); @@ -1140,15 +1103,15 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp) PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); PCIDevice *pci = PCI_DEVICE(dev); PCIBus *bus = pci_get_bus(pci); - PnvPHB3 *phb = NULL; + PnvPHB *phb = NULL; Error *local_err = NULL; - phb = (PnvPHB3 *) object_dynamic_cast(OBJECT(bus->qbus.parent), - TYPE_PNV_PHB3); + phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB); if (!phb) { error_setg(errp, -"pnv_phb3_root_port devices must be connected to pnv-phb3 buses"); +"pnv_phb3_root_port devices must be connected to pnv-phb buses"); return; } @@ -1195,7 +1158,6 @@ static void pnv_phb3_register_types(void) { type_register_static(&pnv_phb3_root_bus_info); type_register_static(&pnv_phb3_root_port_info); - type_register_static(&pnv_phb3_type_info); type_register_static(&pnv_phb3_iommu_memory_region_info); } diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index d8534376f8..84475f8dc1 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -18,7 +18,7 @@ #include "hw/qdev-properties.h" #include "sysemu/reset.h" -static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno) +static uint64_t phb3_msi_ive_addr(PnvPHB *phb, int srcno) { uint64_t ivtbar = phb->regs3[PHB_IVT_BAR >> 3]; uint64_t phbctl = phb->regs3[PHB_CONTROL >> 3]; @@ -43,7 +43,7 @@ static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno) } } -static bool phb3_msi_read_ive(PnvPHB3 *phb, int srcno, uint64_t *out_ive) +static bool phb3_msi_read_ive(PnvPHB *phb, int srcno, uint64_t *out_ive) { uint64_t ive_addr, ive; @@ -281,7 +281,7 @@ static void phb3_msi_instance_init(Object *obj) Phb3MsiState *msi = PHB3_MSI(obj); ICSState *ics = ICS(obj); - object_property_add_link(obj, "phb", TYPE_PNV_PHB3, + object_property_add_link(obj, "phb", TYPE_PNV_PHB, (Object **)&msi->phb, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c index 82f70efa43..39f02c158f 100644 --- a/hw/pci-host/pnv_phb3_pbcq.c +++ b/hw/pci-host/pnv_phb3_pbcq.c @@ -238,7 +238,7 @@ static const MemoryRegionOps pnv_pbcq_spci_xscom_ops = { static void pnv_pbcq_default_bars(PnvPBCQState *pbcq) { uint64_t mm0, mm1, reg; - PnvPHB3 *phb = pbcq->phb; + PnvPHB *phb = pbcq->phb; mm0 = 0x3d00000000000ull + 0x4000000000ull * phb->chip_id + 0x1000000000ull * phb->phb_id; @@ -258,7 +258,7 @@ static void pnv_pbcq_default_bars(PnvPBCQState *pbcq) static void pnv_pbcq_realize(DeviceState *dev, Error **errp) { PnvPBCQState *pbcq = PNV_PBCQ(dev); - PnvPHB3 *phb; + PnvPHB *phb; char name[32]; assert(pbcq->phb); @@ -300,7 +300,7 @@ static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) { const char compat[] = "ibm,power8-pbcq"; - PnvPHB3 *phb = PNV_PBCQ(dev)->phb; + PnvPHB *phb = PNV_PBCQ(dev)->phb; char *name; int offset; uint32_t lpc_pcba = PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id; @@ -331,7 +331,7 @@ static void phb3_pbcq_instance_init(Object *obj) { PnvPBCQState *pbcq = PNV_PBCQ(obj); - object_property_add_link(obj, "phb", TYPE_PNV_PHB3, + object_property_add_link(obj, "phb", TYPE_PNV_PHB, (Object **)&pbcq->phb, object_property_allow_set_link, OBJ_PROP_LINK_STRONG); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7c08a78d6c..12a3fe4920 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -655,7 +655,7 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) { Monitor *mon = opaque; - PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + PnvPHB *phb3 = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); if (phb3) { pnv_phb3_msi_pic_print_info(&phb3->msis, mon); @@ -1155,7 +1155,7 @@ static void pnv_chip_power8_instance_init(Object *obj) chip8->num_phbs = pcc->num_phbs; for (i = 0; i < chip8->num_phbs; i++) { - object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); + object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB); } } @@ -1277,9 +1277,9 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), &chip8->homer.regs); - /* PHB3 controllers */ + /* PHB version 3 controllers */ for (i = 0; i < chip8->num_phbs; i++) { - PnvPHB3 *phb = &chip8->phbs[i]; + PnvPHB *phb = &chip8->phbs[i]; object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, @@ -1942,7 +1942,7 @@ typedef struct ForeachPhb3Args { static int pnv_ics_get_child(Object *child, void *opaque) { ForeachPhb3Args *args = opaque; - PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + PnvPHB *phb3 = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); if (phb3) { if (ics_valid_irq(&phb3->lsis, args->irq)) { @@ -1992,7 +1992,7 @@ PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) static int pnv_ics_resend_child(Object *child, void *opaque) { - PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + PnvPHB *phb3 = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); if (phb3) { ics_resend(&phb3->lsis); diff --git a/include/hw/pci-host/pnv_phb.h b/include/hw/pci-host/pnv_phb.h index 2a8bf9a66d..46158e124f 100644 --- a/include/hw/pci-host/pnv_phb.h +++ b/include/hw/pci-host/pnv_phb.h @@ -21,14 +21,14 @@ #define PNV_PHB3_NUM_REGS (0x1000 >> 3) #define PHB3_MAX_MSI 2048 -typedef struct PnvPHB3 PnvPHB3; typedef struct PnvChip PnvChip; +typedef struct PnvPHB PnvPHB; typedef struct Phb3MsiState { ICSState ics; qemu_irq *qirqs; - PnvPHB3 *phb; + PnvPHB *phb; uint64_t rba[PHB3_MAX_MSI / 64]; uint32_t rba_sum; } Phb3MsiState; @@ -53,7 +53,7 @@ typedef struct PnvPBCQState { uint64_t mmio0_size; uint64_t mmio1_base; uint64_t mmio1_size; - PnvPHB3 *phb; + PnvPHB *phb; MemoryRegion xscom_nest_regs; MemoryRegion xscom_pci_regs; @@ -76,7 +76,7 @@ typedef struct PnvPhb3DMASpace { uint8_t devfn; int pe_num; /* Cached PE number */ #define PHB_INVALID_PE (-1) - PnvPHB3 *phb; + PnvPHB *phb; AddressSpace dma_as; IOMMUMemoryRegion dma_mr; MemoryRegion msi32_mr; @@ -100,7 +100,6 @@ typedef struct PnvPhb4PecState PnvPhb4PecState; /* * Unified PHB PCIe Host Bridge for PowerNV machines */ -typedef struct PnvPHB PnvPHB; #define TYPE_PNV_PHB "pnv-phb" OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB, PNV_PHB) diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index aba26f4f7c..1c4af98fee 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -16,7 +16,6 @@ #include "hw/ppc/xics.h" #include "qom/object.h" -typedef struct PnvPHB3 PnvPHB3; typedef struct PnvChip PnvChip; /* @@ -50,11 +49,6 @@ typedef struct PnvPHB3RootPort { PCIESlot parent_obj; } PnvPHB3RootPort; -/* - * PHB3 PCIe Host Bridge for PowerNV machines (POWER8) - */ -#define TYPE_PNV_PHB3 "pnv-phb3" -OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3) #define PNV_PHB3_NUM_M64 16 #define PNV_PHB3_NUM_REGS (0x1000 >> 3) @@ -63,44 +57,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3) #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) -struct PnvPHB3 { - PCIExpressHost parent_obj; - - uint32_t chip_id; - uint32_t phb_id; - char bus_path[8]; - - uint64_t regs3[PNV_PHB3_NUM_REGS]; - MemoryRegion mr_regs3; - - MemoryRegion mr_m32; - MemoryRegion mr_m64[PNV_PHB3_NUM_M64]; - MemoryRegion pci_mmio; - MemoryRegion pci_io; - - uint64_t ioda2_LIST[8]; - uint64_t ioda2_LXIVT[8]; - uint64_t ioda2_TVT[512]; - uint64_t ioda2_M64BT[16]; - uint64_t ioda2_MDT[256]; - uint64_t ioda2_PEEV[4]; - - uint32_t total_irq; - ICSState lsis; - qemu_irq *qirqs; - Phb3MsiState msis; - - PnvPBCQState pbcq; - - QLIST_HEAD(, PnvPhb3DMASpace) v3_dma_spaces; - - PnvChip *chip; -}; uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size); -void pnv_phb3_update_regions(PnvPHB3 *phb); -void pnv_phb3_remap_irqs(PnvPHB3 *phb); +void pnv_phb3_update_regions(PnvPHB *phb); +void pnv_phb3_remap_irqs(PnvPHB *phb); void pnv_phb3_instance_init(Object *obj); void pnv_phb3_realize(DeviceState *dev, Error **errp); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 86cb7d7f97..539454fe9d 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -80,7 +80,7 @@ struct Pnv8Chip { PnvHomer homer; #define PNV8_CHIP_PHB3_MAX 4 - PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; + PnvPHB phbs[PNV8_CHIP_PHB3_MAX]; uint32_t num_phbs; XICSFabric *xics; From patchwork Sat May 7 19:06:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C488CC433EF for ; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:49 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 07/17] ppc/pnv: user created pnv-phb for powernv8 Date: Sat, 7 May 2022 16:06:14 -0300 Message-Id: <20220507190624.507419-8-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch reintroduces the powernv8 bits of the code what was removed in commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices", using the pnv-phb device instead of the now late pnv-phb3 device, allowing us to enable user creatable pnv-phb devices for the powernv8 machine. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb3.c | 31 +++++++++++++++++++++++++++++-- hw/ppc/pnv.c | 23 ++++++++++++++++++++++- include/hw/ppc/pnv.h | 1 + 3 files changed, 52 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index d2405d4f5a..a6d6a10c52 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -993,6 +993,30 @@ void pnv_phb3_realize(DeviceState *dev, Error **errp) PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; + /* User created devices */ + if (!phb->chip) { + Error *local_err = NULL; + BusState *s; + + phb->chip = pnv_get_chip(pnv, phb->chip_id); + if (!phb->chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + + /* + * Reparent user created devices to the chip to build + * correctly the device tree. + */ + pnv_chip_parent_fixup(phb->chip, OBJECT(phb), phb->phb_id); + + s = qdev_get_parent_bus(DEVICE(phb->chip)); + if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { + error_propagate(errp, local_err); + return; + } + } + if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { error_setg(errp, "invalid PHB index: %d", phb->phb_id); return; @@ -1052,7 +1076,10 @@ void pnv_phb3_realize(DeviceState *dev, Error **errp) pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb); - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), TYPE_PNV_PHB3_ROOT_PORT); + if (defaults_enabled()) { + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), + TYPE_PNV_PHB3_ROOT_PORT); + } } void pnv_phb3_update_regions(PnvPHB *phb) @@ -1137,7 +1164,7 @@ static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) device_class_set_parent_realize(dc, pnv_phb3_root_port_realize, &rpc->parent_realize); - dc->user_creatable = false; + dc->user_creatable = true; k->vendor_id = PCI_VENDOR_ID_IBM; k->device_id = 0x03dc; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 12a3fe4920..d9e7530cd3 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1152,7 +1152,9 @@ static void pnv_chip_power8_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); - chip8->num_phbs = pcc->num_phbs; + if (defaults_enabled()) { + chip8->num_phbs = pcc->num_phbs; + } for (i = 0; i < chip8->num_phbs; i++) { object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB); @@ -1977,6 +1979,23 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) return NULL; } +void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index) +{ + Object *parent = OBJECT(chip); + g_autofree char *default_id = + g_strdup_printf("%s[%d]", object_get_typename(obj), index); + + if (obj->parent == parent) { + return; + } + + object_ref(obj); + object_unparent(obj); + object_property_add_child( + parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj); + object_unref(obj); +} + PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) { int i; @@ -2116,6 +2135,8 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); } static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 539454fe9d..e489bec019 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -190,6 +190,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); void pnv_phb_attach_root_port(PCIHostState *pci, const char *name); +void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index); #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") typedef struct PnvMachineClass PnvMachineClass; From patchwork Sat May 7 19:06:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0B71C433F5 for ; Sat, 7 May 2022 19:15:51 +0000 (UTC) Received: from localhost ([::1]:51886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPuA-0004VL-Md for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:15:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPlY-0005fo-DG; Sat, 07 May 2022 15:06:56 -0400 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]:34657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nnPlV-0001ZF-LL; Sat, 07 May 2022 15:06:56 -0400 Received: by mail-oi1-x233.google.com with SMTP id j12so6181859oie.1; Sat, 07 May 2022 12:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bYqOp8k1rU+dDA9esCZEbvwm9fn+nB2WYshFxo7Yl0U=; b=KZsf0dCARPjwqew2Vh9TSW0A9E9qAhe2SF+QXg8QTMSjsmcryGrMh+2mec5tSKfogl 3tqqcax9RgXvWhmRx0M9q/QC+WgHElVEvDqcwR4/MGyafbtJCw7xfVz4keEQYQuXCu5L G8Lz6w4fVnMQz2Hfzmi60QNEai1WLwug4fYoL2pQGo0em+FT2vRBWtYUF6+Sd6NhlPGM xIWtS1vsf/B1JF5F4hRr2NAPgRF7zwqasNgNLTrLRgyP7ue/sBGJg45rsC712FASFhuX DJdEra0QPl2dfkzuQJmwQSuvKoDfmqHrA6611rkvcnntIaXCudJK6okavxkGbwwyw35G 0hCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bYqOp8k1rU+dDA9esCZEbvwm9fn+nB2WYshFxo7Yl0U=; b=m3atUxTnhErIpAGD/VewBa761ZS1H63wY77o/PvY3MwzNapHo5DMmjHG4n3MHt5etr 4Lu+WK5WciVZOk9962DeVN4hewUF9dxrZ1jFODZnBY3y5pBWTVBAdk83knucl/hXxDBE O+J/XcBOy3djF8kiyiUDSxBe2rY1raxHC4UxNZOxDFp9Ze5R8xJrx+a8Uhebc7zngY4E 1aw75BwBmmDL8agceEEz1ZL1NJ/iQ4FxHvmAN8Z9qpc4sksGCiXD4RvvxxTX7BN1OS6y kIJ2qlvXYeIUUj9XG0aQS4VXGGVVgOkeqrIKjZ0LaL0fVkh9An5/IeKy48vpX3M6ZyU2 xR9w== X-Gm-Message-State: AOAM531VdiSkUueNFOy97gVgh/5ortWO3Tgjv5fgcj1W+F3ZfnZJlizU fLVO+OMfscRfixYavpk0tmHzt+VHeHI= X-Google-Smtp-Source: ABdhPJxd1LODqxYyZj43Y2NlPEgkNaDzrpucubExJmeHr27FaOXA7rHXZQjaJqBbF934w4toyXujUg== X-Received: by 2002:aca:ead4:0:b0:2ec:ba66:12df with SMTP id i203-20020acaead4000000b002ecba6612dfmr8054176oih.194.1651950411765; Sat, 07 May 2022 12:06:51 -0700 (PDT) Received: from balboa.ibmmodules.com (201-1-57-208.dsl.telesp.net.br. [201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 08/17] ppc/pnv: remove PnvPHB4 Date: Sat, 7 May 2022 16:06:15 -0300 Message-Id: <20220507190624.507419-9-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The PnvPHB device is able to replace the PnvPHB4 device in all instances, while also being usable by the PHB3 logic. The PnvPHB4 device wasn't user creatable in any official QEMU release, so we can remove it without breaking ABI. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb.c | 15 ++++ hw/pci-host/pnv_phb4.c | 138 +++++++++++---------------------- hw/pci-host/pnv_phb4_pec.c | 4 +- hw/ppc/pnv.c | 2 +- include/hw/pci-host/pnv_phb4.h | 98 +++-------------------- 5 files changed, 75 insertions(+), 182 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index e4c4cca311..9583c703d4 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -55,7 +55,10 @@ static void pnv_phb_instance_init(Object *obj) !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8E) || !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8NVL)) { pnv_phb3_instance_init(obj); + return; } + + pnv_phb4_instance_init(obj); } static void pnv_phb_realize(DeviceState *dev, Error **errp) @@ -69,7 +72,10 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp) !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8NVL)) { /* PnvPHB3 */ pnv_phb3_realize(dev, errp); + return; } + + pnv_phb4_realize(dev, errp); } static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, @@ -86,6 +92,8 @@ static Property pnv_phb_properties[] = { DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *), + DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC, + PnvPhb4PecState *), DEFINE_PROP_END_OF_LIST(), }; @@ -93,12 +101,15 @@ static void pnv_phb_class_init(ObjectClass *klass, void *data) { PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); + XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); hc->root_bus_path = pnv_phb_root_bus_path; dc->realize = pnv_phb_realize; device_class_set_props(dc, pnv_phb_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->user_creatable = true; + + xfc->notify = pnv_phb4_xive_notify; } static const TypeInfo pnv_phb_type_info = { @@ -107,6 +118,10 @@ static const TypeInfo pnv_phb_type_info = { .instance_size = sizeof(PnvPHB), .class_init = pnv_phb_class_init, .instance_init = pnv_phb_instance_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_XIVE_NOTIFIER }, + { }, + }, }; static void pnv_phb_register_types(void) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 13ba9e45d8..becfd366f1 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -47,7 +47,7 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, return (word & ~mask) | ((value << ctz64(mask)) & mask); } -static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) +static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB *phb) { PCIHostState *pci = PCI_HOST_BRIDGE(phb); uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; @@ -70,7 +70,7 @@ static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) * The CONFIG_DATA register expects little endian accesses, but as the * region is big endian, we have to swap the value. */ -static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off, +static void pnv_phb4_config_write(PnvPHB *phb, unsigned off, unsigned size, uint64_t val) { uint32_t cfg_addr, limit; @@ -105,7 +105,7 @@ static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off, pci_host_config_write_common(pdev, cfg_addr, limit, val, size); } -static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, +static uint64_t pnv_phb4_config_read(PnvPHB *phb, unsigned off, unsigned size) { uint32_t cfg_addr, limit; @@ -142,7 +142,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, /* * Root complex register accesses are memory mapped. */ -static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, +static void pnv_phb4_rc_config_write(PnvPHB *phb, unsigned off, unsigned size, uint64_t val) { PCIHostState *pci = PCI_HOST_BRIDGE(phb); @@ -163,7 +163,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, bswap32(val), 4); } -static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, +static uint64_t pnv_phb4_rc_config_read(PnvPHB *phb, unsigned off, unsigned size) { PCIHostState *pci = PCI_HOST_BRIDGE(phb); @@ -185,7 +185,7 @@ static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, return bswap32(val); } -static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index) +static void pnv_phb4_check_mbt(PnvPHB *phb, uint32_t index) { uint64_t base, start, size, mbe0, mbe1; MemoryRegion *parent; @@ -248,7 +248,7 @@ static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index) memory_region_add_subregion(parent, base, &phb->mr_mmio[index]); } -static void pnv_phb4_check_all_mbt(PnvPHB4 *phb) +static void pnv_phb4_check_all_mbt(PnvPHB *phb) { uint64_t i; uint32_t num_windows = phb->big_phb ? PNV_PHB4_MAX_MMIO_WINDOWS : @@ -259,7 +259,7 @@ static void pnv_phb4_check_all_mbt(PnvPHB4 *phb) } } -static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb, +static uint64_t *pnv_phb4_ioda_access(PnvPHB *phb, unsigned *out_table, unsigned *out_idx) { uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3]; @@ -336,7 +336,7 @@ static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb, return tptr; } -static uint64_t pnv_phb4_ioda_read(PnvPHB4 *phb) +static uint64_t pnv_phb4_ioda_read(PnvPHB *phb) { unsigned table, idx; uint64_t *tptr; @@ -355,7 +355,7 @@ static uint64_t pnv_phb4_ioda_read(PnvPHB4 *phb) return *tptr; } -static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val) +static void pnv_phb4_ioda_write(PnvPHB *phb, uint64_t val) { unsigned table, idx; uint64_t *tptr; @@ -419,7 +419,7 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val) } } -static void pnv_phb4_rtc_invalidate(PnvPHB4 *phb, uint64_t val) +static void pnv_phb4_rtc_invalidate(PnvPHB *phb, uint64_t val) { PnvPhb4DMASpace *ds; @@ -458,7 +458,7 @@ static void pnv_phb4_update_msi_regions(PnvPhb4DMASpace *ds) } } -static void pnv_phb4_update_all_msi_regions(PnvPHB4 *phb) +static void pnv_phb4_update_all_msi_regions(PnvPHB *phb) { PnvPhb4DMASpace *ds; @@ -467,7 +467,7 @@ static void pnv_phb4_update_all_msi_regions(PnvPHB4 *phb) } } -static void pnv_phb4_update_xsrc(PnvPHB4 *phb) +static void pnv_phb4_update_xsrc(PnvPHB *phb) { int shift, flags, i, lsi_base; XiveSource *xsrc = &phb->xsrc; @@ -518,7 +518,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); bool changed; /* Special case outbound configuration data */ @@ -656,7 +656,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); uint64_t val; if ((off & 0xfffc) == PHB_CONFIG_DATA) { @@ -752,7 +752,7 @@ static const MemoryRegionOps pnv_phb4_reg_ops = { static uint64_t pnv_phb4_xscom_read(void *opaque, hwaddr addr, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); uint32_t reg = addr >> 3; uint64_t val; hwaddr offset; @@ -805,7 +805,7 @@ static uint64_t pnv_phb4_xscom_read(void *opaque, hwaddr addr, unsigned size) static void pnv_phb4_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); uint32_t reg = addr >> 3; hwaddr offset; @@ -868,7 +868,7 @@ const MemoryRegionOps pnv_phb4_xscom_ops = { static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); uint32_t reg = addr >> 3; /* TODO: add list of allowed registers and error out if not */ @@ -876,14 +876,14 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, } /* - * Return the 'stack_no' of a PHB4. 'stack_no' is the order + * Return the 'stack_no' of a PHB. 'stack_no' is the order * the PHB4 occupies in the PEC. This is the reverse of what * pnv_phb4_pec_get_phb_id() does. * * E.g. a phb with phb_id = 4 and pec->index = 1 (PEC1) will * be the second phb (stack_no = 1) of the PEC. */ -static int pnv_phb4_get_phb_stack_no(PnvPHB4 *phb) +static int pnv_phb4_get_phb_stack_no(PnvPHB *phb) { PnvPhb4PecState *pec = phb->pec; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); @@ -897,7 +897,7 @@ static int pnv_phb4_get_phb_stack_no(PnvPHB4 *phb) return stack_no; } -static void pnv_phb4_update_regions(PnvPHB4 *phb) +static void pnv_phb4_update_regions(PnvPHB *phb) { /* Unmap first always */ if (memory_region_is_mapped(&phb->mr_regs)) { @@ -921,7 +921,7 @@ static void pnv_phb4_update_regions(PnvPHB4 *phb) pnv_phb4_check_all_mbt(phb); } -static void pnv_pec_phb_update_map(PnvPHB4 *phb) +static void pnv_pec_phb_update_map(PnvPHB *phb) { PnvPhb4PecState *pec = phb->pec; MemoryRegion *sysmem = get_system_memory(); @@ -1010,7 +1010,7 @@ static void pnv_pec_phb_update_map(PnvPHB4 *phb) static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); PnvPhb4PecState *pec = phb->pec; uint32_t reg = addr >> 3; @@ -1099,7 +1099,7 @@ static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = { static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); uint32_t reg = addr >> 3; /* TODO: add list of allowed registers and error out if not */ @@ -1109,7 +1109,7 @@ static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); uint32_t reg = addr >> 3; switch (reg) { @@ -1172,7 +1172,7 @@ static int pnv_phb4_map_irq(PCIDevice *pci_dev, int irq_num) static void pnv_phb4_set_irq(void *opaque, int irq_num, int level) { - PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPHB *phb = PNV_PHB(opaque); uint32_t lsi_base; /* LSI only ... */ @@ -1407,7 +1407,7 @@ static void pnv_phb4_msi_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { PnvPhb4DMASpace *ds = opaque; - PnvPHB4 *phb = ds->phb; + PnvPHB *phb = ds->phb; uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f); @@ -1444,7 +1444,7 @@ static const MemoryRegionOps pnv_phb4_msi_ops = { .endianness = DEVICE_LITTLE_ENDIAN }; -static PnvPhb4DMASpace *pnv_phb4_dma_find(PnvPHB4 *phb, PCIBus *bus, int devfn) +static PnvPhb4DMASpace *pnv_phb4_dma_find(PnvPHB *phb, PCIBus *bus, int devfn) { PnvPhb4DMASpace *ds; @@ -1458,7 +1458,7 @@ static PnvPhb4DMASpace *pnv_phb4_dma_find(PnvPHB4 *phb, PCIBus *bus, int devfn) static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn) { - PnvPHB4 *phb = opaque; + PnvPHB *phb = opaque; PnvPhb4DMASpace *ds; char name[32]; @@ -1488,7 +1488,7 @@ static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn) return &ds->dma_as; } -static void pnv_phb4_xscom_realize(PnvPHB4 *phb) +static void pnv_phb4_xscom_realize(PnvPHB *phb) { PnvPhb4PecState *pec = phb->pec; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); @@ -1534,9 +1534,9 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb) &phb->phb_regs_mr); } -static void pnv_phb4_instance_init(Object *obj) +void pnv_phb4_instance_init(Object *obj) { - PnvPHB4 *phb = PNV_PHB4(obj); + PnvPHB *phb = PNV_PHB(obj); QLIST_INIT(&phb->dma_spaces); @@ -1544,9 +1544,9 @@ static void pnv_phb4_instance_init(Object *obj) object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); } -static void pnv_phb4_realize(DeviceState *dev, Error **errp) +void pnv_phb4_realize(DeviceState *dev, Error **errp) { - PnvPHB4 *phb = PNV_PHB4(dev); + PnvPHB *phb = PNV_PHB(dev); PCIHostState *pci = PCI_HOST_BRIDGE(dev); XiveSource *xsrc = &phb->xsrc; int nr_irqs; @@ -1602,22 +1602,12 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) pnv_phb4_xscom_realize(phb); } -static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, - PCIBus *rootbus) -{ - PnvPHB4 *phb = PNV_PHB4(host_bridge); - - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", - phb->chip_id, phb->phb_id); - return phb->bus_path; -} - /* * Address base trigger mode (POWER10) * * Trigger directly the IC ESB page */ -static void pnv_phb4_xive_notify_abt(PnvPHB4 *phb, uint32_t srcno, +static void pnv_phb4_xive_notify_abt(PnvPHB *phb, uint32_t srcno, bool pq_checked) { uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; @@ -1657,7 +1647,7 @@ static void pnv_phb4_xive_notify_abt(PnvPHB4 *phb, uint32_t srcno, } } -static void pnv_phb4_xive_notify_ic(PnvPHB4 *phb, uint32_t srcno, +static void pnv_phb4_xive_notify_ic(PnvPHB *phb, uint32_t srcno, bool pq_checked) { uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; @@ -1679,10 +1669,10 @@ static void pnv_phb4_xive_notify_ic(PnvPHB4 *phb, uint32_t srcno, } } -static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno, - bool pq_checked) +void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno, + bool pq_checked) { - PnvPHB4 *phb = PNV_PHB4(xf); + PnvPHB *phb = PNV_PHB(xf); if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE) { pnv_phb4_xive_notify_abt(phb, srcno, pq_checked); @@ -1691,45 +1681,10 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno, } } -static Property pnv_phb4_properties[] = { - DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0), - DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), - DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, - PnvPhb4PecState *), - DEFINE_PROP_END_OF_LIST(), -}; - -static void pnv_phb4_class_init(ObjectClass *klass, void *data) -{ - PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); - DeviceClass *dc = DEVICE_CLASS(klass); - XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); - - hc->root_bus_path = pnv_phb4_root_bus_path; - dc->realize = pnv_phb4_realize; - device_class_set_props(dc, pnv_phb4_properties); - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable = false; - - xfc->notify = pnv_phb4_xive_notify; -} - -static const TypeInfo pnv_phb4_type_info = { - .name = TYPE_PNV_PHB4, - .parent = TYPE_PCIE_HOST_BRIDGE, - .instance_init = pnv_phb4_instance_init, - .instance_size = sizeof(PnvPHB4), - .class_init = pnv_phb4_class_init, - .interfaces = (InterfaceInfo[]) { - { TYPE_XIVE_NOTIFIER }, - { }, - } -}; - static const TypeInfo pnv_phb5_type_info = { .name = TYPE_PNV_PHB5, - .parent = TYPE_PNV_PHB4, - .instance_size = sizeof(PnvPHB4), + .parent = TYPE_PNV_PHB, + .instance_size = sizeof(PnvPHB), }; static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data) @@ -1779,14 +1734,14 @@ static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); PCIDevice *pci = PCI_DEVICE(dev); PCIBus *bus = pci_get_bus(pci); - PnvPHB4 *phb = NULL; + PnvPHB *phb = NULL; Error *local_err = NULL; - phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), - TYPE_PNV_PHB4); + phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB); if (!phb) { - error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id); + error_setg(errp, "%s must be connected to pnv-phb buses", dev->id); return; } @@ -1856,14 +1811,13 @@ static void pnv_phb4_register_types(void) type_register_static(&pnv_phb4_root_bus_info); type_register_static(&pnv_phb5_root_port_info); type_register_static(&pnv_phb4_root_port_info); - type_register_static(&pnv_phb4_type_info); type_register_static(&pnv_phb5_type_info); type_register_static(&pnv_phb4_iommu_memory_region_info); } type_init(pnv_phb4_register_types); -void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon) +void pnv_phb4_pic_print_info(PnvPHB *phb, Monitor *mon) { uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K; diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 61bc0b503e..3eed560e44 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -116,7 +116,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, Error **errp) { PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); - PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); + PnvPHB *phb = PNV_PHB(qdev_new(pecc->phb_type)); int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); @@ -262,7 +262,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); pecc->version = PNV_PHB4_VERSION; - pecc->phb_type = TYPE_PNV_PHB4; + pecc->phb_type = TYPE_PNV_PHB; pecc->num_phbs = pnv_pec_num_phbs; pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT; } diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d9e7530cd3..34a200a29c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -676,7 +676,7 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) { Monitor *mon = opaque; - PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); + PnvPHB *phb4 = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); if (phb4) { pnv_phb4_pic_print_info(phb4, mon); diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 19dcbd6f87..65a16f2067 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -12,12 +12,12 @@ #include "hw/pci/pcie_host.h" #include "hw/pci/pcie_port.h" +#include "hw/pci-host/pnv_phb.h" #include "hw/ppc/xive.h" #include "qom/object.h" typedef struct PnvPhb4PecState PnvPhb4PecState; typedef struct PnvPhb4PecStack PnvPhb4PecStack; -typedef struct PnvPHB4 PnvPHB4; typedef struct PnvChip PnvChip; /* @@ -36,7 +36,7 @@ typedef struct PnvPhb4DMASpace { uint8_t devfn; int pe_num; /* Cached PE number */ #define PHB_INVALID_PE (-1) - PnvPHB4 *phb; + PnvPHB *phb; AddressSpace dma_as; IOMMUMemoryRegion dma_mr; MemoryRegion msi32_mr; @@ -55,11 +55,9 @@ typedef struct PnvPHB4RootPort { PCIESlot parent_obj; } PnvPHB4RootPort; -/* - * PHB4 PCIe Host Bridge for PowerNV machines (POWER9) - */ -#define TYPE_PNV_PHB4 "pnv-phb4" -OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) +struct PnvPHB4DeviceClass { + DeviceClass parent_class; +}; #define PNV_PHB4_MAX_LSIs 8 #define PNV_PHB4_MAX_INTs 4096 @@ -77,85 +75,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) -struct PnvPHB4 { - PCIExpressHost parent_obj; - - uint32_t chip_id; - uint32_t phb_id; - - uint64_t version; - - /* The owner PEC */ - PnvPhb4PecState *pec; - - char bus_path[8]; - - /* Main register images */ - uint64_t regs[PNV_PHB4_NUM_REGS]; - MemoryRegion mr_regs; - - /* Extra SCOM-only register */ - uint64_t scom_hv_ind_addr_reg; - - /* - * Geometry of the PHB. There are two types, small and big PHBs, a - * number of resources (number of PEs, windows etc...) are doubled - * for a big PHB - */ - bool big_phb; - - /* Memory regions for MMIO space */ - MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS]; - - /* PCI side space */ - MemoryRegion pci_mmio; - MemoryRegion pci_io; - - /* PCI registers (excluding pass-through) */ -#define PHB4_PEC_PCI_STK_REGS_COUNT 0xf - uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT]; - MemoryRegion pci_regs_mr; - - /* Nest registers */ -#define PHB4_PEC_NEST_STK_REGS_COUNT 0x17 - uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; - MemoryRegion nest_regs_mr; - - /* PHB pass-through XSCOM */ - MemoryRegion phb_regs_mr; - - /* Memory windows from PowerBus to PHB */ - MemoryRegion phbbar; - MemoryRegion intbar; - MemoryRegion mmbar0; - MemoryRegion mmbar1; - uint64_t mmio0_base; - uint64_t mmio0_size; - uint64_t mmio1_base; - uint64_t mmio1_size; - - /* On-chip IODA tables */ - uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; - uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; - uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; - uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; - uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; - uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs]; - - /* - * The internal PESTA/B is 2 bits per PE split into two tables, we - * store them in a single array here to avoid wasting space. - */ - uint8_t ioda_PEST_AB[PNV_PHB4_MAX_PEs]; - - /* P9 Interrupt generation */ - XiveSource xsrc; - qemu_irq *qirqs; - - QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; -}; - -void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon); +void pnv_phb4_pic_print_info(PnvPHB *phb, Monitor *mon); int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); extern const MemoryRegionOps pnv_phb4_xscom_ops; @@ -214,7 +134,7 @@ struct PnvPhb4PecClass { #define TYPE_PNV_PHB5 "pnv-phb5" #define PNV_PHB5(obj) \ - OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5) + OBJECT_CHECK(PnvPhb, (obj), TYPE_PNV_PHB5) #define PNV_PHB5_VERSION 0x000000a500000001ull #define PNV_PHB5_DEVICE_ID 0x0652 @@ -223,4 +143,8 @@ struct PnvPhb4PecClass { #define PNV_PHB5_PEC(obj) \ OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC) +void pnv_phb4_instance_init(Object *obj); +void pnv_phb4_realize(DeviceState *dev, Error **errp); +void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno, bool pq_checked); + #endif /* PCI_HOST_PNV_PHB4_H */ From patchwork Sat May 7 19:06:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE2FDC433EF for ; Sat, 7 May 2022 19:18:08 +0000 (UTC) Received: from localhost ([::1]:59490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPwN-0001EB-NN for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:18:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPlZ-0005kE-E7; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:53 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 09/17] ppc/pnv: user creatable pnv-phb for powernv9 Date: Sat, 7 May 2022 16:06:16 -0300 Message-Id: <20220507190624.507419-10-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch reintroduces the powernv8 bits of the code what was removed in commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices", using the pnv-phb device instead of the now late pnv-phb4 device, allowing us to enable user creatable pnv-phb devices for the powernv9 machine. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 58 +++++++++++++++++++++++++++++++++++++- hw/pci-host/pnv_phb4_pec.c | 6 ++-- hw/ppc/pnv.c | 2 ++ 3 files changed, 63 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index becfd366f1..262251ebcf 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1544,14 +1544,70 @@ void pnv_phb4_instance_init(Object *obj) object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); } +static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB *phb, + Error **errp) +{ + Pnv9Chip *chip9 = PNV9_CHIP(chip); + int chip_id = phb->chip_id; + int index = phb->phb_id; + int i, j; + + for (i = 0; i < chip->num_pecs; i++) { + /* + * For each PEC, check the amount of phbs it supports + * and see if the given phb4 index matches an index. + */ + PnvPhb4PecState *pec = &chip9->pecs[i]; + + for (j = 0; j < pec->num_phbs; j++) { + if (index == pnv_phb4_pec_get_phb_id(pec, j)) { + return pec; + } + } + } + + error_setg(errp, + "pnv-phb chip-id %d index %d didn't match any existing PEC", + chip_id, index); + + return NULL; +} + void pnv_phb4_realize(DeviceState *dev, Error **errp) { PnvPHB *phb = PNV_PHB(dev); + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); PCIHostState *pci = PCI_HOST_BRIDGE(dev); XiveSource *xsrc = &phb->xsrc; + BusState *s; + Error *local_err = NULL; int nr_irqs; char name[32]; + if (!chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + + /* User created PHBs need to be assigned to a PEC */ + if (!phb->pec) { + phb->pec = pnv_phb4_get_pec(chip, phb, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + } + + /* Reparent the PHB to the chip to build the device tree */ + pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id); + + s = qdev_get_parent_bus(DEVICE(chip)); + if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { + error_propagate(errp, local_err); + return; + } + /* Set the "big_phb" flag */ phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3; @@ -1763,7 +1819,7 @@ static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data) PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); dc->desc = "IBM PHB4 PCIE Root Port"; - dc->user_creatable = false; + dc->user_creatable = true; device_class_set_parent_realize(dc, pnv_phb4_root_port_realize, &rpc->parent_realize); diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 3eed560e44..243a079ea7 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -150,8 +150,10 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) pec->num_phbs = pecc->num_phbs[pec->index]; /* Create PHBs if running with defaults */ - for (i = 0; i < pec->num_phbs; i++) { - pnv_pec_default_phb_realize(pec, i, errp); + if (defaults_enabled()) { + for (i = 0; i < pec->num_phbs; i++) { + pnv_pec_default_phb_realize(pec, i, errp); + } } /* Initialize the XSCOM regions for the PEC registers */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 34a200a29c..1a3cafcb7a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2155,6 +2155,8 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); pmc->dt_power_mgt = pnv_dt_power_mgt; + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); } static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) From patchwork Sat May 7 19:06:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18FCCC4332F for ; Sat, 7 May 2022 19:12:28 +0000 (UTC) Received: from localhost ([::1]:40688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPqt-0005WV-8R for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:12:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPlb-0005oT-QC; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:56 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 10/17] ppc/pnv: use PnvPHB.version Date: Sat, 7 May 2022 16:06:17 -0300 Message-Id: <20220507190624.507419-11-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The 'version' attribute of the PnvPHB was never used. Instead of removing it, let's make use of it by setting the PHB version the PnvPHB device is currently running. This distinction will be used next patch. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb.c | 11 +++++++++++ include/hw/pci-host/pnv_phb.h | 7 +++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 9583c703d4..cef6a57d50 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -63,6 +63,7 @@ static void pnv_phb_instance_init(Object *obj) static void pnv_phb_realize(DeviceState *dev, Error **errp) { + PnvPHB *phb = PNV_PHB(dev); g_autofree char *chip_typename = pnv_phb_get_chip_typename(); g_assert(chip_typename != NULL); @@ -71,10 +72,20 @@ static void pnv_phb_realize(DeviceState *dev, Error **errp) !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8E) || !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8NVL)) { /* PnvPHB3 */ + phb->version = PHB_VERSION_3; pnv_phb3_realize(dev, errp); return; } + if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER9)) { + phb->version = PHB_VERSION_4; + } else if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER10)) { + phb->version = PHB_VERSION_5; + } else { + error_setg(errp, "unknown PNV chip: %s", chip_typename); + return; + } + pnv_phb4_realize(dev, errp); } diff --git a/include/hw/pci-host/pnv_phb.h b/include/hw/pci-host/pnv_phb.h index 46158e124f..cceb37d03c 100644 --- a/include/hw/pci-host/pnv_phb.h +++ b/include/hw/pci-host/pnv_phb.h @@ -103,9 +103,14 @@ typedef struct PnvPhb4PecState PnvPhb4PecState; #define TYPE_PNV_PHB "pnv-phb" OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB, PNV_PHB) +#define PHB_VERSION_3 3 +#define PHB_VERSION_4 4 +#define PHB_VERSION_5 5 + struct PnvPHB { PCIExpressHost parent_obj; + uint64_t version; uint32_t chip_id; uint32_t phb_id; char bus_path[8]; @@ -142,8 +147,6 @@ struct PnvPHB { /* * PnvPHB4 attributes */ - uint64_t version; - /* The owner PEC */ PnvPhb4PecState *pec; From patchwork Sat May 7 19:06:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52F2FC433F5 for ; Sat, 7 May 2022 19:14:37 +0000 (UTC) Received: from localhost ([::1]:49202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPsy-0002hU-5I for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:14:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPld-0005r7-KP; Sat, 07 May 2022 15:07:03 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]:43760) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nnPlc-0001Zt-51; Sat, 07 May 2022 15:07:01 -0400 Received: by mail-oi1-x229.google.com with SMTP id v65so11105183oig.10; Sat, 07 May 2022 12:06:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lyrqtu/ju6nIMFNI5M52L71ErShd0EbZtz7+D8xmNmM=; b=GEaIdZgjMsYAJPz0HSB9oLIsA2XlI1wATZYzC/rsPTYcmTvAM4q+kRwZY5DRWA5q7F LSXAq+zGb0k7fdNdteMPNAhB4T1Fz1TklWxaQ5PVkpzEr1qFsjz0mADSGImnrPIjhznc 4+qtBwmIFJZuEnPhqqDwuWjur7rg8K3lVW1EDrL8B7bHbMhEtKLXgiKdElPdtBF/t6pz KRfI8iCo9tc8wnzVBvJbh4bxoOATHPx+/lN7lfZO+S3DnCTVC7nnP9dvDU5bTShj4kBL qKXh+EM/Kxha3O+toFTWTBFJMdSPXumypriumym++bQUZVwMWfZaf1/kz9Sm8URE8PRP 3uxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lyrqtu/ju6nIMFNI5M52L71ErShd0EbZtz7+D8xmNmM=; b=gKDM1x/mm7hudxN6rClelrv6IWvBkzFv7P1ZnKAaA3PAh22C5ymKyooHhKv6YWpN1O qEOL0SXz9FL2lZpvXmT+VqoLaC6lzMBvnd0NLrWpRuI3SuDLqNKGZQp5d77M7BFrOlh3 PH68PVydInELBq8391VsbZOi/urWzoXTPGAboNYd/DmP92RnfP3q4vE845Jq6ZejgjxX 2gjPhCIzCK0KYYmovR7ASOf56HY0bANBHuuxlaVGx67IOft4WwdSYc0AvpkMgJPRk+AU sdcSMqVuuFD3VCGJRlQXKpVgHc94R1tlbruF7G4JMqENcpIhScqlshz/d+Cv+nyHuS6Z LLHA== X-Gm-Message-State: AOAM5337867T+IyGPLLi0qIXMFZBRlif6JPuHP4namNSRlBq3Uus384v tzcGnCegPp5yEDhxltJo69R3+AYfF1Y= X-Google-Smtp-Source: ABdhPJxkFcvTQyMZK5+Htm1UDk4M6DcKBN4abk5TlFgvT6I9GJ9mRbVjk+RBARvfWoYUP4JMROIAEg== X-Received: by 2002:a05:6808:ecc:b0:322:319c:cd3 with SMTP id q12-20020a0568080ecc00b00322319c0cd3mr7670277oiv.148.1651950418753; Sat, 07 May 2022 12:06:58 -0700 (PDT) Received: from balboa.ibmmodules.com (201-1-57-208.dsl.telesp.net.br. [201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:06:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 11/17] ppc/pnv: change pnv_phb4_get_pec() to also retrieve chip10->pecs Date: Sat, 7 May 2022 16:06:18 -0300 Message-Id: <20220507190624.507419-12-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The function assumes that we're always dealing with a PNV9_CHIP() object. This is not the case when the pnv-phb device belongs to a powernv10 machine. Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if necessary. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 262251ebcf..f911957f10 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1547,17 +1547,29 @@ void pnv_phb4_instance_init(Object *obj) static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB *phb, Error **errp) { - Pnv9Chip *chip9 = PNV9_CHIP(chip); + PnvPhb4PecState *pecs = NULL; int chip_id = phb->chip_id; int index = phb->phb_id; int i, j; + if (phb->version == PHB_VERSION_4) { + Pnv9Chip *chip9 = PNV9_CHIP(chip); + + pecs = chip9->pecs; + } else if (phb->version == PHB_VERSION_5) { + Pnv10Chip *chip10 = PNV10_CHIP(chip); + + pecs = chip10->pecs; + } else { + return NULL; + } + for (i = 0; i < chip->num_pecs; i++) { /* * For each PEC, check the amount of phbs it supports * and see if the given phb4 index matches an index. */ - PnvPhb4PecState *pec = &chip9->pecs[i]; + PnvPhb4PecState *pec = &pecs[i]; for (j = 0; j < pec->num_phbs; j++) { if (index == pnv_phb4_pec_get_phb_id(pec, j)) { From patchwork Sat May 7 19:06:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67FDBC433F5 for ; Sat, 7 May 2022 19:18:20 +0000 (UTC) Received: from localhost ([::1]:60450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPwZ-0001vt-IH for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:18:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPlf-0005rs-DJ; Sat, 07 May 2022 15:07:03 -0400 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]:39927) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nnPle-0001XG-1U; Sat, 07 May 2022 15:07:03 -0400 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-deb9295679so10547896fac.6; Sat, 07 May 2022 12:07:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xmyvjZGeJMptuTaPZY79LPqXlpBB0BF1k94gn8nzXV4=; b=Oz3dbZxtZyV7lni0meyjy/6pg+2XbS3jUU4yrwdtzkRDqT9CKGy/N+nmEhZNa5zGop rNRwtiwCRk/W4l18CULUXfT+mDjzTVXIwDx7kkBj6rjlgGR1bdMg10uhBCQEzipPPuwA pzH0muNkE+xXa15cN+xhy/3hvdmqSfnp6RYeHmxEWedx+mqg6lh9ruPX63+qWFXPx9uz EOFqodXDNATgssyz1y4ua+9dnNmlqLdG4Rlc3dY2meoxVdtmwckooojx0+3NxFuD9Axa Ic14SUt0Qa2PwnvziWdPqnkUmH6zk3HivfavKh27t44SGXnJ7ySwuYbovEBvVB7fPE88 4ZFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xmyvjZGeJMptuTaPZY79LPqXlpBB0BF1k94gn8nzXV4=; b=JqHttcIavkdrNiSpLu/NP7SefiPfQMUmRlpigxZhkWXsHPhgHkTZ41zEnHBk8KgKag WzngJkuOLSjUs/dtNzov0Ne2b5/kbd1qaug7IpNz4N9wgGl47aa8IDxOmwho3hkl2zY2 H6NSrr5rILI08KEO4074/qdgbubvtFlgP/ERFfJwerHMz3CZT9ltvWwz40ngiI3uEZTl UVrQ0QKU5gP6IfInvVwwQZjd5B3REcx7P0ozowKByut57BnvEYRIKLR5DRRJQSFTofbU XHOl+REzVaAC36UEEMJu+HXuskbJ64FduN6qHLpy5U6SI4YWL7b9zm6KdTG4x6TZ9EQp ELWA== X-Gm-Message-State: AOAM531FS8eGzK598XQzabMW5OfAayfqky4MEJ2yMVd7tPUbzNw/tcZb GJIev3mcMPa18SfIgLeO+ZKqa3xYvhM= X-Google-Smtp-Source: ABdhPJyFWcdn53SxtieUZ3jAVA0ymS7TyhRi52aoxLErMdOdldoWs9Lv7xCzk/hVUBHJpH+cVK8lvw== X-Received: by 2002:a05:6870:8985:b0:da:b3f:3253 with SMTP id f5-20020a056870898500b000da0b3f3253mr3648866oaq.259.1651950420925; Sat, 07 May 2022 12:07:00 -0700 (PDT) Received: from balboa.ibmmodules.com (201-1-57-208.dsl.telesp.net.br. [201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:07:00 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 12/17] ppc/pnv: user creatable pnv-phb for powernv10 Date: Sat, 7 May 2022 16:06:19 -0300 Message-Id: <20220507190624.507419-13-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Given that powernv9 and powernv10 uses the same pnv-phb backend, the logic to allow user created pnv-phbs for powernv10 is already in place. This patch just flips the switch. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 2 +- hw/ppc/pnv.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index f911957f10..fb3222d458 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1861,7 +1861,7 @@ static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); dc->desc = "IBM PHB5 PCIE Root Port"; - dc->user_creatable = false; + dc->user_creatable = true; k->vendor_id = PCI_VENDOR_ID_IBM; k->device_id = PNV_PHB5_DEVICE_ID; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 1a3cafcb7a..bb193b1ed3 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2174,6 +2174,8 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) pmc->dt_power_mgt = pnv_dt_power_mgt; xfc->match_nvt = pnv10_xive_match_nvt; + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); } static bool pnv_machine_get_hb(Object *obj, Error **errp) From patchwork Sat May 7 19:06:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5988C433EF for ; Sat, 7 May 2022 19:21:02 +0000 (UTC) Received: from localhost ([::1]:39582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnPzA-0006ye-Ny for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:21:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPli-0005wN-EX; Sat, 07 May 2022 15:07:06 -0400 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]:33919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nnPlg-0001aN-N5; Sat, 07 May 2022 15:07:06 -0400 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-ed9ac77cbbso10560925fac.1; Sat, 07 May 2022 12:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gei2OB85I43clXzsP6k10NUHL8FGav4LFxdv8uOXcWs=; b=Vfx/wrL/Wanx3y7kG+9M6kwl/56MAHYcdJ5/flAzFKsIpS8XK5e0soGWfesCoBnY+9 o/3EM/gurfKTSXR5HNS3WyLbRZsPUTQ1wNonw/H9TITRZr73HXEyA+Ri41pOtLgZgWbV UB/OGzU6HgmcJwaxBJMECLjqC5u6TajrkOm8hnV7igjM/F15OPWw6/wGe+J5sTXA/4nX /o0hmKKF9lUDET9uTdoWim9Zi8CvtArDX7h4uumicoqN7fJJFtQXdSTWVbMs/6CAQUBa y2vVNkTzdcmZsH2eYKJq91k6eqsfEhoxMfNz1JV+n3NpDr0SaAV1Mg89Js3Cjqz1AKl7 lVhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gei2OB85I43clXzsP6k10NUHL8FGav4LFxdv8uOXcWs=; b=0VNhibxBQuFgpF/toK0fHZDW7jTH2i/aWiCC6U2uMRN+W/V77C6AWd+KNnjLVjXgmc 4byxllZ71QajNqMysMvBylwHyoEWh40PNvqz2WN8N96nsbSwQ6fdAxWpKFoiQXg+9EV2 cXiEG2vt9PcypthhXVDQisjhG9U5hvZUc0MYIBwCZ/iLUc//zSf5XCKod6yOT56GYx1C /udikTz+jSEhUMYN1N24mZOEMT0w5moDPnxq1EkcpqxVoeUR4CSBkYPYMDowpztOud82 j+Ddsl+zLmctMs4yr0Aruy5l5HLpGjvfP/bHW5I0wNUhvXoLiC5Wzg1j/pZjaM4QN6PX BPHw== X-Gm-Message-State: AOAM531LSkzBcSh41V/fSzVY0rooOoQgjyS8Za1oYQe2+FDm90iXk3rR S4lEFGB/BahNEh7Dqr6RvGrEHcBZTks= X-Google-Smtp-Source: ABdhPJwMDQjTQiOnPgrJLrLdFNepIGM4+07jWWUISprj2ixseNhvbLFPWS/cSS3mY98ZKlMeezJ8Hw== X-Received: by 2002:a05:6870:c348:b0:ed:f231:2b41 with SMTP id e8-20020a056870c34800b000edf2312b41mr6863186oak.23.1651950423404; Sat, 07 May 2022 12:07:03 -0700 (PDT) Received: from balboa.ibmmodules.com (201-1-57-208.dsl.telesp.net.br. [201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:07:03 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 13/17] ppc/pnv: add pnv_phb_get_current_machine() Date: Sat, 7 May 2022 16:06:20 -0300 Message-Id: <20220507190624.507419-14-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a simple helper to avoid hardcoding strcmp() comparisons all around pnv_phb.c. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb.c | 40 +++++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index cef6a57d50..e03062a494 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -20,6 +20,10 @@ #include "sysemu/sysemu.h" +#define PNV_MACHINE_POWER8 1 +#define PNV_MACHINE_POWER9 2 +#define PNV_MACHINE_POWER10 3 + static char *pnv_phb_get_chip_typename(void) { Object *qdev_machine = qdev_get_machine(); @@ -39,7 +43,7 @@ static char *pnv_phb_get_chip_typename(void) return g_steal_pointer(&chip_typename); } -static void pnv_phb_instance_init(Object *obj) +static int pnv_phb_get_current_machine(void) { g_autofree char *chip_typename = pnv_phb_get_chip_typename(); @@ -48,12 +52,31 @@ static void pnv_phb_instance_init(Object *obj) * a valid machine->cpu_type value. */ if (!chip_typename) { - return; + return 0; } if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER8) || !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8E) || !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8NVL)) { + return PNV_MACHINE_POWER8; + } else if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER9)) { + return PNV_MACHINE_POWER9; + } else if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER10)) { + return PNV_MACHINE_POWER10; + } + + return 0; +} + +static void pnv_phb_instance_init(Object *obj) +{ + int pnv_current_machine = pnv_phb_get_current_machine(); + + if (pnv_current_machine == 0) { + return; + } + + if (pnv_current_machine == PNV_MACHINE_POWER8) { pnv_phb3_instance_init(obj); return; } @@ -63,25 +86,24 @@ static void pnv_phb_instance_init(Object *obj) static void pnv_phb_realize(DeviceState *dev, Error **errp) { + int pnv_current_machine = pnv_phb_get_current_machine(); PnvPHB *phb = PNV_PHB(dev); - g_autofree char *chip_typename = pnv_phb_get_chip_typename(); - g_assert(chip_typename != NULL); + g_assert(pnv_current_machine != 0); - if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER8) || - !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8E) || - !strcmp(chip_typename, TYPE_PNV_CHIP_POWER8NVL)) { + if (pnv_current_machine == PNV_MACHINE_POWER8) { /* PnvPHB3 */ phb->version = PHB_VERSION_3; pnv_phb3_realize(dev, errp); return; } - if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER9)) { + if (pnv_current_machine == PNV_MACHINE_POWER9) { phb->version = PHB_VERSION_4; - } else if (!strcmp(chip_typename, TYPE_PNV_CHIP_POWER10)) { + } else if (pnv_current_machine == PNV_MACHINE_POWER10) { phb->version = PHB_VERSION_5; } else { + g_autofree char *chip_typename = pnv_phb_get_chip_typename(); error_setg(errp, "unknown PNV chip: %s", chip_typename); return; } From patchwork Sat May 7 19:06:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56C2CC433EF for ; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:07:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 14/17] ppc/pnv: add pnv-phb-root-port device Date: Sat, 7 May 2022 16:06:21 -0300 Message-Id: <20220507190624.507419-15-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We have two very similar root-port devices, pnv-phb3-root-port and pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device that, until now, has no additional attributes. The main difference between the PHB3 and PHB4 root ports is that pnv-phb4-root-port has the pnv_phb4_root_port_reset() callback. All other differences can be merged in a single device without too much trouble. This patch introduces the unified pnv-phb-root-port that, in time, will be used as the default root port for the pnv-phb device. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb.c | 93 +++++++++++++++++++++++++++++++++++ include/hw/pci-host/pnv_phb.h | 11 +++++ 2 files changed, 104 insertions(+) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index e03062a494..369dc21931 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -157,9 +157,102 @@ static const TypeInfo pnv_phb_type_info = { }, }; +static void pnv_phb_root_port_reset(DeviceState *dev) +{ + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); + PCIDevice *d = PCI_DEVICE(dev); + uint8_t *conf = d->config; + int pnv_current_machine = pnv_phb_get_current_machine(); + + rpc->parent_reset(dev); + + if (pnv_current_machine == PNV_MACHINE_POWER8) { + return; + } + + pci_byte_test_and_set_mask(conf + PCI_IO_BASE, + PCI_IO_RANGE_MASK & 0xff); + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, + PCI_IO_RANGE_MASK & 0xff); + pci_set_word(conf + PCI_MEMORY_BASE, 0); + pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); + pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); + pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); + pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ + pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); + pci_config_set_interrupt_pin(conf, 0); +} + +static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) +{ + PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); + PCIDevice *pci = PCI_DEVICE(dev); + PCIBus *bus = pci_get_bus(pci); + PnvPHB *phb = NULL; + Error *local_err = NULL; + + phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB); + + if (!phb) { + error_setg(errp, +"pnv_phb_root_port devices must be connected to pnv-phb buses"); + return; + } + + /* Set unique chassis/slot values for the root port */ + qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id); + qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id); + + rpc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + pci_config_set_interrupt_pin(pci->config, 0); +} + +static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); + + dc->desc = "IBM PHB PCIE Root Port"; + + device_class_set_parent_realize(dc, pnv_phb_root_port_realize, + &rpc->parent_realize); + + device_class_set_parent_reset(dc, pnv_phb_root_port_reset, + &rpc->parent_reset); + dc->reset = &pnv_phb_root_port_reset; + + dc->user_creatable = true; + + k->vendor_id = PCI_VENDOR_ID_IBM; + /* + * k->device_id is defaulted to PNV_PHB3_DEVICE_ID. We'll fix + * it during instance_init() when we are aware of what machine + * we're running. + */ + k->device_id = 0x03dc; + k->revision = 0; + + rpc->exp_offset = 0x48; + rpc->aer_offset = 0x100; +} + +static const TypeInfo pnv_phb_root_port_info = { + .name = TYPE_PNV_PHB_ROOT_PORT, + .parent = TYPE_PCIE_ROOT_PORT, + .instance_size = sizeof(PnvPHBRootPort), + .class_init = pnv_phb_root_port_class_init, +}; + static void pnv_phb_register_types(void) { type_register_static(&pnv_phb_type_info); + type_register_static(&pnv_phb_root_port_info); } type_init(pnv_phb_register_types) diff --git a/include/hw/pci-host/pnv_phb.h b/include/hw/pci-host/pnv_phb.h index cceb37d03c..ff90a9c200 100644 --- a/include/hw/pci-host/pnv_phb.h +++ b/include/hw/pci-host/pnv_phb.h @@ -210,4 +210,15 @@ struct PnvPHB { QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; }; +/* + * PHB PCIe Root port + */ +typedef struct PnvPHBRootPort { + PCIESlot parent_obj; +} PnvPHBRootPort; + +#define TYPE_PNV_PHB_ROOT_PORT "pnv-phb-root-port" +#define PNV_PHB_ROOT_PORT(obj) \ + OBJECT_CHECK(PnvPHBRootPort, obj, TYPE_PNV_PHB_ROOT_PORT) + #endif /* PCI_HOST_PNV_PHB_H */ From patchwork Sat May 7 19:06:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5718AC433F5 for ; Sat, 7 May 2022 19:24:09 +0000 (UTC) Received: from localhost ([::1]:45830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nnQ2C-0002uU-CB for qemu-devel@archiver.kernel.org; Sat, 07 May 2022 15:24:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54974) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nnPln-00063R-32; Sat, 07 May 2022 15:07:11 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]:45654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nnPll-0001at-J7; Sat, 07 May 2022 15:07:10 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-e93bbb54f9so10526703fac.12; Sat, 07 May 2022 12:07:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ofHjr863M55zAJYZjc/8WB8QUpdLBzZ169xhUdZ2QEs=; b=DFssnT6AToJcuOlTaGw17gO4UyGXTqgkPKSpjMmQnNOxnpYPLWOLqMN+piOrVXzPg2 QMYVUtjzr3KEZBK0+17IawRnH3YHQG+b3R4xRzO0E1of+u8EPmrbEs9NE3Cs/bGqUoYR oKk61pmQaoz90Vo4FYqijK5O3DTWZdK7ouY41s0DOql9NV2pV++q6aZ9SNgxPQDAqoaY EE0pkrvzJ9NTCrfl8m7ijbh3HkLJZ85J4MoxL8xfM/xodwwikCBMrOaRfiJJWHOLAZv3 aMRs2MBgcSvCDpxzGEKJ2Hhq+LxukGX4CF6wZEjFdoo1aE+71Rc8ry9ckocr4aHMxB7T w/AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ofHjr863M55zAJYZjc/8WB8QUpdLBzZ169xhUdZ2QEs=; b=Qm9QmVKEEYQkS/y4kSwIlbLPcJIH4wtMW5jMZGa4N7MdHv8ZSsgBmUHWOZwkPBrlta 4ISJeEfnfIBXsQwxNEtWi3ukTbVI0e7XdJhb+zeDda6rt3Wqob+JLLyOm07PUpOr0Iay R2cppwLb2jvVjWzNYszv5p4pisY3c9pBt8hLelhI42M5ctokt5AFam7BEGJBztLQh/41 xNJpiaRMjZGX4V8m5Mtuphu/Ou61rhq9YpvBFJaAqdg8N8nxjNeDwhJUJnPBmQkR2763 fTiWugwVHoU4G008XnskZBsgRWUG8ScA+kw3Rag+8mTV9+Ny0K6cxQmPSG6z019OvMNi mwzg== X-Gm-Message-State: AOAM530pRzqn35mbPHJMsNxvaLS5QxfMbB4iTNIsxm0s7IfQ6q2lKCZW N1ByrrYplcUxiPMeQ97IVmXKAPS6VMw= X-Google-Smtp-Source: ABdhPJzV5lQwlcl1NQ2VGHLWVXPBMVG9sjRAg1uYdeemzaCZjnk0tzf6BGqiwU3TrZiQrR5c1qaH0Q== X-Received: by 2002:a05:6870:7093:b0:e6:210a:d98d with SMTP id v19-20020a056870709300b000e6210ad98dmr3805661oae.68.1651950428204; Sat, 07 May 2022 12:07:08 -0700 (PDT) Received: from balboa.ibmmodules.com (201-1-57-208.dsl.telesp.net.br. [201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:07:07 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 15/17] ppc/pnv: remove pnv-phb3-root-port Date: Sat, 7 May 2022 16:06:22 -0300 Message-Id: <20220507190624.507419-16-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The unified pnv-phb-root-port can be used in its place. There is no ABI breakage in doing so because no official QEMU release introduced user creatable pnv-phb3-root-port devices. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb3.c | 59 +--------------------------------- include/hw/pci-host/pnv_phb3.h | 7 ---- 2 files changed, 1 insertion(+), 65 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a6d6a10c52..1c52df4c3f 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1078,7 +1078,7 @@ void pnv_phb3_realize(DeviceState *dev, Error **errp) if (defaults_enabled()) { pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), - TYPE_PNV_PHB3_ROOT_PORT); + TYPE_PNV_PHB_ROOT_PORT); } } @@ -1125,66 +1125,9 @@ static const TypeInfo pnv_phb3_root_bus_info = { }, }; -static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp) -{ - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); - PCIDevice *pci = PCI_DEVICE(dev); - PCIBus *bus = pci_get_bus(pci); - PnvPHB *phb = NULL; - Error *local_err = NULL; - - phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), - TYPE_PNV_PHB); - - if (!phb) { - error_setg(errp, -"pnv_phb3_root_port devices must be connected to pnv-phb buses"); - return; - } - - /* Set unique chassis/slot values for the root port */ - qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id); - qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id); - - rpc->parent_realize(dev, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - pci_config_set_interrupt_pin(pci->config, 0); -} - -static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); - - dc->desc = "IBM PHB3 PCIE Root Port"; - - device_class_set_parent_realize(dc, pnv_phb3_root_port_realize, - &rpc->parent_realize); - dc->user_creatable = true; - - k->vendor_id = PCI_VENDOR_ID_IBM; - k->device_id = 0x03dc; - k->revision = 0; - - rpc->exp_offset = 0x48; - rpc->aer_offset = 0x100; -} - -static const TypeInfo pnv_phb3_root_port_info = { - .name = TYPE_PNV_PHB3_ROOT_PORT, - .parent = TYPE_PCIE_ROOT_PORT, - .instance_size = sizeof(PnvPHB3RootPort), - .class_init = pnv_phb3_root_port_class_init, -}; - static void pnv_phb3_register_types(void) { type_register_static(&pnv_phb3_root_bus_info); - type_register_static(&pnv_phb3_root_port_info); type_register_static(&pnv_phb3_iommu_memory_region_info); } diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index 1c4af98fee..417b0f99a7 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -43,13 +43,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ) */ #define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root" -#define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port" - -typedef struct PnvPHB3RootPort { - PCIESlot parent_obj; -} PnvPHB3RootPort; - - #define PNV_PHB3_NUM_M64 16 #define PNV_PHB3_NUM_REGS (0x1000 >> 3) #define PNV_PHB3_NUM_LSI 8 From patchwork Sat May 7 19:06:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12842141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91A00C433F5 for ; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:07:10 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 16/17] ppc/pnv: remove pnv-phb4-root-port Date: Sat, 7 May 2022 16:06:23 -0300 Message-Id: <20220507190624.507419-17-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The unified pnv-phb-root-port can be used instead. THe pnv-phb4-root-port device isn't exposed to the user in any official QEMU release so there's no ABI breakage in removing it. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 100 --------------------------------- hw/pci-host/pnv_phb4_pec.c | 4 +- include/hw/pci-host/pnv_phb4.h | 9 --- 3 files changed, 2 insertions(+), 111 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index fb3222d458..2dce10830d 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1776,109 +1776,9 @@ static const TypeInfo pnv_phb4_root_bus_info = { }, }; -static void pnv_phb4_root_port_reset(DeviceState *dev) -{ - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); - PCIDevice *d = PCI_DEVICE(dev); - uint8_t *conf = d->config; - - rpc->parent_reset(dev); - - pci_byte_test_and_set_mask(conf + PCI_IO_BASE, - PCI_IO_RANGE_MASK & 0xff); - pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, - PCI_IO_RANGE_MASK & 0xff); - pci_set_word(conf + PCI_MEMORY_BASE, 0); - pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); - pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); - pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); - pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ - pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); - pci_config_set_interrupt_pin(conf, 0); -} - -static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) -{ - PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); - PCIDevice *pci = PCI_DEVICE(dev); - PCIBus *bus = pci_get_bus(pci); - PnvPHB *phb = NULL; - Error *local_err = NULL; - - phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), - TYPE_PNV_PHB); - - if (!phb) { - error_setg(errp, "%s must be connected to pnv-phb buses", dev->id); - return; - } - - /* Set unique chassis/slot values for the root port */ - qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id); - qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id); - - rpc->parent_realize(dev, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } -} - -static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); - - dc->desc = "IBM PHB4 PCIE Root Port"; - dc->user_creatable = true; - - device_class_set_parent_realize(dc, pnv_phb4_root_port_realize, - &rpc->parent_realize); - device_class_set_parent_reset(dc, pnv_phb4_root_port_reset, - &rpc->parent_reset); - - k->vendor_id = PCI_VENDOR_ID_IBM; - k->device_id = PNV_PHB4_DEVICE_ID; - k->revision = 0; - - rpc->exp_offset = 0x48; - rpc->aer_offset = 0x100; - - dc->reset = &pnv_phb4_root_port_reset; -} - -static const TypeInfo pnv_phb4_root_port_info = { - .name = TYPE_PNV_PHB4_ROOT_PORT, - .parent = TYPE_PCIE_ROOT_PORT, - .instance_size = sizeof(PnvPHB4RootPort), - .class_init = pnv_phb4_root_port_class_init, -}; - -static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - dc->desc = "IBM PHB5 PCIE Root Port"; - dc->user_creatable = true; - - k->vendor_id = PCI_VENDOR_ID_IBM; - k->device_id = PNV_PHB5_DEVICE_ID; -} - -static const TypeInfo pnv_phb5_root_port_info = { - .name = TYPE_PNV_PHB5_ROOT_PORT, - .parent = TYPE_PNV_PHB4_ROOT_PORT, - .instance_size = sizeof(PnvPHB4RootPort), - .class_init = pnv_phb5_root_port_class_init, -}; - static void pnv_phb4_register_types(void) { type_register_static(&pnv_phb4_root_bus_info); - type_register_static(&pnv_phb5_root_port_info); - type_register_static(&pnv_phb4_root_port_info); type_register_static(&pnv_phb5_type_info); type_register_static(&pnv_phb4_iommu_memory_region_info); } diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 243a079ea7..51821276e9 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -266,7 +266,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->version = PNV_PHB4_VERSION; pecc->phb_type = TYPE_PNV_PHB; pecc->num_phbs = pnv_pec_num_phbs; - pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT; + pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT; } static const TypeInfo pnv_pec_type_info = { @@ -319,7 +319,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data) pecc->version = PNV_PHB5_VERSION; pecc->phb_type = TYPE_PNV_PHB5; pecc->num_phbs = pnv_phb5_pec_num_stacks; - pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT; + pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT; } static const TypeInfo pnv_phb5_pec_type_info = { diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 65a16f2067..8c57d836d1 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -44,16 +44,7 @@ typedef struct PnvPhb4DMASpace { QLIST_ENTRY(PnvPhb4DMASpace) list; } PnvPhb4DMASpace; -/* - * PHB4 PCIe Root port - */ #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root" -#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port" -#define TYPE_PNV_PHB5_ROOT_PORT "pnv-phb5-root-port" - -typedef struct PnvPHB4RootPort { - PCIESlot parent_obj; -} PnvPHB4RootPort; struct PnvPHB4DeviceClass { DeviceClass parent_class; From patchwork Sat May 7 19:06:24 2022 Content-Type: text/plain; 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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id p1-20020a0568301d4100b0060603221270sm2907397oth.64.2022.05.07.12.07.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 12:07:12 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, clg@kaod.org, fbarrat@linux.ibm.com, Daniel Henrique Barboza Subject: [PATCH 17/17] ppc/pnv: remove pecc->rp_model Date: Sat, 7 May 2022 16:06:24 -0300 Message-Id: <20220507190624.507419-18-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220507190624.507419-1-danielhb413@gmail.com> References: <20220507190624.507419-1-danielhb413@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The attribute is always being set to TYPE_PNV_PHB_ROOT_PORT. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4_pec.c | 4 +--- include/hw/pci-host/pnv_phb4.h | 1 - 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 51821276e9..509039bfe6 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -132,7 +132,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, } /* Add a single Root port if running with defaults */ - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), TYPE_PNV_PHB_ROOT_PORT); } static void pnv_pec_realize(DeviceState *dev, Error **errp) @@ -266,7 +266,6 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->version = PNV_PHB4_VERSION; pecc->phb_type = TYPE_PNV_PHB; pecc->num_phbs = pnv_pec_num_phbs; - pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT; } static const TypeInfo pnv_pec_type_info = { @@ -319,7 +318,6 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data) pecc->version = PNV_PHB5_VERSION; pecc->phb_type = TYPE_PNV_PHB5; pecc->num_phbs = pnv_phb5_pec_num_stacks; - pecc->rp_model = TYPE_PNV_PHB_ROOT_PORT; } static const TypeInfo pnv_phb5_pec_type_info = { diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 8c57d836d1..b2c59ea1a0 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -116,7 +116,6 @@ struct PnvPhb4PecClass { uint64_t version; const char *phb_type; const uint32_t *num_phbs; - const char *rp_model; }; /*