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[94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:48:58 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 01/11] clk: qcom: ipq8074: fix NSS core PLL-s Date: Sun, 8 May 2022 12:48:45 +0200 Message-Id: <20220508104855.78804-1-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 541016db3c4b..1a5141da7e23 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .pre_div_val = 0x0, + .pre_div_mask = BIT(12), + .post_div_val = 0x0, + .post_div_mask = GENMASK(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x3e, + .alpha = 0x0, + .alpha_hi = 0x80, + .config_ctl_val = 0x4001055b, + .main_output_mask = BIT(0), + .pre_div_val = 0x0, + .pre_div_mask = GENMASK(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = GENMASK(11, 8), + .vco_mask = GENMASK(21, 20), + .vco_val = 0x0, + .alpha_en_mask = BIT(24), +}; + static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, @@ -4772,7 +4799,17 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { static int gcc_ipq8074_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq8074_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = { From patchwork Sun May 8 10:48:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8147FC4332F for ; Sun, 8 May 2022 10:49:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231561AbiEHKwx (ORCPT ); Sun, 8 May 2022 06:52:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231508AbiEHKwv (ORCPT ); Sun, 8 May 2022 06:52:51 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BD79B7E8; Sun, 8 May 2022 03:49:02 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id g6so21892551ejw.1; Sun, 08 May 2022 03:49:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zvBNJiZ8Rei9kCvvOCgcWJFVne61zQ3dcujbgkMHjus=; b=WJ+EKkRU5lf6p61s+aziGmHhhJaoN8V24tfbJBBUCaiVLPP6kf9ALBeiAk4rNLjpJ+ U4TojXKkJz8tW8fkdWCrGTbu9MadVtzcCvzc9PfJZnpHUp5f2V7JoYCmZpt/eD9+catH qVsX8SjGXV6KocGtJdhZ1ChyHS1Eb9ToZQtIkiCIs2u1k7tGszYsQWAAmoxyowbUjI1y /ey/KZjxysEzLl82tegohB6JqjBXndkyBjaysmJFldQ/tYNSiPPOFHrwvtQZNfaMSf0E w5zk+2QV4EOr3C1f2KFC2XXe00zsqScxsIrmN2TjT6cE8I0IWFcAZwtFVJZ567BscUVa 618w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zvBNJiZ8Rei9kCvvOCgcWJFVne61zQ3dcujbgkMHjus=; b=KkRbZGYvnBlzbDhfWLS/KFIdU+yf3XZ/fV1+T071So6rq7KwuY64rq9voPiSqie1Vy lpfXOYgeQy83Mxwk1ZsJ4UtSDU5WVyHtOkFA45rMDceOOTC7yAD4dbPs3H0s5Tpu0NCO E/JcwL1QwvNeJgsi/4UWQzBV/8GxKvKJiz1NXq7GNS04BpVOFJm3Ej0g4oAB3LNPbkzw SHbqJvsA9rciOVMtlVtkcCIa1CVxkHWMAAipEWgQZDpw0vjVAkvfeqXVybkCMtyzdTXk lVigpu4lvK+bE7TCsPOnB+xr05F2O5J9LpkWsA+9cnu22QGaGU/q88lJEH6k3XcDd0NP NRfQ== X-Gm-Message-State: AOAM530s2UG6d5rbtOGqlFfBTHOWvWtoqgBzeHeuiDkhZsvbL3LbE2rH mER3z8uA+Aw9bR6fPQ5u2F02+Ovc+cBBxg== X-Google-Smtp-Source: ABdhPJyUoOXsFon979o9oEGdhhkSxghUylQHelWz44wXSsaJsArclcqfrG0uqSpjCjKbnWAIm5PtNQ== X-Received: by 2002:a17:907:3da3:b0:6f4:4292:6d6 with SMTP id he35-20020a1709073da300b006f4429206d6mr9987539ejc.162.1652006940398; Sun, 08 May 2022 03:49:00 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:00 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 02/11] clk: qcom: ipq8074: SW workaround for UBI32 PLL lock Date: Sun, 8 May 2022 12:48:46 +0200 Message-Id: <20220508104855.78804-2-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it will cause the wait_for_pll() to timeout and thus return the error indicating that the PLL failed to lock. This is bug in Huayra PLL HW for which SW workaround is to set bit 26 of TEST_CTL register. This is ported from the QCA 5.4 based downstream kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 1a5141da7e23..b4291ba53c78 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4805,6 +4805,9 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + /* SW Workaround for UBI32 Huayra PLL */ + regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, &nss_crypto_pll_config); From patchwork Sun May 8 10:48:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA75AC433F5 for ; Sun, 8 May 2022 10:49:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231983AbiEHKxK (ORCPT ); Sun, 8 May 2022 06:53:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231566AbiEHKwx (ORCPT ); Sun, 8 May 2022 06:52:53 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81E45B7DD; Sun, 8 May 2022 03:49:03 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id p18so13233188edr.7; Sun, 08 May 2022 03:49:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wj10WxHIbo6UUCAP9oJqNfD8dGhuPiu7BAPjORdqN3c=; b=W2scJrPH7Y546YfSLyYIyMgXfyQHp2qyMXq8whSjj8j2+xJkkVDj3EWjOVBnCGc91m HEZVf/DxkWYCzI6J5PUcIHQik+fnLHch0xdnciFl3VSwO80wYrtFEfZlYHdT7e7+GZR7 2ftoJC4s/oHB31264G4FdV/4cbNfhG5PTjxISAOub0yZW6lUgM0xgnib3teSeMhogvNL CQb1gTLl8My01k/05vxI+PuMgfc84zy4jzFedUOYg1Q6soI8zb6ov8n9UmK4wRwWHi96 7TZtShogZZHk8ItUCm1l1FzXo3cq3zT+WumG4Gfio1jmIyR/4z1JxkGrHAAQygd7wxGn peag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wj10WxHIbo6UUCAP9oJqNfD8dGhuPiu7BAPjORdqN3c=; b=MTeVFu06uzNYTUun+9G9YsXXvIlDEULgB3MektBQdnAz11iOu30ndgPvwnHqN9dMhT j6YA8q+yODJ5OZBqR15zziuV9nWi40vpUUxR6ZaNZc+iAdjkd1ISbkyJ6HbZJm5SVEI0 f4n43m4UIZPpfIlswhkNZaU2ShBJ/wv5Ibci9JS4jMLlZb1GPVrv370SQwMDtmW/2YEx DJmFsTm7pSTeNkkz1+AHQh9HH8ZCF2iVnDbeMDMu9JNftpeX+TbRbovhmaG6NAIweonA TryGAZsoLTXwsgNkyQAbRhN3GOdcJsii+WLnyu/vQIPXaVTvRQhu6Q1vnArqqWCdZ7aI 1Wsg== X-Gm-Message-State: AOAM532aX8fg3SPe18oK2dkq0bBGNeJwIZTdMFoSErjHk6wtxsw04dF0 m1KnvV7qiFsQZYSPY8w2/r4= X-Google-Smtp-Source: ABdhPJy9rTN6jNl0tQIuVSuMp8SiY0yYVYp/7QTdUOBAhtt7BjLHKocyvI7uhj5eqwN+BARk6sDVqA== X-Received: by 2002:a50:eb87:0:b0:425:c3e2:17a9 with SMTP id y7-20020a50eb87000000b00425c3e217a9mr12311085edr.109.1652006942072; Sun, 08 May 2022 03:49:02 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:01 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 03/11] clk: qcom: ipq8074: fix NSS port frequency tables Date: Sun, 8 May 2022 12:48:47 +0200 Message-Id: <20220508104855.78804-3-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org NSS port 5 and 6 frequency tables are currently broken and are causing a wide ranges of issue like 1G not working at all on port 6 or port 5 being clocked with 312 instead of 125 MHz as UNIPHY1 gets selected. So, update the frequency tables with the ones from the downstream QCA 5.4 based kernel which has already fixed this. Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index b4291ba53c78..f1017f2e61bd 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1788,8 +1788,10 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_RX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_RX, 5, 0, 0), F(78125000, P_UNIPHY1_RX, 4, 0, 0), F(125000000, P_UNIPHY1_RX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_RX, 1, 0, 0), F(156250000, P_UNIPHY1_RX, 2, 0, 0), F(312500000, P_UNIPHY1_RX, 1, 0, 0), { } @@ -1828,8 +1830,10 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(25000000, P_UNIPHY1_TX, 12.5, 0, 0), + F(25000000, P_UNIPHY0_TX, 5, 0, 0), F(78125000, P_UNIPHY1_TX, 4, 0, 0), F(125000000, P_UNIPHY1_TX, 2.5, 0, 0), + F(125000000, P_UNIPHY0_TX, 1, 0, 0), F(156250000, P_UNIPHY1_TX, 2, 0, 0), F(312500000, P_UNIPHY1_TX, 1, 0, 0), { } @@ -1867,8 +1871,10 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_RX, 5, 0, 0), F(25000000, P_UNIPHY2_RX, 12.5, 0, 0), F(78125000, P_UNIPHY2_RX, 4, 0, 0), + F(125000000, P_UNIPHY2_RX, 1, 0, 0), F(125000000, P_UNIPHY2_RX, 2.5, 0, 0), F(156250000, P_UNIPHY2_RX, 2, 0, 0), F(312500000, P_UNIPHY2_RX, 1, 0, 0), @@ -1907,8 +1913,10 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = { static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = { F(19200000, P_XO, 1, 0, 0), + F(25000000, P_UNIPHY2_TX, 5, 0, 0), F(25000000, P_UNIPHY2_TX, 12.5, 0, 0), F(78125000, P_UNIPHY2_TX, 4, 0, 0), + F(125000000, P_UNIPHY2_TX, 1, 0, 0), F(125000000, P_UNIPHY2_TX, 2.5, 0, 0), F(156250000, P_UNIPHY2_TX, 2, 0, 0), F(312500000, P_UNIPHY2_TX, 1, 0, 0), From patchwork Sun May 8 10:48:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13DBEC433FE for ; Sun, 8 May 2022 10:49:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231886AbiEHKxI (ORCPT ); Sun, 8 May 2022 06:53:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231585AbiEHKw4 (ORCPT ); Sun, 8 May 2022 06:52:56 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 519C8B86F; Sun, 8 May 2022 03:49:06 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id gh6so21929369ejb.0; Sun, 08 May 2022 03:49:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gEM8092vCUXJvD5hNfzZpNzpdrsS4y8FwWR/EIuYhPw=; b=V2SXUx8E0fVhlE+MkGRRMS2T64rJ8iGCDaOKR5zhbyHAkxJnoQ6ODw7Yv3JR/5KMzE HWoLvyZQI+8UGD7Ft7FYFjHX1v0y8eQO/z4XVPC/0MyV1puO2qvbu7YSJyp5exd9KgFP CSozuieZpuvxfnK9WwXKDHUc0ViaQzASxGBfJY464mCsKazK6XaE3OB3UIWH7MPwVeRr nrf0YLeQ61IGKrAozbQOrXvx1pKilIyGBaR+cudvkeUhXejkGAopHXX+v1KrqJ6ktQ2l P24ufNUpEujz5L0wtbnYW0l9X8ZsDteTE3lNetxn1Gr5p/w+1+PUgrK2uGvlTFEQ0vE1 4Cpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gEM8092vCUXJvD5hNfzZpNzpdrsS4y8FwWR/EIuYhPw=; b=C0eEPStUsVYUj6YqicJKDZZ/dGKb9VP9kZq/f69wFn9PvSZp+H1C4fYlUAxH3lTrFA DcxCpiaOkB46dcyZZPMHEzmVEMSff3t5vq/1u7ZZ4Wce78frs4ppSzjAWYqROUN/FDlb cW3TzxK6lJVtBZW7GTBqD/cNctFDF8XqvJavlMBv/al0RObpSDj+24nxMSNnks4bVYwt jyTIknZF13kBLYG2PmWmsni6urDkpA1+MD8tmeb108cXgXKbBhVL47bjK2Hx3tzGPOJy 3Lf24igJc8NHmRY8VHcsidS0/ZsumAHGdOD3njmF7ZmuAw4fD+wNbrASRbqZDsuT4FKO mupA== X-Gm-Message-State: AOAM530WINy5goZvFLOBTdJBASXNIwsQQs+2bhb1sJ+Dcw33m3q5IsmE mqmcj7qvAKznV5yWMWppRBSJ12ymlCeTpQ== X-Google-Smtp-Source: ABdhPJwdJwBI2WCXoRCJczJpkYlJUksipQCWe9odDU+X4rK9UjX7bmcIiag763NvEKJJc8J0Hs2DZg== X-Received: by 2002:a17:906:d54b:b0:6f4:d14b:bb91 with SMTP id cr11-20020a170906d54b00b006f4d14bbb91mr10081969ejc.314.1652006943513; Sun, 08 May 2022 03:49:03 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:03 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v3 04/11] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock Date: Sun, 8 May 2022 12:48:48 +0200 Message-Id: <20220508104855.78804-4-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add binding for the PPE crypto clock in IPQ8074. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 8e2bec1c91bf..5f0928785d7a 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -233,6 +233,7 @@ #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 #define GCC_PCIE0_RCHNG_CLK_SRC 225 #define GCC_PCIE0_RCHNG_CLK 226 +#define GCC_CRYPTO_PPE_CLK 227 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 From patchwork Sun May 8 10:48:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CEF1C433EF for ; Sun, 8 May 2022 10:49:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231967AbiEHKxR (ORCPT ); Sun, 8 May 2022 06:53:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231609AbiEHKw5 (ORCPT ); Sun, 8 May 2022 06:52:57 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37AC8DED7; Sun, 8 May 2022 03:49:07 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id kq17so21883319ejb.4; Sun, 08 May 2022 03:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KNJHJYCxxfdyu7+KWLs4v3umHsmxXP/GIzj4jmPOymA=; b=CxjELPOVikgcjVOxG7YyyykGu9UvsfEDv54V2QwQeq/wT/HSE7mKv+ZhMBK1VQSsdP 39FIM4DBRka467X4y1NeEqmLwL17awfYMJjNjgTerUQeG602OLFA4G8/cgBshFXjRZEe 4tH8nRb4n2kHgGBci+njBD30siRECHKzYAlMFHTV0crAlPkh1x2QUUOnmU3ZL+Z2E9wT GBNgudcKTVHO50vf+3sDB4T1A0glvuqSoksbZuUWY40ffhRssb4D/d4HpzfuxYoPLGdp y4U+khzJP0KWGazJK5uU+46Se7zGV1y+vZ6V84ivFJwHUk1bYltyg472dnYtGq+mKlRg apHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KNJHJYCxxfdyu7+KWLs4v3umHsmxXP/GIzj4jmPOymA=; b=RIKCumN7jgAURCFt8+xhEakkCmekLVEkfMxDkSocV5aZ/DfZjuXPJNiuXCwxhaHM89 djOiLJgbVXOLomrWIx2qCyIaH9z3mkRPpQsyxhSSpTx4Whk07yeK23DlzWFiWOX0tbzp WpyJaeEABn4Lp5h+OOUTFUstczCqBngKvLhCQPcOI77sW9uH6WLhZhZLSJoqEHM+o4TN LfMrPq+rCjfzMZdjAIMKv+onqUrE46FFngQaohrFR7LrZGdxLCG+40zImcyfqwroinVd qw9TqdxUymmvdWK4kwvX/n1gbPDdNHg3Z7y1P1P+w1JAomMEk/vRa9+Qs7ckQhMvWuM4 SG8Q== X-Gm-Message-State: AOAM531sHb9IudUDru4B2ByC4qN0vMMfUBa3ZTaUFepP6lmp+jRZacth KNE6P7BtY0ornprqmkpF4JZNrIMBGk1E0Q== X-Google-Smtp-Source: ABdhPJx4bFCFRoz0wS2CeD69sikc10lLJ83QKVyR0kP7wAwynFMYO5H4p4u9DqfhCTh8XK8RZKRX+A== X-Received: by 2002:a17:906:a08b:b0:6cf:65bc:e7de with SMTP id q11-20020a170906a08b00b006cf65bce7demr10564954ejy.220.1652006945769; Sun, 08 May 2022 03:49:05 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:05 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 05/11] clk: qcom: ipq8074: add PPE crypto clock Date: Sun, 8 May 2022 12:48:49 +0200 Message-Id: <20220508104855.78804-5-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The built-in PPE engine has a dedicated clock for the EIP-197 crypto engine. So, since the required clock currently missing add support for it. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index f1017f2e61bd..c964e43ba68a 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { }, }; +static struct clk_branch gcc_crypto_ppe_clk = { + .halt_reg = 0x68310, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ppe_clk", + .parent_names = (const char *[]){ + "nss_ppe_clk_src" + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { @@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, }; static const struct qcom_reset_map gcc_ipq8074_resets[] = { From patchwork Sun May 8 10:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A666C43217 for ; Sun, 8 May 2022 10:49:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232103AbiEHKxQ (ORCPT ); Sun, 8 May 2022 06:53:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231610AbiEHKw5 (ORCPT ); Sun, 8 May 2022 06:52:57 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7F92DEE3; Sun, 8 May 2022 03:49:07 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id gh6so21929369ejb.0; Sun, 08 May 2022 03:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jRvjrwoDTG2vGn1+XsgjmHuelkhoFakkhEz4+edI7ZE=; b=Qap5WEO7IaF080iuoxxkrpgNLpgEgiF9PhIpfdOyCRkKd0qMoJtiNc9DyVToQ0FNYS hz+gEay8DGfmqmG8dMexZswzr+FPWUGeLSvZwp0bqnJ7bPr5ztUFeuwOrROoLCyxGptV kOksvV1NacDXm36CfZxzKcGO6RZrnl+NqxtNhaysWRj5JM6RL01ENXdPFOyf5MqStd3p h+iHNEpcSrPfo4eeE+BAMY7rAZM91D2n5g78WX2+Q8kRqa1nOhwD9QaR4Iu27/RTnmBP MI3Ytn999waSZ92nMW2nlfKsj/BvaN8oDV95tjqfxm/q+E+grVh0vW3V0DWQokmXEG9M PDyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jRvjrwoDTG2vGn1+XsgjmHuelkhoFakkhEz4+edI7ZE=; b=UlsmVnQcHCzr8RHLcNmwNqEFtzFbXRQ7EiHg02j/Kdd94j/rNQdf7j+SxMsHSs0EyV zDsxk+mJ0lVQvYVLIFCxSNgJusiYb85TPe/8DXXVy4tKvSaD7tXQFA3HEPA1u6LBEb/e j8+O49Ki0pG3Czle6deMRMRiMFpKVXSPHg68m8z0il6xOki7M0pLqnCQaCdF/3lDzsIh SDpT3zQ7UERMsPtM0VBvFjIMYga78yYHAMLNq6UexfPCTAgsifJnHMdYBLfm+YC12VKs lm6C8+CNxtVbJeWR5MQ7+fTqjh7boRmHB6B8WIgipl+ED6+sRP+jTbj8R7OUb+7bDfxp NvAA== X-Gm-Message-State: AOAM533aR8/xsMy212d0JdD4RARuXB9OLwQXGy3cboEItHqItCQD43fa +ohAmSXxJyZ+/rbT8lZIMMjZT8twe8fDMg== X-Google-Smtp-Source: ABdhPJxklFBtaaBdJ1PDtdKt/h7+g9cXSipxIzeW3Vr2CBrluL7R1Wzr7l5XdcXtL+EnJ0gBbV65Sg== X-Received: by 2002:a17:906:2294:b0:6f3:bd02:95a3 with SMTP id p20-20020a170906229400b006f3bd0295a3mr10244746eja.201.1652006947279; Sun, 08 May 2022 03:49:07 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:06 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 06/11] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks Date: Sun, 8 May 2022 12:48:50 +0200 Message-Id: <20220508104855.78804-6-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Currently, attempting to enable the UBI clocks will cause the stuck at off warning to be printed and clk_enable will fail. [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off' Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY flag on UBI clocks, so lets do the same. Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks") Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index c964e43ba68a..85076c1383c7 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -3372,6 +3372,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi0_ahb_clk = { .halt_reg = 0x6820c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6820c, .enable_mask = BIT(0), @@ -3389,6 +3390,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = { static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68200, .enable_mask = BIT(0), @@ -3406,6 +3408,7 @@ static struct clk_branch gcc_ubi0_axi_clk = { static struct clk_branch gcc_ubi0_nc_axi_clk = { .halt_reg = 0x68204, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68204, .enable_mask = BIT(0), @@ -3423,6 +3426,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = { static struct clk_branch gcc_ubi0_core_clk = { .halt_reg = 0x68210, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68210, .enable_mask = BIT(0), @@ -3440,6 +3444,7 @@ static struct clk_branch gcc_ubi0_core_clk = { static struct clk_branch gcc_ubi0_mpt_clk = { .halt_reg = 0x68208, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68208, .enable_mask = BIT(0), @@ -3457,6 +3462,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = { static struct clk_branch gcc_ubi1_ahb_clk = { .halt_reg = 0x6822c, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x6822c, .enable_mask = BIT(0), @@ -3474,6 +3480,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = { static struct clk_branch gcc_ubi1_axi_clk = { .halt_reg = 0x68220, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68220, .enable_mask = BIT(0), @@ -3491,6 +3498,7 @@ static struct clk_branch gcc_ubi1_axi_clk = { static struct clk_branch gcc_ubi1_nc_axi_clk = { .halt_reg = 0x68224, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68224, .enable_mask = BIT(0), @@ -3508,6 +3516,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = { static struct clk_branch gcc_ubi1_core_clk = { .halt_reg = 0x68230, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68230, .enable_mask = BIT(0), @@ -3525,6 +3534,7 @@ static struct clk_branch gcc_ubi1_core_clk = { static struct clk_branch gcc_ubi1_mpt_clk = { .halt_reg = 0x68228, + .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x68228, .enable_mask = BIT(0), From patchwork Sun May 8 10:48:51 2022 Content-Type: text/plain; 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[94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:08 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 07/11] dt-bindings: clocks: qcom,gcc-ipq8074: support power domains Date: Sun, 8 May 2022 12:48:51 +0200 Message-Id: <20220508104855.78804-7-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org GCC inside of IPQ8074 also provides power management via built-in GDSCs. In order to do so, '#power-domain-cells' must be set to 1. Signed-off-by: Robert Marko --- .../devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 98572b4a9b60..e3e236e4ce7d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -27,6 +27,9 @@ properties: '#reset-cells': const: 1 + '#power-domain-cells': + const: 1 + reg: maxItems: 1 @@ -39,6 +42,7 @@ required: - reg - '#clock-cells' - '#reset-cells' + - '#power-domain-cells' additionalProperties: false @@ -49,5 +53,6 @@ examples: reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; ... 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[94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:09 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 08/11] dt-bindings: clock: qcom: ipq8074: add USB GDSCs Date: Sun, 8 May 2022 12:48:52 +0200 Message-Id: <20220508104855.78804-8-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add bindings for the USB GDSCs found in IPQ8074 GCC. Signed-off-by: Robert Marko --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 5f0928785d7a..e4991d303708 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -368,4 +368,7 @@ #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 +#define USB0_GDSC 0 +#define USB1_GDSC 1 + #endif From patchwork Sun May 8 10:48:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54811C433FE for ; Sun, 8 May 2022 10:49:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231857AbiEHKxQ (ORCPT ); Sun, 8 May 2022 06:53:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231756AbiEHKxD (ORCPT ); Sun, 8 May 2022 06:53:03 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CC2CE0CF; Sun, 8 May 2022 03:49:13 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id j6so21837962ejc.13; Sun, 08 May 2022 03:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LhdyFUF6lZ0ZAM234mZVD3RqGmEW+gwWcf23USU26BQ=; b=Lamwd2r87pQHyK9oPjh6gAmpP7nLMeVNiIHKL2taohQDlJOfnFCATD00O4R4FTLWkw RdtMJz4vdiGIaX9ihC0MelO3Tt1rUKktxHr51B9G0A/0FwnCIVGXvd4IfMNDa8+XF3/7 YCkHZppgAi0LFSFCpyMPcI+2wVG0Yfclb4WFlN+f3uG/aLFcVtAbnE0O979lJVJhI57U fJLMUb/UQFo3plXKxfCWurLvLs0PxuZJU70BhTfomfry6Q6ipx6JiBwikm5VK3eVpbFT 5RGy2nT5w/ZmC8qFSjf5YaUL8SyN+Xv/xaDQg1KThp8SGfAjPtjOzbrMe5Id9la+bJsa Sd2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LhdyFUF6lZ0ZAM234mZVD3RqGmEW+gwWcf23USU26BQ=; b=pCQJiTQvOl1stRP/SDJrjQ12xCtDWQAnPn+fJyDDirQKjfnqJhGoRaqPbyoaeHa42h Z69V4r4M1DhxsAQKv4JRh6y+BKMM8ShAxdZ0QWIMmdup43jlBy+9B7c1zFwM2dTXUutg MI0CfikpfFsteyGJ6DXgSBKOF8p9jsG95ov9A1tiMZuPWj6ORDdiRgueRJeySdkh5J+B 8off0LdqYa70GFxlc51oyGcxf45hoTCY6KqTEUXCW2ybck3DU6ssWTeJ4H9wIwJJqDwP j42GD00qMnpDj0McnH1HhMtOvUAeX+CzVd6Ek4rWnUAzXFmQDcLxOwSbaM2iNTd31Cw5 EWxg== X-Gm-Message-State: AOAM533pqefx+RidP61BiL+qI0FOXPEoOfEj8hGvtCKCID809gO4NwDk BH0ODrhpVBUohVsImqBStgc= X-Google-Smtp-Source: ABdhPJxaK1R8JK60+GOYGt4Pk+XE/lRbVgZ3mOIsnkicE3rPNXymgeYtsOvLdXpN11a7+0fXNLnCFg== X-Received: by 2002:a17:907:1c82:b0:6f4:60e5:1ddd with SMTP id nb2-20020a1709071c8200b006f460e51dddmr10116004ejc.274.1652006951691; Sun, 08 May 2022 03:49:11 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:11 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 09/11] clk: qcom: ipq8074: add USB GDSCs Date: Sun, 8 May 2022 12:48:53 +0200 Message-Id: <20220508104855.78804-9-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add GDSC-s for each of the two USB controllers built-in the IPQ8074. Signed-off-by: Robert Marko --- Changes in v2: * Use proper GSDCs instead of raw regmap writes. --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d01436be6d7a..00fe5f066de5 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -166,6 +166,7 @@ config IPQ_LCC_806X config IPQ_GCC_8074 tristate "IPQ8074 Global Clock Controller" + select QCOM_GDSC help Support for global clock controller on ipq8074 devices. Say Y if you want to use peripheral devices such as UART, SPI, diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 85076c1383c7..3204d550ff76 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -22,6 +22,7 @@ #include "clk-alpha-pll.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +#include "gdsc.h" #include "reset.h" enum { @@ -4407,6 +4408,22 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static struct gdsc usb0_gdsc = { + .gdscr = 0x3e078, + .pd = { + .name = "usb0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc usb1_gdsc = { + .gdscr = 0x3f078, + .pd = { + .name = "usb1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static const struct alpha_pll_config ubi32_pll_config = { .l = 0x4e, .config_ctl_val = 0x200d4aa8, @@ -4810,6 +4827,11 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = { [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, }; +static struct gdsc *gcc_ipq8074_gdscs[] = { + [USB0_GDSC] = &usb0_gdsc, + [USB1_GDSC] = &usb1_gdsc, +}; + static const struct of_device_id gcc_ipq8074_match_table[] = { { .compatible = "qcom,gcc-ipq8074" }, { } @@ -4832,6 +4854,8 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), .clk_hws = gcc_ipq8074_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws), + .gdscs = gcc_ipq8074_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs), }; static int gcc_ipq8074_probe(struct platform_device *pdev) From patchwork Sun May 8 10:48:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A7D5C433F5 for ; Sun, 8 May 2022 10:49:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231799AbiEHKxL (ORCPT ); Sun, 8 May 2022 06:53:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231800AbiEHKxE (ORCPT ); Sun, 8 May 2022 06:53:04 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C6F2DEE3; Sun, 8 May 2022 03:49:14 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id bv19so21881437ejb.6; Sun, 08 May 2022 03:49:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jUoVtZp3FHNEmRMS9sjznujtKL5i65I6AtU+XnfV9Fs=; b=f4GzyYd6HYtRXF6KciFTlPYaA33JK/Q6mfxs4NWdjMCwhB8jaLTYzSnL1IbMO6SnEr P2DdfPF+gTY15Ivc2TOYweWtXwtHa5XBaZd9s3o1AgmASjAic7jb7xxTPOlmVMj/YsKv ylo2SziN3IxxK5dQVknA4mtsn4hPF6E+isNPWeG3dR9o638Zw3jLXBB54SB0r5k4Gdz5 P79L3h1nRkkw5/2kvsvA+hqLR80mpH85pzz7fDKrtfFQcDnhOln3Nt9Pf7WdkRgYuLKq mOC+Iu0U/jMrLHz9FH/ID/G5BPkgiNxwYvCbnE6gHRKdpYmlKgYArl6SNz+o3SA6aFFI okgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jUoVtZp3FHNEmRMS9sjznujtKL5i65I6AtU+XnfV9Fs=; b=HuW+L1kvSZZQlFVTqg4zGsbO+wweJmJW9qlAHlAgW5JzE7UCKW4ic7LhwdvJTly/2N tBY9/gZUn6bdzJPOuNb22CTbFCg49noQ7skJQ99fSyJBnL//Ry+uayykh+SeoF8eehtx /Ch6oKktIIoSxnjayJWLlA48JkeUCmJRjatONiyWf/dZTYRm7U3A9J0K8srKrr2ovBwS GKCx6FYp29wqHDhilmDC0eZejDKxi6dfNfgef/TyJFKrXCIh9SBjQ8MWvK5EHiso/Dco 2ymHKF58ZanA5YZCFNPl7+cDiJE9/JtClM0fApkL6+w1stZG5p9L+eUpATmVh4TWkxng 8+uA== X-Gm-Message-State: AOAM531y0GoqV1UvGZGyLlf1Urig1m2xEUxMwji1TvgKu400f/QBFnN8 WfH6vgvspLUZuIaBLUmj1Ug= X-Google-Smtp-Source: ABdhPJwHrnWeHJyOr3Un9oIgcCMs6FjPWnXqEe+cJ7EImhz7Pv1/aJG3470Sr4FeL2+qcJPvql8s7g== X-Received: by 2002:a17:906:6bd7:b0:6f4:e6e4:1d41 with SMTP id t23-20020a1709066bd700b006f4e6e41d41mr10567723ejs.770.1652006953108; Sun, 08 May 2022 03:49:13 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:12 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 10/11] clk: qcom: ipq8074: dont disable gcc_sleep_clk_src Date: Sun, 8 May 2022 12:48:54 +0200 Message-Id: <20220508104855.78804-10-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Once the usb sleep clocks are disabled, clock framework is trying to disable the sleep clock source also. However, it seems that it cannot be disabled and trying to do so produces: [ 245.436390] ------------[ cut here ]------------ [ 245.441233] gcc_sleep_clk_src status stuck at 'on' [ 245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140 [ 245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio [ 245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215 [ 245.463889] Hardware name: Xiaomi AX9000 (DT) [ 245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 245.474307] pc : clk_branch_wait+0x130/0x140 [ 245.481073] lr : clk_branch_wait+0x130/0x140 [ 245.485588] sp : ffffffc009f2bad0 [ 245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000 [ 245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20 [ 245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0 [ 245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7 [ 245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777 [ 245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129 [ 245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001 [ 245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001 [ 245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027 [ 245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026 [ 245.557122] Call trace: [ 245.564229] clk_branch_wait+0x130/0x140 [ 245.566490] clk_branch2_disable+0x2c/0x40 [ 245.570656] clk_core_disable+0x60/0xb0 [ 245.574561] clk_core_disable+0x68/0xb0 [ 245.578293] clk_disable+0x30/0x50 [ 245.582113] dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom] [ 245.585588] platform_remove+0x28/0x60 [ 245.590361] device_remove+0x4c/0x80 [ 245.594179] device_release_driver_internal+0x1dc/0x230 [ 245.597914] device_driver_detach+0x18/0x30 [ 245.602861] unbind_store+0xec/0x110 [ 245.607027] drv_attr_store+0x24/0x40 [ 245.610847] sysfs_kf_write+0x44/0x60 [ 245.614405] kernfs_fop_write_iter+0x128/0x1c0 [ 245.618052] new_sync_write+0xc0/0x130 [ 245.622391] vfs_write+0x1d4/0x2a0 [ 245.626123] ksys_write+0x58/0xe0 [ 245.629508] __arm64_sys_write+0x1c/0x30 [ 245.632895] invoke_syscall.constprop.0+0x5c/0x110 [ 245.636890] do_el0_svc+0xa0/0x150 [ 245.641488] el0_svc+0x18/0x60 [ 245.644872] el0t_64_sync_handler+0xa4/0x130 [ 245.647914] el0t_64_sync+0x174/0x178 [ 245.652340] ---[ end trace 0000000000000000 ]--- So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try to disable the sleep clock. Signed-off-by: Robert Marko --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 3204d550ff76..42d185fe19c8 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -663,6 +663,7 @@ static struct clk_branch gcc_sleep_clk_src = { }, .num_parents = 1, .ops = &clk_branch2_ops, + .flags = CLK_IS_CRITICAL, }, }, }; From patchwork Sun May 8 10:48:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 12842350 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D98EC433EF for ; Sun, 8 May 2022 10:49:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231978AbiEHKxS (ORCPT ); Sun, 8 May 2022 06:53:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231935AbiEHKxK (ORCPT ); Sun, 8 May 2022 06:53:10 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37C51DECA; Sun, 8 May 2022 03:49:16 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id dk23so21875522ejb.8; Sun, 08 May 2022 03:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7p1Ky747M6b7mZG1S1tHMWxma441ZRmxJs8dLDJ9L1E=; b=AJ4N3IqUrdRc0rQ4YUPrVJo2vf4IqnY7XGyLPV0+q5v+vy3/TXyWcH1A5iWPat+eQK HNqTnAquj7KTJc4D3W9mPjChTsjQ3yMfknYy3hG0SktFp4lDWUqLoF3oDnOPnaHb58rG PnXuC58S72Ge2p5kmD3JAYeoK8EJ3OGP4IngaILlZ8fCl3Sm/3Rp/ZkT4UjRNWhajOJc My9w4D7phNHzwQs2RKOF+LEskW5TEb7GqRp6WcAb6eb6XRGMi9Kam5ja0wTMvxG8G/c1 8fNGeKqOVL/h1aDOA/Cr44tB6G2i+gylXp+VkbwAZAm4dU0eQfpHwSgMujQ3pzYuW+oW xtaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7p1Ky747M6b7mZG1S1tHMWxma441ZRmxJs8dLDJ9L1E=; b=nE32qanna1ODC1jLT/YAzU7kzOc1zXFy7PcvcVwf+U8CiOCkBnsUNw1CYFQUzIk5o3 yUZv0jbRNB9gMAoU67O720xvwsvpjgreVksJDtZqlud0z6wGG68avh8pJLI4Pb4vvRDU AcoVeYu70d9UZIPzOlMO1MVrEtsL5DH44Jvzm27iNtXnpfilBapHPkzewpLmC0MmB5bS D5yQI+YUkixSvaT766zSuwphAduG1M54d4X2Q85lSQ8RnBYxhzPqyBHlsobUZCBji3t5 FCrwpSSGsSthI8qhOMNa1y+zwK3oMrPNKs/9xpcDdo0DLc/2I+HEBV6AfThA/IZsz3WW UBsw== X-Gm-Message-State: AOAM531xBy2zkKcA2bUuLT1AEq5EohDGFR20F441CApKZY3yn9SxSuRP lkejoqHHEbfnME8YZ80eJtk= X-Google-Smtp-Source: ABdhPJwSIYliEMNd5yuIHSMUvUw8LUMnPmhuUrimOKGtP7mvXX6S5/PY4uamiZMMv3jcgtAczMvG1A== X-Received: by 2002:a17:906:5616:b0:6f3:8fe2:a8e8 with SMTP id f22-20020a170906561600b006f38fe2a8e8mr10099685ejq.465.1652006954619; Sun, 08 May 2022 03:49:14 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id hg12-20020a1709072ccc00b006f3ef214e0csm3917471ejc.114.2022.05.08.03.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 May 2022 03:49:14 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: Robert Marko Subject: [PATCH v3 11/11] arm64: dts: ipq8074: add USB power domains Date: Sun, 8 May 2022 12:48:55 +0200 Message-Id: <20220508104855.78804-11-robimarko@gmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220508104855.78804-1-robimarko@gmail.com> References: <20220508104855.78804-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add USB power domains provided by GCC GDSCs. Add the required #power-domain-cells to the GCC as well. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index ba81c510dd39..0bc21b0c177f 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -383,6 +383,7 @@ gcc: gcc@1800000 { reg = <0x01800000 0x80000>; #clock-cells = <0x1>; #reset-cells = <0x1>; + #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { @@ -610,6 +611,8 @@ usb_0: usb@8af8800 { <133330000>, <19200000>; + power-domains = <&gcc USB0_GDSC>; + resets = <&gcc GCC_USB0_BCR>; status = "disabled"; @@ -650,6 +653,8 @@ usb_1: usb@8cf8800 { <133330000>, <19200000>; + power-domains = <&gcc USB1_GDSC>; + resets = <&gcc GCC_USB1_BCR>; status = "disabled";