From patchwork Mon May 9 07:24:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 12843084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9741EC433F5 for ; Mon, 9 May 2022 07:24:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 20EF810EF23; Mon, 9 May 2022 07:24:20 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAFC110EF23 for ; Mon, 9 May 2022 07:24:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652081058; x=1683617058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UnqKBSqv0RbsRamhm4DelwHBuEuv8GQru05lB2Man74=; b=URYW/0hzZgVT+j46+3/Srt1GT9bE/cHK4e/3SzCFqoHYioUWgU96awf3 bIHzV0nm+DBmyTh5Ws2n54O5ad6DwXL+qiSiCp26mgQogiJraL2guYY4N BYWxC+Hj4bp9ZS7XMsZ34QV/YA30Sj7UlCWyNp9BZozdDdU8MB/to6HKi c8ybGP3Q9yPUjj16ZEYdhp4YCKkSvthvmhcQ0HJKEBYpuHChvShQrLefv QJB2Z5Zr5nfoxVmgP7vXZR6Da5VhKjVgoZgkn/Ce1eCeP26rDnDePJcbl L+CJgyRMfqfqVDt0EynXvSOBgjWYlTFmbd5z9OCdb/z2lmXWBq9xY1KUb A==; X-IronPort-AV: E=McAfee;i="6400,9594,10341"; a="249503527" X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="249503527" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2022 00:24:18 -0700 X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="710390641" Received: from jparmijo-mobl.amr.corp.intel.com (HELO jhogande-mobl1.ger.corp.intel.com) ([10.251.219.202]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2022 00:24:16 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Date: Mon, 9 May 2022 10:24:03 +0300 Message-Id: <20220509072404.1423018-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509072404.1423018-1-jouni.hogander@intel.com> References: <20220509072404.1423018-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/psr: Use full update In case of area calculation fails X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Pearson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we have some corner cases where area calculation fails. For these sel fetch area calculation ends up having update area as y1 = 0, y2 = 4. Instead of these values safer option is full update. One of such for example is big fb with offset. We don't have usable offset in psr2_sel_fetch_update. Currently it's open what is the proper way to fix this corner case. Use full update for now. v2: Commit message modified Cc: José Roberto de Souza Cc: Mika Kahola Tested-by: Mark Pearson Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 06db407e2749..8c099d24de86 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1770,6 +1770,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, clip_area_update(&pipe_clip, &damaged_area); } + if (pipe_clip.y1 == -1) + full_update = true; + if (full_update) goto skip_sel_fetch_set_loop; From patchwork Mon May 9 07:24:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 12843085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B529C433F5 for ; Mon, 9 May 2022 07:24:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 702E210EF59; Mon, 9 May 2022 07:24:23 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BEF210F00B for ; Mon, 9 May 2022 07:24:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652081062; x=1683617062; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VlgdfH1KeE9uDBlnmJKEu/hhjQ8q6vYgNQTa4ZcHHVs=; b=mxNz5OgEPVrNi/RMLTDoJC598dFo8hravo/EKP2cGYpnA1OPV1TSEoSN F1gCxBa2tLc6a5aAU3HdO6oCM1kvmonofzXnA8P6fIr1bDPUVrjiihqi+ xaqSiVBp6zhVHjFjP2q53Ms1sq8HPB0RVftpAx54RpXwGRAGBMNbyQqPl wA4PSc3XrBEYH7KC0sNox5ysr+OFvxgJLeL3KWaM9c7V7afP4b46EwgRy T6fGKZ45mWppYBoJ/e3wG52xBYTuW+5FEUpC6X25LzjfXJyeC1IuZkElY UYa8ynoc7Do+9pFgk9fR5pY7YxHkb7e6oskqKs3KZmWGUyt9Kwzs/GiVg Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10341"; a="249503539" X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="249503539" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2022 00:24:22 -0700 X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="710390670" Received: from jparmijo-mobl.amr.corp.intel.com (HELO jhogande-mobl1.ger.corp.intel.com) ([10.251.219.202]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2022 00:24:20 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Date: Mon, 9 May 2022 10:24:04 +0300 Message-Id: <20220509072404.1423018-3-jouni.hogander@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509072404.1423018-1-jouni.hogander@intel.com> References: <20220509072404.1423018-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915: Ensure damage clip area is within pipe area X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Pearson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Current update area calculation is not handling situation where e.g. cursor plane is fully or partially outside pipe area. Fix this by checking damage area against pipe_src area using drm_rect_intersect. v2: Set x1 and x2 in damaged_area initialization Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5440 Cc: José Roberto de Souza Cc: Mika Kahola Tested-by: Mark Pearson Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8c099d24de86..ecd062a0fea4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1708,7 +1708,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, */ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { - struct drm_rect src, damaged_area = { .y1 = -1 }; + /* Set damaged_area x1 and x2 for drm_rect_intersect usage */ + struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, + .x2 = INT_MAX }; struct drm_atomic_helper_damage_iter iter; struct drm_rect clip; @@ -1735,20 +1737,23 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, if (old_plane_state->uapi.visible) { damaged_area.y1 = old_plane_state->uapi.dst.y1; damaged_area.y2 = old_plane_state->uapi.dst.y2; - clip_area_update(&pipe_clip, &damaged_area); + if (drm_rect_intersect(&damaged_area, &crtc_state->pipe_src)) + clip_area_update(&pipe_clip, &damaged_area); } if (new_plane_state->uapi.visible) { damaged_area.y1 = new_plane_state->uapi.dst.y1; damaged_area.y2 = new_plane_state->uapi.dst.y2; - clip_area_update(&pipe_clip, &damaged_area); + if (drm_rect_intersect(&damaged_area, &crtc_state->pipe_src)) + clip_area_update(&pipe_clip, &damaged_area); } continue; } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { /* If alpha changed mark the whole plane area as damaged */ damaged_area.y1 = new_plane_state->uapi.dst.y1; damaged_area.y2 = new_plane_state->uapi.dst.y2; - clip_area_update(&pipe_clip, &damaged_area); + if (drm_rect_intersect(&damaged_area, &crtc_state->pipe_src)) + clip_area_update(&pipe_clip, &damaged_area); continue; } @@ -1767,7 +1772,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; - clip_area_update(&pipe_clip, &damaged_area); + + if (drm_rect_intersect(&damaged_area, &crtc_state->pipe_src)) + clip_area_update(&pipe_clip, &damaged_area); } if (pipe_clip.y1 == -1)