From patchwork Mon May 9 08:49:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12843180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1AE4C433EF for ; Mon, 9 May 2022 08:51:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7A8rZPVpZzcc0UQwiUd2DZf0PPv4y6ovbXeJPxILyb0=; b=ERC3TqF4/EFU1/ su33rjZgmklj9NDpwq0ceeW40770rLNE2S++5FPs/P+DTlAwEh2Ir7AlkAUgQ6Bsq1BwbRdxds/d4 vMz7OKkakiCNGr92THvNAccU+L5+L6Pj+A8HtI5SPlz2y3eIfeGBSKl2TsGDk+4slZF60goZsJq4c ui3dWda15rrxgiI/A+oOt9bmtanSo7k8PEPdlUUUaIyIjq/a35Qrut1WBOQFHQkSTuOs3siojKNXO GmKO6aOyOO4ZcLO4OhGnCTHQGuwyDU839u822Yh+7zmjITWpZoDhFJAJyzDxeK6i0r4qslpzuaG4b DtwLEfgEFSSxXmp5Henw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nnz5S-00DDEk-Aq; Mon, 09 May 2022 08:49:51 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nnz5E-00DD8K-7g for linux-arm-kernel@lists.infradead.org; Mon, 09 May 2022 08:49:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1652086175; x=1683622175; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=6lCNDnYJkosgYLV0xK1CqQWOhk+Z+YnHv527i+VzDNc=; b=Ki7RJTVEOmepcsCr07bt1kixKXZ4EKjEsaReSod9Z2MWJwtatB9qmNYI mruN1lzT0dSyQL5LRy5dfD/ZQZI8fgvSEDw4MWIJ5GnmdQ5GMAFNoraSu i58QC/8ggESgBG75HLWfHHib7YQTMmShHpO4iB3Svgmgj/mQttolZA+MR v0B1A+ShjBNE7PGSdbXqOPBFA+nGoVf9X+WFRhKoG9+JF+eedAYtm3t/7 cIEZd6ULpW/GRNCZ5MXnkkSQM0fC6x1hf3P3nz+mpHuynX2y/7aFkGbjk LpL8TVzJl7Um4JeaYbLEnDHqX2VfqhExUtZjCVK2qkKCkIrL8ajBqW/Up g==; X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="163212300" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2022 01:49:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 9 May 2022 01:49:34 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 9 May 2022 01:49:29 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH v2 1/4] dt-bindings: mfd: atmel, flexcom: Convert to json-schema Date: Mon, 9 May 2022 14:19:17 +0530 Message-ID: <20220509084920.14529-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> References: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220509_014936_338556_29F3628C X-CRM114-Status: GOOD ( 17.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the Atmel flexcom device tree bindings to json schema. Signed-off-by: Kavyasree Kotagiri --- .../bindings/mfd/atmel,flexcom.yaml | 92 +++++++++++++++++++ .../devicetree/bindings/mfd/atmel-flexcom.txt | 63 ------------- 2 files changed, 92 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml new file mode 100644 index 000000000000..79ec7ebc7055 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) + +maintainers: + - Kavyasree Kotagiri + +description: + The Atmel Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + const: atmel,sama5d2-flexcom + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + maxItems: 3 + + atmel,flexcom-mode: + description: | + Specifies the flexcom mode as follows: + 1: USART + 2: SPI + 3: I2C. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + - atmel,flexcom-mode + +additionalProperties: false + +patternProperties: + "^serial@[0-9a-f]+$": + description: See atmel-usart.txt for details of USART bindings. + "^spi@[0-9a-f]+$": + description: See ../spi/spi_atmel.txt for details of SPI bindings. + "^i2c@[0-9a-f]+$": + description: See ../i2c/i2c-at91.txt for details of I2C bindings. + +examples: + - | + flx0: flexcom@f8034000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xf8034000 0x200>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xf8034000 0x800>; + atmel,flexcom-mode = <2>; + + spi0: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <19 4 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&flx0_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index 692300117c64..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is chosen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as one for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible = "atmel,sama5d2-flexcom"; - reg = <0xf8034000 0x200>; - clocks = <&flx0_clk>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0xf8034000 0x800>; - atmel,flexcom-mode = <2>; - - spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flx0_default>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&flx0_clk>; - clock-names = "spi_clk"; - atmel,fifo-size = <32>; - - mtd_dataflash@0 { - compatible = "atmel,at25f512b"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; -}; From patchwork Mon May 9 08:49:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 12843188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9D7BC433F5 for ; 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09 May 2022 01:49:44 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 9 May 2022 01:49:42 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 9 May 2022 01:49:37 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH v2 2/4] dt-bindings: mfd: atmel, flexcom: Add lan966 compatible string and mux properties Date: Mon, 9 May 2022 14:19:18 +0530 Message-ID: <20220509084920.14529-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> References: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220509_014943_115757_44E5F7AA X-CRM114-Status: UNSURE ( 9.56 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add lan966 flexcom compatible string and flexcom mux device tree properties. Signed-off-by: Kavyasree Kotagiri --- .../bindings/mfd/atmel,flexcom.yaml | 52 ++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml index 79ec7ebc7055..228c095c84ca 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -16,7 +16,9 @@ description: properties: compatible: - const: atmel,sama5d2-flexcom + enum: + - atmel,sama5d2-flexcom + - microchip,lan966-flexcom reg: maxItems: 1 @@ -57,6 +59,27 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan966-flexcom + + then: + properties: + mux-controls: + minItems: 1 + maxItems: 2 + $ref: /schemas/types.yaml#/definitions/phandle-array + + mux-control-names: + minItems: 1 + $ref: ../mux/mux-consumer.yaml + items: + - const: cs0 + - const: cs1 + patternProperties: "^serial@[0-9a-f]+$": description: See atmel-usart.txt for details of USART bindings. @@ -89,4 +112,31 @@ examples: atmel,fifo-size = <32>; }; }; + + - | + flx3: flexcom@e0064000 { + compatible = "microchip,lan966-flexcom"; + reg = <0xe0064000 0x100>; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0064000 0x800>; + atmel,flexcom-mode = <2>; + mux-controls = <&mux 0>; + mux-control-names = "cs0"; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <0 51 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + pinctrl-0 = <&fc3_b_sck_pins>, <&fc3_b_rxd_pins>, + <&fc3_b_txd_pins>, <&fc_shrd9_pins>; + pinctrl-names = "default"; + atmel,fifo-size = <32>; + }; + }; ... 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Signed-off-by: Kavyasree Kotagiri --- .../mux/microchip,lan966-flx-mux.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml diff --git a/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml new file mode 100644 index 000000000000..63147a2e8f3a --- /dev/null +++ b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/microchip,lan966-flx-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Lan966 Flexcom multiplexer bindings + +maintainers: + - Kavyasree Kotagiri + +description: |+ + The Microchip Lan966 have 5 Flexcoms. Each flexcom has 2 chip-selects + when operating in USART and SPI modes. + Each chip select of each flexcom can be mapped to 21 flexcom shared pins. + Define register offset and pin number to map a flexcom chip-select + to flexcom shared pin. + +allOf: + - $ref: /schemas/mux/mux-controller.yaml# + +properties: + compatible: + const: microchip,lan966-flx-mux + + reg: + maxItems: 1 + + '#mux-control-cells': + const: 1 + + mux-offset-pin: + description: an array of register offset and flexcom shared pin(0-20). + +required: + - compatible + - reg + - '#mux-control-cells' + - mux-offset-pin + +additionalProperties: false + +examples: + - | + mux: mux-controller@e2004168 { + compatible = "microchip,lan966-flx-mux"; + reg = <0xe2004168 0x8>; + #mux-control-cells = <1>; + mux-offset-pin = <0x18 9>; /* 0: flx3 cs0 offset, pin-9 */ + }; +... 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Each flexcom has 2 chip-selects. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri Reported-by: kernel test robot Reported-by: kernel test robot --- arch/arm/mach-at91/Kconfig | 2 + drivers/mfd/atmel-flexcom.c | 55 +++++++++++++++- drivers/mux/Kconfig | 12 ++++ drivers/mux/Makefile | 2 + drivers/mux/lan966-flx.c | 121 ++++++++++++++++++++++++++++++++++++ 5 files changed, 191 insertions(+), 1 deletion(-) create mode 100644 drivers/mux/lan966-flx.c diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 279810381256..26fb0f4e1b79 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -74,6 +74,8 @@ config SOC_LAN966 select DW_APB_TIMER_OF select ARM_GIC select MEMORY + select MULTIPLEXER + select MUX_LAN966 help This enables support for ARMv7 based Microchip LAN966 SoC family. diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 559eb4d352b6..7cfd0fc3f4f0 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -17,6 +17,7 @@ #include #include #include +#include /* I/O register offsets */ #define FLEX_MR 0x0 /* Mode Register */ @@ -28,6 +29,10 @@ #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) +struct atmel_flex_caps { + bool has_flx_mux; +}; + struct atmel_flexcom { void __iomem *base; u32 opmode; @@ -37,6 +42,7 @@ struct atmel_flexcom { static int atmel_flexcom_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + const struct atmel_flex_caps *caps; struct resource *res; struct atmel_flexcom *ddata; int err; @@ -76,13 +82,60 @@ static int atmel_flexcom_probe(struct platform_device *pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); + caps = of_device_get_match_data(&pdev->dev); + if (!caps) { + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); + return -EINVAL; + } + + /* Flexcom Mux */ + if (caps->has_flx_mux && of_property_read_bool(np, "mux-controls")) { + struct mux_control *flx_mux; + struct of_phandle_args args; + int i, count; + + flx_mux = devm_mux_control_get(&pdev->dev, NULL); + if (IS_ERR(flx_mux)) + return PTR_ERR(flx_mux); + + count = of_property_count_strings(np, "mux-control-names"); + for (i = 0; i < count; i++) { + err = of_parse_phandle_with_fixed_args(np, "mux-controls", 1, i, &args); + if (err) + break; + + err = mux_control_select(flx_mux, args.args[0]); + if (!err) { + mux_control_deselect(flx_mux); + } else { + dev_err(&pdev->dev, "Failed to select FLEXCOM mux\n"); + return err; + } + } + } + clk_disable_unprepare(ddata->clk); return devm_of_platform_populate(&pdev->dev); } +static const struct atmel_flex_caps atmel_flexcom_caps = {}; + +static const struct atmel_flex_caps lan966x_flexcom_caps = { + .has_flx_mux = true, +}; + static const struct of_device_id atmel_flexcom_of_match[] = { - { .compatible = "atmel,sama5d2-flexcom" }, + { + .compatible = "atmel,sama5d2-flexcom", + .data = &atmel_flexcom_caps, + }, + + { + .compatible = "microchip,lan966-flexcom", + .data = &lan966x_flexcom_caps, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match); diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig index e5c571fd232c..ea09f474bc2f 100644 --- a/drivers/mux/Kconfig +++ b/drivers/mux/Kconfig @@ -45,6 +45,18 @@ config MUX_GPIO To compile the driver as a module, choose M here: the module will be called mux-gpio. +config MUX_LAN966 + tristate "LAN966 Flexcom multiplexer" + depends on OF || COMPILE_TEST + help + Lan966 Flexcom Multiplexer controller. + + The driver supports mapping 2 chip-selects of each of the lan966 + flexcoms to 21 flexcom shared pins. + + To compile the driver as a module, choose M here: the module will + be called mux-lan966. + config MUX_MMIO tristate "MMIO/Regmap register bitfield-controlled Multiplexer" depends on OF || COMPILE_TEST diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile index 6e9fa47daf56..53a9840d96fa 100644 --- a/drivers/mux/Makefile +++ b/drivers/mux/Makefile @@ -7,10 +7,12 @@ mux-core-objs := core.o mux-adg792a-objs := adg792a.o mux-adgs1408-objs := adgs1408.o mux-gpio-objs := gpio.o +mux-lan966-objs := lan966-flx.o mux-mmio-objs := mmio.o obj-$(CONFIG_MULTIPLEXER) += mux-core.o obj-$(CONFIG_MUX_ADG792A) += mux-adg792a.o obj-$(CONFIG_MUX_ADGS1408) += mux-adgs1408.o obj-$(CONFIG_MUX_GPIO) += mux-gpio.o +obj-$(CONFIG_MUX_LAN966) += mux-lan966.o obj-$(CONFIG_MUX_MMIO) += mux-mmio.o diff --git a/drivers/mux/lan966-flx.c b/drivers/mux/lan966-flx.c new file mode 100644 index 000000000000..2c7dab616a6a --- /dev/null +++ b/drivers/mux/lan966-flx.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LAN966 Flexcom MUX driver + * + * Copyright (c) 2022 Microchip Inc. + * + * Author: Kavyasree Kotagiri + */ + +#include +#include +#include +#include +#include +#include +#include + +#define FLEX_SHRD_MASK 0x1FFFFF +#define LAN966_MAX_CS 21 + +static void __iomem *flx_shared_base; +struct mux_lan966x { + u32 offset; + u32 ss_pin; +}; + +static int mux_lan966x_set(struct mux_control *mux, int state) +{ + struct mux_lan966x *mux_lan966x = mux_chip_priv(mux->chip); + u32 val; + + val = ~(1 << mux_lan966x[state].ss_pin) & FLEX_SHRD_MASK; + writel(val, flx_shared_base + mux_lan966x[state].offset); + + return 0; +} + +static const struct mux_control_ops mux_lan966x_ops = { + .set = mux_lan966x_set, +}; + +static const struct of_device_id mux_lan966x_dt_ids[] = { + { .compatible = "microchip,lan966-flx-mux", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mux_lan966x_dt_ids); + +static int mux_lan966x_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct mux_lan966x *mux_lan966x; + struct mux_chip *mux_chip; + int ret, num_fields, i; + + ret = of_property_count_u32_elems(np, "mux-offset-pin"); + if (ret == 0 || ret % 2) + ret = -EINVAL; + if (ret < 0) + return dev_err_probe(dev, ret, + "mux-offset-pin property missing or invalid"); + num_fields = ret / 2; + + mux_chip = devm_mux_chip_alloc(dev, num_fields, sizeof(*mux_lan966x)); + if (IS_ERR(mux_chip)) + return dev_err_probe(dev, PTR_ERR(mux_chip), + "failed to allocate mux_chips\n"); + + mux_lan966x = mux_chip_priv(mux_chip); + + flx_shared_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(flx_shared_base)) + return dev_err_probe(dev, PTR_ERR(flx_shared_base), + "failed to get flexcom shared base address\n"); + + for (i = 0; i < num_fields; i++) { + struct mux_control *mux = &mux_chip->mux[i]; + u32 offset, shared_pin; + + ret = of_property_read_u32_index(np, "mux-offset-pin", + 2 * i, &offset); + if (ret == 0) + ret = of_property_read_u32_index(np, "mux-offset-pin", + 2 * i + 1, + &shared_pin); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to read mux-offset-pin property: %d", i); + + if (shared_pin >= LAN966_MAX_CS) + return -EINVAL; + + mux_lan966x[i].offset = offset; + mux_lan966x[i].ss_pin = shared_pin; + + mux->states = LAN966_MAX_CS; + } + + mux_chip->ops = &mux_lan966x_ops; + + ret = devm_mux_chip_register(dev, mux_chip); + if (ret < 0) + return ret; + + return 0; +} + +static struct platform_driver mux_lan966x_driver = { + .driver = { + .name = "lan966-mux", + .of_match_table = of_match_ptr(mux_lan966x_dt_ids), + }, + .probe = mux_lan966x_probe, +}; + +module_platform_driver(mux_lan966x_driver); + +MODULE_DESCRIPTION("LAN966 Flexcom multiplexer driver"); +MODULE_AUTHOR("Kavyasree Kotagiri "); +MODULE_LICENSE("GPL v2"); +