From patchwork Mon May 9 14:36:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12843697 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 043B6C433F5 for ; Mon, 9 May 2022 14:36:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237419AbiEIOkk (ORCPT ); Mon, 9 May 2022 10:40:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237408AbiEIOki (ORCPT ); Mon, 9 May 2022 10:40:38 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 783781BA8F2 for ; Mon, 9 May 2022 07:36:43 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id v64-20020a1cac43000000b0038cfd1b3a6dso10877151wme.5 for ; Mon, 09 May 2022 07:36:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=solid-run-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yPyFcCAqsBcaZbtE1X5DjA7G79Cug8Z1WeFCxfEjFlo=; b=TnAJo0TSbSssofJ/+UOs/L2Sd05RiqqcB0xVFZixDATsXtGCFOtpGZ90WxyTEODTh1 T3DNynS8287uYEoZu2sLBd8fdUnXCCEk/xO1OdafiCHFG0C7Plijv4H9i7sonu6KobAr 8V5QAv7E8D6cYfgOC7lW6jDQnwRe7Tqo8Gpb8JWHXbyx1QbkvUfS89hcfQKikDhEBDNf SEGY4hTUuEbWpeQkubMx9HeHywwegJRNQvO6BNUx61nGV95PCY6kqLaVHujg2mmDhEop 4GNx6hy7kUfWegaPqTo2QzUsIfJMWKxJf4Feqnh5qB7IAnrc6tAYI4jRXKaLQctMsdVg vs8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yPyFcCAqsBcaZbtE1X5DjA7G79Cug8Z1WeFCxfEjFlo=; b=rKg3FtfGu0ny972idqqxspu1Wna7Ryv7WcwRT35iezwfvg/hIsMN1RzXhWfJrYXc5h FnlCjOCbIXULLZw4ln90ZxLWDyLaG1bmYaX6Ev9X9oA65eas7oQ36eLvR3jEFHp0bcxe k8qkXVZBfx1psDaRxA/HCQinVBHNrD1Yfr8DFNrFOZZ3SK9o2TFGgRJK5BlVSNoaWrSi F7e67LmJYFUCjezH+VLS2J7kgn4Uta6ifRf7R2AW9hFY6uHwFoPz9CpcGpMDjPh0/J4V jSDDbQC4TEX+5Xi3MnLXIRdjkF2TpfBz0Nfw6a/4N9R9SJIOL3/ispx6HHNv/xHymjyA iU8Q== X-Gm-Message-State: AOAM531IlTF5eChLMyJXmAMmniV06S2CG3k7alRzprNyq6vZ140bBcbB Cp6BLPQc62y2OzEYyaA1688zXYGf1IF6PHr34yF2vA== X-Google-Smtp-Source: ABdhPJwuhSG6FUo3GYajEjDPeKw30Pi/VtO+YYqofICsgTOPsR3fZeL7GgnL2c+WPXPwbtsg7vUwUw== X-Received: by 2002:a7b:c5d0:0:b0:389:fe85:3d79 with SMTP id n16-20020a7bc5d0000000b00389fe853d79mr23513603wmk.77.1652107001657; Mon, 09 May 2022 07:36:41 -0700 (PDT) Received: from josua-work.lan (bzq-82-81-222-124.cablep.bezeqint.net. [82.81.222.124]) by smtp.gmail.com with ESMTPSA id x18-20020adfdd92000000b0020c5253d915sm11121155wrl.97.2022.05.09.07.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 07:36:41 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Michael Hennerich , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Alexandru Ardelean Subject: [PATCH v4 1/3] dt-bindings: net: adin: document phy clock output properties Date: Mon, 9 May 2022 17:36:33 +0300 Message-Id: <20220509143635.26233-2-josua@solid-run.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220509143635.26233-1-josua@solid-run.com> References: <20220428082848.12191-1-josua@solid-run.com> <20220509143635.26233-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add DT properties to configure both pins. Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski --- V3 -> V4: changed type of adi,phy-output-reference-clock to boolean V1 -> V2: changed clkout property to enum V1 -> V2: added property for CLK25_REF pin .../devicetree/bindings/net/adi,adin.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml index 1129f2b58e98..cc4f128222ba 100644 --- a/Documentation/devicetree/bindings/net/adi,adin.yaml +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml @@ -36,6 +36,23 @@ properties: enum: [ 4, 8, 12, 16, 20, 24 ] default: 8 + adi,phy-output-clock: + description: Select clock output on GP_CLK pin. Three clocks are available: + A 25MHz reference, a free-running 125MHz and a recovered 125MHz. + The phy can also automatically switch between the reference and the + respective 125MHz clocks based on its internal state. + $ref: /schemas/types.yaml#/definitions/string + enum: + - 25mhz-reference + - 125mhz-free-running + - 125mhz-recovered + - adaptive-free-running + - adaptive-recovered + + adi,phy-output-reference-clock: + description: Enable 25MHz reference clock output on CLK25_REF pin. + type: boolean + unevaluatedProperties: false examples: From patchwork Mon May 9 14:36:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12843699 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21587C433EF for ; Mon, 9 May 2022 14:36:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237425AbiEIOkn (ORCPT ); Mon, 9 May 2022 10:40:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237418AbiEIOkj (ORCPT ); Mon, 9 May 2022 10:40:39 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D09D1C6C9E for ; Mon, 9 May 2022 07:36:45 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id x18so19784095wrc.0 for ; Mon, 09 May 2022 07:36:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=solid-run-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HoVmVQwfiBi2YHILDcYtwP/fJDbARk6SD+ZYiz3y2VM=; b=BjYFb30KozwqY4XK9gTRnLuy2y15Tj2yMC4zaoJUCgbgnG1gIbX8abvJwASN29bY2d ZKH4Pad/3uES7T5p9q/1K/J8wbjn1ihVMiBy5sL71w8qE5wxIynO69/ee16SLUSPgAhU B2byfuL8NZvbDLAN3qZQ88UmiQmPbb+JddVIXtLKs0fyV5VooKoaUd5uNE0lZLaZ+mSR i9yLJuNK50GXFA49Fbo/TVQ8tBeBoojndgAQMz6W+d82RhIyI6PxvLVaeqg+u58vlRDQ aDAPjZARJBl5P1wgLO+snqXGm6nBFMB64eGjVow0YOAfS0o8hcu9gTpMYOap/A84XouZ tTQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HoVmVQwfiBi2YHILDcYtwP/fJDbARk6SD+ZYiz3y2VM=; b=Nad6wlO3iEFObX6PHRCgBCW4ZeYoBhPRb2Lm0A9Oi4DEYwL5xPkkiPRT+aij859NRR uwPAgSFM51OTDKxK1s4qCZz7lVAAQIdP4qmtY90XG+dtvT9LP3cDiHXLZP69lmUWmcZn CL/3c9CyiKt1ckkd/HXJMJJxim43xcG5WcY7mhg8plRagrsx23iquN2JdAKdktMdrxsn HVZHISREvr7DGxDYqsKM62lK/bSGfiXhjIx1KKwIPNdMA+pCKvJe/JV7AP8TyZsAMOcj TDY6FrdpGyV8N+Aw73F5XgSBqhWdlwWii7XQqZDCSLxR3yVJmVDrgfpvbgpyb86tZdya QBmA== X-Gm-Message-State: AOAM532FVPP4xMAWzgiChpHNe4HZIMBFNKTygBDIYNoeN0yxesVG3F6Z 4l619ys6WLu7/MHWzeQdabz3kdYWexMZh9OhwbZWGA== X-Google-Smtp-Source: ABdhPJw0b20AEi3wemMqAPHZryCPGjaTQID/2ifnOW7RGtSDsioG9CmmFqgS5mQR0BJ4iLsSzrix5Q== X-Received: by 2002:a5d:56c8:0:b0:20a:d4a1:94de with SMTP id m8-20020a5d56c8000000b0020ad4a194demr13927858wrw.268.1652107003479; Mon, 09 May 2022 07:36:43 -0700 (PDT) Received: from josua-work.lan (bzq-82-81-222-124.cablep.bezeqint.net. [82.81.222.124]) by smtp.gmail.com with ESMTPSA id x18-20020adfdd92000000b0020c5253d915sm11121155wrl.97.2022.05.09.07.36.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 07:36:43 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Michael Hennerich , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Subject: [PATCH v4 2/3] net: phy: adin: add support for clock output Date: Mon, 9 May 2022 17:36:34 +0300 Message-Id: <20220509143635.26233-3-josua@solid-run.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220509143635.26233-1-josua@solid-run.com> References: <20220428082848.12191-1-josua@solid-run.com> <20220509143635.26233-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The ADIN1300 supports generating certain clocks on its GP_CLK pin, as well as providing the reference clock on CLK25_REF. Add support for selecting the clock via device-tree properties. Co-developed-by: Alvaro Karsz Signed-off-by: Alvaro Karsz Signed-off-by: Josua Mayer --- V3 -> V4: fix coding style violations reported by Andrew and checkpatch V2 -> V3: fix integer-as-null-pointer compiler warning V1 -> V2: revised dts property name for clock(s) V1 -> V2: implemented all 6 bits in the clock configuration register drivers/net/phy/adin.c | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c index 5ce6da62cc8e..1341249d8d2c 100644 --- a/drivers/net/phy/adin.c +++ b/drivers/net/phy/adin.c @@ -99,6 +99,15 @@ #define ADIN1300_GE_SOFT_RESET_REG 0xff0c #define ADIN1300_GE_SOFT_RESET BIT(0) +#define ADIN1300_GE_CLK_CFG_REG 0xff1f +#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0) +#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5) +#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4) +#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3) +#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2) +#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1) +#define ADIN1300_GE_CLK_CFG_25 BIT(0) + #define ADIN1300_GE_RGMII_CFG_REG 0xff23 #define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6) #define ADIN1300_GE_RGMII_RX_SEL(x) \ @@ -433,6 +442,37 @@ static int adin_set_tunable(struct phy_device *phydev, } } +static int adin_config_clk_out(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + const char *val = NULL; + u8 sel = 0; + + device_property_read_string(dev, "adi,phy-output-clock", &val); + if (!val) { + /* property not present, do not enable GP_CLK pin */ + } else if (strcmp(val, "25mhz-reference") == 0) { + sel |= ADIN1300_GE_CLK_CFG_25; + } else if (strcmp(val, "125mhz-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_FREE_125; + } else if (strcmp(val, "125mhz-recovered") == 0) { + sel |= ADIN1300_GE_CLK_CFG_RCVR_125; + } else if (strcmp(val, "adaptive-free-running") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_FREE; + } else if (strcmp(val, "adaptive-recovered") == 0) { + sel |= ADIN1300_GE_CLK_CFG_HRT_RCVR; + } else { + phydev_err(phydev, "invalid adi,phy-output-clock\n"); + return -EINVAL; + } + + if (device_property_read_bool(dev, "adi,phy-output-reference-clock")) + sel |= ADIN1300_GE_CLK_CFG_REF_EN; + + return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG, + ADIN1300_GE_CLK_CFG_MASK, sel); +} + static int adin_config_init(struct phy_device *phydev) { int rc; @@ -455,6 +495,10 @@ static int adin_config_init(struct phy_device *phydev) if (rc < 0) return rc; + rc = adin_config_clk_out(phydev); + if (rc < 0) + return rc; + phydev_dbg(phydev, "PHY is using mode '%s'\n", phy_modes(phydev->interface)); From patchwork Mon May 9 14:36:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 12843700 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A008C433EF for ; Mon, 9 May 2022 14:37:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237424AbiEIOlK (ORCPT ); Mon, 9 May 2022 10:41:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237417AbiEIOkk (ORCPT ); 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[82.81.222.124]) by smtp.gmail.com with ESMTPSA id x18-20020adfdd92000000b0020c5253d915sm11121155wrl.97.2022.05.09.07.36.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 07:36:44 -0700 (PDT) From: Josua Mayer To: netdev@vger.kernel.org Cc: alvaro.karsz@solid-run.com, Josua Mayer , Russell King , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Subject: [PATCH v4 3/3] ARM: dts: imx6qdl-sr-som: update phy configuration for som revision 1.9 Date: Mon, 9 May 2022 17:36:35 +0300 Message-Id: <20220509143635.26233-4-josua@solid-run.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220509143635.26233-1-josua@solid-run.com> References: <20220428082848.12191-1-josua@solid-run.com> <20220509143635.26233-1-josua@solid-run.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Since SoM revision 1.9 the PHY has been replaced with an ADIN1300, add an entry for it next to the original. As Russell King pointed out, additional phy nodes cause warnings like: mdio_bus 2188000.ethernet-1: MDIO device at address 1 is missing To avoid this the new node has its status set to disabled. U-Boot will be modified to enable the appropriate phy node after probing. The existing ar8035 nodes have to stay enabled by default to avoid breaking existing systems when they update Linux only. Co-developed-by: Alvaro Karsz Signed-off-by: Alvaro Karsz Signed-off-by: Josua Mayer --- V2 -> V3: new phy node status set disabled V1 -> V2: changed dts property name arch/arm/boot/dts/imx6qdl-sr-som.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi index f86efd0ccc40..ce543e325cd3 100644 --- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi @@ -83,6 +83,16 @@ ethernet-phy@4 { qca,clk-out-frequency = <125000000>; qca,smarteee-tw-us-1g = <24>; }; + + /* + * ADIN1300 (som rev 1.9 or later) is always at address 1. It + * will be enabled automatically by U-Boot if detected. + */ + ethernet-phy@1 { + reg = <1>; + adi,phy-output-clock = "125mhz-free-running"; + status = "disabled"; + }; }; };