From patchwork Tue May 10 07:52:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 12844640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0406C433EF for ; Tue, 10 May 2022 07:54:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Tk/tHtbnVncixRNaaqi5Per0siVT1jzEpxH6xfX/dFc=; b=PcQ+L3TRE+nIGJ Opdfx18F9l6R/7xgY34rXCf0RpCwdV050p+337t9wCs+WQQVqR5CkyCjtRXCjl3HjV0wn/4a167Pe qYpifE1GLJEnUX9HF+QOJeqoYINZnA9QCimW06rtIOeVMd/oyR/BQxfR1Kvgk76THt/9yWRNhllmV Ogj4hTT5buXtqykZpnLvziEDj6Jdulb+UG4Nkwez0ZJn7ynV1Hn5IcUktsEBTWBzeOrGkWI/JwoNm ropc49P4JOTiza4EFoc51mAzv/F20TrTyXH9ByqHXnkIuL5SsjGtbOSsAgjpKrY7LnFhqaa0rqsBd hh5QsCESsKOy2XEVYm9Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1noKgC-000S4e-Fw; Tue, 10 May 2022 07:53:12 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1noKfp-000RuW-Gs; Tue, 10 May 2022 07:52:51 +0000 X-UUID: f3858e8af8aa4f5482b2b8888f5c62a3-20220510 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:f511997c-e923-46a4-b203-98c4827fec2e, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9, CLOUDID:b752df16-2e53-443e-b81a-655c13977218, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: f3858e8af8aa4f5482b2b8888f5c62a3-20220510 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1543770739; Tue, 10 May 2022 00:52:41 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 10 May 2022 00:52:40 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 10 May 2022 15:52:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 10 May 2022 15:52:38 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , , Allen-KH Cheng Subject: [PATCH v10 1/4] dt-bindings: timer: Add compatible for Mediatek MT8186 Date: Tue, 10 May 2022 15:52:30 +0800 Message-ID: <20220510075233.5426-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220510075233.5426-1-allen-kh.cheng@mediatek.com> References: <20220510075233.5426-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220510_005249_635375_C8979B4B X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Allen-KH Cheng This commit adds dt-binding documentation of timer for Mediatek MT8186 SoC Platform. Signed-off-by: Allen-KH Cheng Acked-by: Rob Herring --- Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index fbd76a8e023b..6f1f9dba6e88 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -23,6 +23,7 @@ Required properties: For those SoCs that use SYST * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) + * "mediatek,mt8186-timer" for MT8186 compatible timers (SYST) * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST) * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) From patchwork Tue May 10 07:52:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 12844639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8A7DC433F5 for ; Tue, 10 May 2022 07:54:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LYkd7Vo0eK0xUwEqzBBaKJJSz12jI+sK+r80w2qVZoo=; b=Fp/KuWU8VrFZl0 kyECbcQs15wV80lpC08wbclhbXilnnloDS4OTT/gp/d6CnPc0OZXwtBkp9/CG1psazsiTDilDaxcu bHuZWCEXbORlrdq/vNxqHMmXZbpMEOHbWS1MPrjU+N6d+qRVmIxIReR0t8a9W6VodFHTZjLtJSm73 PHYrRu1DsjizY/VEUA0TNAM3tilLOyO0EALEcwX7N5iItuBqZV0OzLBQzoc7yl5HMK6ytJ/PzmVDc bIEF9QCeGHD2s5fOW12xFzXg6L7MxzaecGDUnBJdscIQNHPdOtci7rLrV8Xi40yvYUH7ZHMXzVet4 pZFqxD7VppsfHrPlF7QQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1noKg2-000S0U-VI; Tue, 10 May 2022 07:53:03 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1noKfp-000RuM-Gs; Tue, 10 May 2022 07:52:50 +0000 X-UUID: 94de16e76fce4d1b89855431e027bc85-20220510 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:14d212c6-d133-4c3c-8194-81824fd7d4b6, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9, CLOUDID:b652df16-2e53-443e-b81a-655c13977218, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 94de16e76fce4d1b89855431e027bc85-20220510 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 11229631; Tue, 10 May 2022 00:52:42 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 10 May 2022 00:52:40 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 10 May 2022 15:52:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 10 May 2022 15:52:39 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , , Allen-KH Cheng Subject: [PATCH v10 2/4] dt-bindings: arm: mediatek: Add mt8186 pericfg compatible Date: Tue, 10 May 2022 15:52:31 +0800 Message-ID: <20220510075233.5426-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220510075233.5426-1-allen-kh.cheng@mediatek.com> References: <20220510075233.5426-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220510_005249_624047_9DCA443A X-CRM114-Status: UNSURE ( 9.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mt8186 pericfg compatible to binding document. Signed-off-by: Allen-KH Cheng Acked-by: Rob Herring --- .../devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 611f666f359d..8585f6f18f69 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8186-pericfg - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon From patchwork Tue May 10 07:52:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 12844652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB121C433F5 for ; Tue, 10 May 2022 08:04:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dhKNdn7lqjqTqqmki1mdX8xwr+rbKPDsQoQOi/R8dfg=; b=i/pwuN0b2fhwIP J5hCaJqF6XJBI61ibFkwJOdD4CnM64upJhb9+yipr1XY2HUl6S10rZ1BT+uXHGz4AsMlLXvxeYFgE eUfdO9COn/0XP4ijl3hOIiNffvycwV4gssHE+P8+Y8eQBDl5jKpInZnU4RliYQ1B5ta5pPUbPUOwT DxqcC0yUOQ5wZKLyQCJAtG4+9X9UL4xkOp0Lr79VTHgUsZSVdyqXQVSKq/JLekBIPziYDhGYmmr9A ooiKq5j2IaRXcC1Z5owmJwRpdKH8Zk8yGIRZRbU4CM8XhaWwddmNK0X0VppDChdOsxDKuGvAwGzsE QIcnUrMtWj7OgHX0ZIdA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1noKpe-000VAf-ME; Tue, 10 May 2022 08:02:59 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1noKpY-000V8y-9i; Tue, 10 May 2022 08:02:53 +0000 X-UUID: 27d7bfa055054259a90d4b5611d49ead-20220510 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:07c45a71-7bde-4e4b-b36c-fecb3a8076e0, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9, CLOUDID:8bd7df16-2e53-443e-b81a-655c13977218, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 27d7bfa055054259a90d4b5611d49ead-20220510 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 873827342; Tue, 10 May 2022 01:02:48 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 10 May 2022 00:52:47 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 10 May 2022 15:52:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 10 May 2022 15:52:45 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , , Allen-KH Cheng Subject: [PATCH v10 3/4] dt-bindings: arm: Add compatible for MediaTek MT8186 Date: Tue, 10 May 2022 15:52:32 +0800 Message-ID: <20220510075233.5426-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220510075233.5426-1-allen-kh.cheng@mediatek.com> References: <20220510075233.5426-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220510_010252_425223_BE4584F1 X-CRM114-Status: UNSURE ( 9.79 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This commit adds dt-binding documentation for the MediaTek MT8186 reference board. Signed-off-by: Allen-KH Cheng Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 4a2bd9759c47..5a29b7b381ef 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -131,6 +131,10 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8186-evb + - const: mediatek,mt8186 - items: - enum: - mediatek,mt8192-evb From patchwork Tue May 10 08:12:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 12844659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DB6CC433EF for ; Tue, 10 May 2022 08:17:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=0HFio9CN9anrfVp4yIh1BaHRWt3V93cRCwaOZobQywA=; b=1VMQpieV/B5tUg OS+ED53BfUk770guILO7bulRcq9efc7qcfBwXGVbi/+E6D8tGEZjuJVUFXSV+GtU4vMNoQqPmB9GP NFLPAN9mNp9npNYCcSGV061Ze4qoqQ6fpKVg+X+p0kl0r8JyrhFJnzAo8S95uRZ3gWMb5jwuSTv3E 8c8RS1c4Lswj03TYnrwRPrQhP+zd6Q5V3BBIr3+92MAq1+3BowzIthlUcdufn5sjAqLhrC4QSIlL/ kSZpeswwrA6iB3R+mxTTY3+Vk0JdFTMj3KFxyT0xl/z3ovwyocTkbW8f2oZ1cVE+MOFCeVDQPd5Q7 m1PYuV+f61pl0SpW9QGw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1noL2h-000ZLA-BA; Tue, 10 May 2022 08:16:27 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1noL2T-000ZIg-VP; Tue, 10 May 2022 08:16:17 +0000 X-UUID: a8eb346424da4c038f5329495de7f680-20220510 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4, REQID:6ef945f8-f7df-4d5a-bacc-7db9d86d2b01, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9, CLOUDID:7f2c40b3-56b5-4c9e-8d83-0070b288eb6a, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: a8eb346424da4c038f5329495de7f680-20220510 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1992255060; Tue, 10 May 2022 01:16:08 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 10 May 2022 01:12:29 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 10 May 2022 16:12:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 10 May 2022 16:12:27 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski CC: , , , , , "Chen-Yu Tsai" , Ryder Lee , , Allen-KH Cheng , "Allen-KH Cheng" Subject: [PATCH v10 4/4] arm64: dts: Add MediaTek SoC MT8186 dts and evaluation board and Makefile Date: Tue, 10 May 2022 16:12:24 +0800 Message-ID: <20220510081224.17679-1-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220510_011614_073781_9D3AF88D X-CRM114-Status: GOOD ( 14.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add basic chip support for MediaTek MT8186. Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 232 +++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 996 ++++++++++++++++++++ 3 files changed, 1229 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c7d4636a2cb7..50a2c58c5f56 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -37,6 +37,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts new file mode 100644 index 000000000000..3e8018c1e802 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" + +/ { + model = "MediaTek MT8186 evaluation board"; + compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <8000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + i2c-scl-internal-delay-ns = <10000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + status = "okay"; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; + status = "okay"; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_pins>; + status = "okay"; +}; + +&i2c9 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_pins>; + status = "okay"; +}; + +&pio { + i2c0_pins: i2c0{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c1_pins: i2c1{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c2_pins: i2c2{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c3_pins: i2c3{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c4_pins: i2c4{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c5_pins: i2c5{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c6_pins: i2c6{ + pins-sda-scl { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c7_pins: i2c7{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c8_pins: i2c8{ + pins-sda-scl { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; + + i2c9_pins: i2c9{ + pins-sda-scl { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + input-enable; + }; + }; +}; + +&u3phy0 { + status="okay"; +}; + +&u3phy1 { + status="okay"; +}; + +&uart0 { + status = "okay"; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi new file mode 100644 index 000000000000..69b764e32b47 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -0,0 +1,996 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Allen-KH Cheng + */ +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8186"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2000000000>; + capacity-dmips-mhz = <382>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2050000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2050000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <1600>; + }; + + cpu_off_b: cpu-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <100>; + min-residency-us = <1400>; + }; + + cluster_off_l: cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <2100>; + }; + + cluster_off_b: cluster-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010001>; + local-timer-stop; + entry-latency-us = <100>; + exit-latency-us = <250>; + min-residency-us = <1900>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + clk13m: oscillator-13m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <13000000>; + clock-output-names = "clk13m"; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + }; + + mcusys: syscon@c53a000 { + compatible = "mediatek,mt8186-mcusys", "syscon"; + reg = <0 0xc53a000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8186-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8186-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8186-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8186-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x0200>, + <0 0x10002200 0 0x0200>, + <0 0x10002400 0 0x0200>, + <0 0x10002600 0 0x0200>, + <0 0x10002A00 0 0x0200>, + <0 0x10002C00 0 0x0200>, + <0 0x1000B000 0 0x1000>; + reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", + "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 185>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8186-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { + reg = ; + clocks = <&topckgen CLK_TOP_MFG>; + clock-names= "mfg00"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG1 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names= "csirx_top0", "csirx_top1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_ADSP_AO { + reg = ; + clocks = <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + clock-names= "adsp_ao0", "adsp_ao1"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_CONN_ON { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_DIS { + reg = ; + clocks = <&topckgen CLK_TOP_DISP>, + <&topckgen CLK_TOP_MDP>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names= "dis0", "dis1", "dis-0", "dis-1", + "dis-2", "dis-3"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names= "vdec0", "vdec-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>, + <&topckgen CLK_TOP_SENINF2>, + <&topckgen CLK_TOP_SENINF3>, + <&topckgen CLK_TOP_CAMTM>, + <&camsys CLK_CAM2MM_GALS>; + clock-names= "cam0", "cam1", "cam2", "cam3", + "cam4", "cam5", "cam-0"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { + reg = ; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IMG { + reg = ; + clocks = <&topckgen CLK_TOP_IMG1>, + <&imgsys1 CLK_IMG1_GALS_IMG1>; + clock-names = "img0", "img-0"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8186_POWER_DOMAIN_IMG2 { + reg = ; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8186_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS_IPE>; + clock-names= "ipe0", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_VENC>, + <&vencsys CLK_VENC_CKE1_VENC>; + clock-names= "venc0", "venc-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8186_POWER_DOMAIN_WPE { + reg = ; + clocks = <&topckgen CLK_TOP_WPE>, + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; + clock-names= "wpe0", "wpe-0", "wpe-1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8186-wdt", + "mediatek,mt6589-wdt"; + mediatek,disable-extrst; + reg = <0 0x10007000 0 0x1000>; + #reset-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8186-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8186-pwrap", "syscon"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8186-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&clk13m>; + }; + + scp: scp@10500000 { + compatible = "mediatek,mt8186-scp"; + reg = <0 0x10500000 0 0x40000>, + <0 0x105c0000 0 0x19080>; + reg-names = "sram", "cfg"; + interrupts = ; + }; + + nor_flash: spi@11000000 { + compatible = "mediatek,mt8186-nor", "mediatek,mt8173-nor"; + reg = <0 0x11000000 0 0x1000>; + clocks = <&topckgen CLK_TOP_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_SPINOR>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, + <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; + clock-names = "spi", "sf", "axi", "axi_s"; + assigned-clocks = <&topckgen CLK_TOP_SPINOR>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + #io-channel-cells = <1>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names = "main"; + status = "okay"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c0: i2c0@11007000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10200100 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c1: i2c1@11008000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11008000 0 0x1000>, + <0 0x10200200 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c2: i2c2@11009000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11009000 0 0x1000>, + <0 0x10200300 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c3: i2c3@1100f000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x1100f000 0 0x1000>, + <0 0x10200480 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c4: i2c4@11011000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11011000 0 0x1000>, + <0 0x10200580 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c5: i2c5@11016000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11016000 0 0x1000>, + <0 0x10200700 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c6: i2c6@1100d000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x1100d000 0 0x1000>, + <0 0x10200800 0 0x100>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c7: i2c7@11004000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10200900 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + i2c8: i2c8@11005000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10200A80 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + status = "okay"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11014000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11014000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11015000 { + compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11015000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MAINPLL_D5>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + imp_iic_wrap: clock-controller@11017000 { + compatible = "mediatek,mt8186-imp_iic_wrap"; + reg = <0 0x11017000 0 0x1000>; + #clock-cells = <1>; + }; + + uart2: serial@11018000 { + compatible = "mediatek,mt8186-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + i2c9: i2c9@11019000 { + compatible = "mediatek,mt8186-i2c"; + reg = <0 0x11019000 0 0x1000>, + <0 0x10200c00 0 0x180>; + interrupts = ; + clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, + <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <1>; + status = "disabled"; + }; + + xhci0: usb@11200000 { + compatible = "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; + mediatek,syscon-wakeup = <&pericfg 0x420 2>; + wakeup-source; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, + <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; + clock-names = "source", "hclk", "source_cg", "ahb_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8186-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + xhci1: usb@11280000 { + compatible = "mediatek,mt8186-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11280000 0 0x1000>, + <0 0x11283e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + mediatek,syscon-wakeup = <&pericfg 0x424 2>; + wakeup-source; + status = "disabled"; + }; + + u3phy0: t-phy@11c80000 { + compatible = "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11c80000 0x1000>; + status = "disabled"; + + u2port1: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port1: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy1: t-phy@11ca0000 { + compatible = "mediatek,mt8186-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11ca0000 0x1000>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,discth = <0x8>; + }; + }; + + mfgsys: clock-controller@13000000 { + compatible = "mediatek,mt8186-mfgsys"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8186-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wpesys: clock-controller@14020000 { + compatible = "mediatek,mt8186-wpesys"; + reg = <0 0x14020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1: clock-controller@15020000 { + compatible = "mediatek,mt8186-imgsys1"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys2: clock-controller@15820000 { + compatible = "mediatek,mt8186-imgsys2"; + reg = <0 0x15820000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@1602f000 { + compatible = "mediatek,mt8186-vdecsys"; + reg = <0 0x1602f000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt8186-vencsys"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt8186-camsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: clock-controller@1a04f000 { + compatible = "mediatek,mt8186-camsys_rawa"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1a06f000 { + compatible = "mediatek,mt8186-camsys_rawb"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; + }; + + mdpsys: clock-controller@1b000000 { + compatible = "mediatek,mt8186-mdpsys"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1c000000 { + compatible = "mediatek,mt8186-ipesys"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +};