From patchwork Tue May 10 11:55:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= X-Patchwork-Id: 12844909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6DBEC433F5 for ; Tue, 10 May 2022 11:56:21 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.325533.548140 (Exim 4.92) (envelope-from ) id 1noOTL-0006Ez-4j; Tue, 10 May 2022 11:56:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 325533.548140; Tue, 10 May 2022 11:56:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1noOTL-0006Es-1h; Tue, 10 May 2022 11:56:11 +0000 Received: by outflank-mailman (input) for mailman id 325533; Tue, 10 May 2022 11:56:09 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1noOTJ-0006Eh-Jv for xen-devel@lists.xenproject.org; Tue, 10 May 2022 11:56:09 +0000 Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2ac8f4b2-d058-11ec-8fc4-03012f2f19d4; Tue, 10 May 2022 13:56:05 +0200 (CEST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id C08E33200035; Tue, 10 May 2022 07:56:01 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Tue, 10 May 2022 07:56:02 -0400 Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 10 May 2022 07:55:59 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2ac8f4b2-d058-11ec-8fc4-03012f2f19d4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:from:from:in-reply-to:message-id :mime-version:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1652183761; x=1652270161; bh=l470sTk6AYbXl/5StCvjUCS8xfxEHkh+cnC xv6SFlLs=; b=ZCUmZT3Os/s28TZniTUEc9go6riZk3N372WE1HduPF3qrdmJawx av0VkpNGQHtuzo4YPQFvGfd/BbSg0ZjFzEiqg4JXnZrmJAOxbt3ONgRGHspa723V 9O3cggoTMIx77F4SMAKXxa7qfYTHTjdgWUnB1fF1lv86zpv93M0BsBbe/Z59AbXh Lxdnar9tCi/Y6jEBHnAKMHDVgkSAFkEcZMrfiBZuhboW9QE5ABuPIIbJEJNRmVyk ukDXMVWmNFI3jkUwsiBasRN2bq+UgdwN5VoqVj+lvxeC7hF32Mm18BdPnz3ciayP /DTIqeBSMCU/C/ZZOdrLjDWmOMjaruyWblg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrgedugdegudcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffogggtgfesthekredtredtjeenucfhrhhomhepofgrrhgvkhcu ofgrrhgtiiihkhhofihskhhiqdfikphrvggtkhhiuceomhgrrhhmrghrvghksehinhhvih hsihgslhgvthhhihhnghhslhgrsgdrtghomheqnecuggftrfgrthhtvghrnhepleekhfdu leetleelleetteevfeefteffkeetteejheelgfegkeelgeehhfdthedvnecuvehluhhsth gvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepmhgrrhhmrghrvghksehi nhhvihhsihgslhgvthhhihhnghhslhgrsgdrtghomh X-ME-Proxy: From: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= To: xen-devel@lists.xenproject.org Cc: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 1/2] ns16550: reject IRQ above nr_irqs_gsi Date: Tue, 10 May 2022 13:55:45 +0200 Message-Id: <20220510115546.1779279-1-marmarek@invisiblethingslab.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Intel LPSS has INTERRUPT_LINE set to 0xff by default, that can't possibly work. While a proper IRQ configuration may be useful, validating value retrieved from the hardware is still necessary. If it fails, use the device in poll mode, instead of crashing down the line (at smp_initr_init()). Currently it's x86-specific, as the surrounding code is guarded with CONFIG_X86 anyway. Signed-off-by: Marek Marczykowski-Górecki --- Changes in v2: - add log message - extend commit message - code style fix --- xen/drivers/char/ns16550.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index fb75cee4a13a..0c6f6ec43de1 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1238,6 +1238,15 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) pci_conf_read8(PCI_SBDF(0, b, d, f), PCI_INTERRUPT_LINE) : 0; + if ( uart->irq >= nr_irqs_gsi ) + { + printk(XENLOG_WARNING + "ns16550: %02x:%02x.%u reports invalid IRQ %d, " + "falling back to a poll mode\n", + b, d, f, uart->irq); + uart->irq = 0; + } + return 0; } } From patchwork Tue May 10 11:55:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Marczykowski-G=C3=B3recki?= X-Patchwork-Id: 12844910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4988C433FE for ; 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Signed-off-by: Marek Marczykowski-Górecki Acked-by: Andrew Cooper --- Changes in v2: - new patch, adding more IDs to the patch that went in already --- xen/drivers/char/ns16550.c | 80 +++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 0c6f6ec43de1..b4486a4e8768 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1077,12 +1077,90 @@ static const struct ns16550_config __initconst uart_config[] = .dev_id = 0x0358, .param = param_exar_xr17v358 }, - /* Intel Corp. TGL-LP LPSS PCI */ + /* Intel Corp. TGL-LP LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa0a8, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-LP LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa0a9, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-LP LPSS PCI UART #2 */ { .vendor_id = PCI_VENDOR_ID_INTEL, .dev_id = 0xa0c7, .param = param_intel_lpss }, + /* Intel Corp. TGL-H LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a8, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-H LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a9, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-H LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a7, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51a8, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51a9, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51c7, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #3 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51da, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7aa8, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7aa9, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7afe, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #3 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7adc, + .param = param_intel_lpss + }, }; static int __init