From patchwork Tue May 10 17:30:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCBC9C43219 for ; Tue, 10 May 2022 17:31:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348261AbiEJRfe (ORCPT ); Tue, 10 May 2022 13:35:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348257AbiEJRfb (ORCPT ); Tue, 10 May 2022 13:35:31 -0400 Received: from mail-qv1-xf36.google.com (mail-qv1-xf36.google.com [IPv6:2607:f8b0:4864:20::f36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4E6043EE4 for ; Tue, 10 May 2022 10:31:21 -0700 (PDT) Received: by mail-qv1-xf36.google.com with SMTP id l1so10715711qvh.1 for ; Tue, 10 May 2022 10:31:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GMr8b4BmAHS+DUXpg+0Wt80r4ZRRFaNc2qGGf+i+Pr4=; b=tuHY9M8DoxY2gOeu8yyeCuF0hVOPQlZwaH5l4ETuPbDu5S80E5MyAU261fYe8KjYDj hGzxv5Kf+/ggXg2u0afvUWm7zJ5gIlMv9KNBmYcpf4O2kVwPJGNGdG4o/8mRUceoXTFq W5pTrflJKMubFxI+NBun8iYpwFi3LFWDR/MP0h60SE+IQ41aQbG2lNCcSib3/ormQOeu s8P9qmAjQ1LtG2AGUo7ey58o6uMdXNqh9XafLooskY15Q34Upg27is17hWuqS++wnDYl N4G3nRtDpdR3GyZ6TNeHcCj4AP3TQftaMekXy74OFUEg1eoQ6GIF93D3BU985vh70Lox 94Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GMr8b4BmAHS+DUXpg+0Wt80r4ZRRFaNc2qGGf+i+Pr4=; b=mGqCvEUAvJqi73LB4lWy/nGmIvssY7u7om6ohEqszdzl076UR8p7bRFnshgJtFuY/I mj2cNvgkncIcpqxj9sfGSyAwn14yaRb2qW0oyqP2AVCE8kgx5/1JlbLldiEZ+YfNMkU1 AmM/LfrUXShE0nv/8YlMiTKBDs91JT1r8I4HRCNbhFeYa4GDBpVTagPTmQJiq8CSsOd+ pT2i3w6G0I0k/Hx0tz7F1HPunW5ez74hnWZPtQUSRNHpRF9mGd3FM8JDyPm/Fvumzn5W ohbUKBy1GPZlzm9pkt4w+Jv+NYRmw1dFIb3PRXh80S4AxsKt5TLwUc7rC/bhdQ4FQYNR Bvcg== X-Gm-Message-State: AOAM533J7QJ6Lw46Aybfybi2yef3+ESyhkGH3KKNI/BnOoyRbAFy36FF vJM3EL72nqFDzagf6h4LaoNn0RwXTOo/7g== X-Google-Smtp-Source: ABdhPJwAT3ySmpvbs0JZzW8gSefBjLJOHI/9odB/A0U86xyRB/Wb7FOWu8Q3JZBXqPfKAMabyt55MQ== X-Received: by 2002:a05:6214:108b:b0:456:38b0:7ba6 with SMTP id o11-20020a056214108b00b0045638b07ba6mr18715845qvr.84.1652203880800; Tue, 10 May 2022 10:31:20 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:20 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Syed Nayyar Waris Subject: [PATCH 1/8] counter: 104-quad-8: Utilize iomap interface Date: Tue, 10 May 2022 13:30:53 -0400 Message-Id: <861c003318dce3d2bef4061711643bb04f5ec14f.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Cc: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- drivers/counter/104-quad-8.c | 169 ++++++++++++++++++----------------- 1 file changed, 89 insertions(+), 80 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index a17e51d65aca..43dde9abfdcf 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -63,7 +63,7 @@ struct quad8 { unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; unsigned int index_polarity[QUAD8_NUM_COUNTERS]; unsigned int cable_fault_enable; - unsigned int base; + void __iomem *base; }; #define QUAD8_REG_INTERRUPT_STATUS 0x10 @@ -118,8 +118,8 @@ static int quad8_signal_read(struct counter_device *counter, if (signal->id < 16) return -EINVAL; - state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) - & BIT(signal->id - 16); + state = ioread8(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) & + BIT(signal->id - 16); *level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; @@ -130,14 +130,14 @@ static int quad8_count_read(struct counter_device *counter, struct counter_count *count, u64 *val) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id; + void __iomem *const base_offset = priv->base + 2 * count->id; unsigned int flags; unsigned int borrow; unsigned int carry; unsigned long irqflags; int i; - flags = inb(base_offset + 1); + flags = ioread8(base_offset + 1); borrow = flags & QUAD8_FLAG_BT; carry = !!(flags & QUAD8_FLAG_CT); @@ -147,11 +147,11 @@ static int quad8_count_read(struct counter_device *counter, spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer; transfer Counter to Output Latch */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, - base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, + base_offset + 1); for (i = 0; i < 3; i++) - *val |= (unsigned long)inb(base_offset) << (8 * i); + *val |= (unsigned long)ioread8(base_offset) << (8 * i); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -162,7 +162,7 @@ static int quad8_count_write(struct counter_device *counter, struct counter_count *count, u64 val) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id; + void __iomem *const base_offset = priv->base + 2 * count->id; unsigned long irqflags; int i; @@ -173,27 +173,27 @@ static int quad8_count_write(struct counter_device *counter, spin_lock_irqsave(&priv->lock, irqflags); /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); /* Counter can only be set via Preset Register */ for (i = 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), base_offset); /* Transfer Preset Register to Counter */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); /* Set Preset Register back to original value */ val = priv->preset[count->id]; for (i = 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), base_offset); /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -246,7 +246,7 @@ static int quad8_function_write(struct counter_device *counter, unsigned int *const quadrature_mode = priv->quadrature_mode + id; unsigned int *const scale = priv->quadrature_scale + id; unsigned int *const synchronous_mode = priv->synchronous_mode + id; - const int base_offset = priv->base + 2 * id + 1; + void __iomem *const base_offset = priv->base + 2 * id + 1; unsigned long irqflags; unsigned int mode_cfg; unsigned int idr_cfg; @@ -266,7 +266,7 @@ static int quad8_function_write(struct counter_device *counter, if (*synchronous_mode) { *synchronous_mode = 0; /* Disable synchronous function mode */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); } } else { *quadrature_mode = 1; @@ -292,7 +292,7 @@ static int quad8_function_write(struct counter_device *counter, } /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -305,10 +305,10 @@ static int quad8_direction_read(struct counter_device *counter, { const struct quad8 *const priv = counter_priv(counter); unsigned int ud_flag; - const unsigned int flag_addr = priv->base + 2 * count->id + 1; + void __iomem *const flag_addr = priv->base + 2 * count->id + 1; /* U/D flag: nonzero = up, zero = down */ - ud_flag = inb(flag_addr) & QUAD8_FLAG_UD; + ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD; *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD; @@ -402,7 +402,7 @@ static int quad8_events_configure(struct counter_device *counter) struct counter_event_node *event_node; unsigned int next_irq_trigger; unsigned long ior_cfg; - unsigned long base_offset; + void __iomem *base_offset; spin_lock_irqsave(&priv->lock, irqflags); @@ -438,13 +438,13 @@ static int quad8_events_configure(struct counter_device *counter) priv->preset_enable[event_node->channel] << 1 | priv->irq_trigger[event_node->channel] << 3; base_offset = priv->base + 2 * event_node->channel + 1; - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); /* Enable IRQ line */ irq_enabled |= BIT(event_node->channel); } - outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -508,7 +508,7 @@ static int quad8_index_polarity_set(struct counter_device *counter, { struct quad8 *const priv = counter_priv(counter); const size_t channel_id = signal->id - 16; - const int base_offset = priv->base + 2 * channel_id + 1; + void __iomem *const base_offset = priv->base + 2 * channel_id + 1; unsigned long irqflags; unsigned int idr_cfg = index_polarity << 1; @@ -519,7 +519,7 @@ static int quad8_index_polarity_set(struct counter_device *counter, priv->index_polarity[channel_id] = index_polarity; /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -549,7 +549,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, { struct quad8 *const priv = counter_priv(counter); const size_t channel_id = signal->id - 16; - const int base_offset = priv->base + 2 * channel_id + 1; + void __iomem *const base_offset = priv->base + 2 * channel_id + 1; unsigned long irqflags; unsigned int idr_cfg = synchronous_mode; @@ -566,7 +566,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, priv->synchronous_mode[channel_id] = synchronous_mode; /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -614,7 +614,7 @@ static int quad8_count_mode_write(struct counter_device *counter, struct quad8 *const priv = counter_priv(counter); unsigned int count_mode; unsigned int mode_cfg; - const int base_offset = priv->base + 2 * count->id + 1; + void __iomem *const base_offset = priv->base + 2 * count->id + 1; unsigned long irqflags; /* Map Generic Counter count mode to 104-QUAD-8 count mode */ @@ -648,7 +648,7 @@ static int quad8_count_mode_write(struct counter_device *counter, mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3; /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -669,7 +669,7 @@ static int quad8_count_enable_write(struct counter_device *counter, struct counter_count *count, u8 enable) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id; + void __iomem *const base_offset = priv->base + 2 * count->id; unsigned long irqflags; unsigned int ior_cfg; @@ -681,7 +681,7 @@ static int quad8_count_enable_write(struct counter_device *counter, priv->irq_trigger[count->id] << 3; /* Load I/O control configuration */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -697,9 +697,9 @@ static int quad8_error_noise_get(struct counter_device *counter, struct counter_count *count, u32 *noise_error) { const struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id + 1; + void __iomem *const base_offset = priv->base + 2 * count->id + 1; - *noise_error = !!(inb(base_offset) & QUAD8_FLAG_E); + *noise_error = !!(ioread8(base_offset) & QUAD8_FLAG_E); return 0; } @@ -717,17 +717,17 @@ static int quad8_count_preset_read(struct counter_device *counter, static void quad8_preset_register_set(struct quad8 *const priv, const int id, const unsigned int preset) { - const unsigned int base_offset = priv->base + 2 * id; + void __iomem *const base_offset = priv->base + 2 * id; int i; priv->preset[id] = preset; /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); /* Set Preset Register */ for (i = 0; i < 3; i++) - outb(preset >> (8 * i), base_offset); + iowrite8(preset >> (8 * i), base_offset); } static int quad8_count_preset_write(struct counter_device *counter, @@ -816,7 +816,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, u8 preset_enable) { struct quad8 *const priv = counter_priv(counter); - const int base_offset = priv->base + 2 * count->id + 1; + void __iomem *const base_offset = priv->base + 2 * count->id + 1; unsigned long irqflags; unsigned int ior_cfg; @@ -831,7 +831,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, priv->irq_trigger[count->id] << 3; /* Load I/O control configuration to Input / Output Control Register */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -858,7 +858,7 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter, } /* Logic 0 = cable fault */ - status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + status = ioread8(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -899,7 +899,8 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter, /* Enable is active low in Differential Encoder Cable Status register */ cable_fault_enable = ~priv->cable_fault_enable; - outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(cable_fault_enable, + priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -923,7 +924,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, { struct quad8 *const priv = counter_priv(counter); const size_t channel_id = signal->id / 2; - const int base_offset = priv->base + 2 * channel_id; + void __iomem *const base_offset = priv->base + 2 * channel_id; unsigned long irqflags; spin_lock_irqsave(&priv->lock, irqflags); @@ -931,12 +932,12 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, priv->fck_prescaler[channel_id] = prescaler; /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); /* Set filter clock factor */ - outb(prescaler, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); + iowrite8(prescaler, base_offset); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + base_offset + 1); spin_unlock_irqrestore(&priv->lock, irqflags); @@ -1084,12 +1085,12 @@ static irqreturn_t quad8_irq_handler(int irq, void *private) { struct counter_device *counter = private; struct quad8 *const priv = counter_priv(counter); - const unsigned long base = priv->base; + void __iomem *const base = priv->base; unsigned long irq_status; unsigned long channel; u8 event; - irq_status = inb(base + QUAD8_REG_INTERRUPT_STATUS); + irq_status = ioread8(base + QUAD8_REG_INTERRUPT_STATUS); if (!irq_status) return IRQ_NONE; @@ -1118,17 +1119,43 @@ static irqreturn_t quad8_irq_handler(int irq, void *private) } /* Clear pending interrupts on device */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); return IRQ_HANDLED; } +static void quad8_init_counter(void __iomem *const base_offset) +{ + unsigned long i; + + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + /* Reset filter clock factor */ + iowrite8(0, base_offset); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + base_offset + 1); + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + /* Reset Preset Register */ + for (i = 0; i < 3; i++) + iowrite8(0x00, base_offset); + /* Reset Borrow, Carry, Compare, and Sign flags */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); + /* Reset Error flag */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); + /* Binary encoding; Normal count; non-quadrature mode */ + iowrite8(QUAD8_CTR_CMR, base_offset + 1); + /* Disable A and B inputs; preset on index; FLG1 as Carry */ + iowrite8(QUAD8_CTR_IOR, base_offset + 1); + /* Disable index function; negative index polarity */ + iowrite8(QUAD8_CTR_IDR, base_offset + 1); +} + static int quad8_probe(struct device *dev, unsigned int id) { struct counter_device *counter; struct quad8 *priv; - int i, j; - unsigned int base_offset; + unsigned long i; int err; if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) { @@ -1142,6 +1169,10 @@ static int quad8_probe(struct device *dev, unsigned int id) return -ENOMEM; priv = counter_priv(counter); + priv->base = devm_ioport_map(dev, base[id], QUAD8_EXTENT); + if (!priv->base) + return -ENOMEM; + /* Initialize Counter device and driver data */ counter->name = dev_name(dev); counter->parent = dev; @@ -1150,43 +1181,21 @@ static int quad8_probe(struct device *dev, unsigned int id) counter->num_counts = ARRAY_SIZE(quad8_counts); counter->signals = quad8_signals; counter->num_signals = ARRAY_SIZE(quad8_signals); - priv->base = base[id]; spin_lock_init(&priv->lock); /* Reset Index/Interrupt Register */ - outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(0x00, priv->base + QUAD8_REG_INDEX_INTERRUPT); /* Reset all counters and disable interrupt function */ - outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, priv->base + QUAD8_REG_CHAN_OP); /* Set initial configuration for all counters */ - for (i = 0; i < QUAD8_NUM_COUNTERS; i++) { - base_offset = base[id] + 2 * i; - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset filter clock factor */ - outb(0, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset Preset Register */ - for (j = 0; j < 3; j++) - outb(0x00, base_offset); - /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); - /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); - /* Binary encoding; Normal count; non-quadrature mode */ - outb(QUAD8_CTR_CMR, base_offset + 1); - /* Disable A and B inputs; preset on index; FLG1 as Carry */ - outb(QUAD8_CTR_IOR, base_offset + 1); - /* Disable index function; negative index polarity */ - outb(QUAD8_CTR_IDR, base_offset + 1); - } + for (i = 0; i < QUAD8_NUM_COUNTERS; i++) + quad8_init_counter(priv->base + 2 * i); /* Disable Differential Encoder Cable Status for all channels */ - outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(0xFF, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); /* Enable all counters and enable interrupt function */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, + priv->base + QUAD8_REG_CHAN_OP); err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, IRQF_SHARED, counter->name, counter); From patchwork Tue May 10 17:30:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19A3FC433F5 for ; Tue, 10 May 2022 17:31:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239114AbiEJRfe (ORCPT ); Tue, 10 May 2022 13:35:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348258AbiEJRfb (ORCPT ); Tue, 10 May 2022 13:35:31 -0400 Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFDC84507F for ; Tue, 10 May 2022 10:31:22 -0700 (PDT) Received: by mail-qt1-x829.google.com with SMTP id t16so14049154qtr.9 for ; Tue, 10 May 2022 10:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bGocoAF4XnDshiIFwV2UZS9TD3DaSuUYN+zlu0xXJbk=; b=F9CRF4WkRUCxKWi+OaY2dPbGEQmUQz6J7M77VupTCPKmE79pxzAfkFGa0h+w0iHlwi v4LnIT9iNqOMIvTWQcXpV/J9Kgd6aDkX/wJz+pekpBWDH3jatuMqzhhOpxGBuzvk9/eW bRKoic0IHtRa0L2QqY9NFqkhbyFufoV/I1FRNJnDhjGy8eHtxZ5y+9nnYoeSYT4n/dfV BnHXGZ7EIJdhLe10cd3XjTqqgh4aFd4n5C3SA/JwDG0qgfge2JViqCgsaFKgtiMTbHta dvEomHDGJMwfsHe0VVo0I24iPpsNwp2dOv3RocpQzPMGGfSBCFSxwtOD8RzymP7j1FAS 3sYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bGocoAF4XnDshiIFwV2UZS9TD3DaSuUYN+zlu0xXJbk=; b=wpOL/CAdaEVjkELmh5ln1B0HR3i/+tkOkpKdn7Vx3BtuOzlzJDKqFx9fH9byULMbw0 dSDqDTtnsxMK4Jh+ub2NGfuVQ167VH9GlOICV0x2ShnMjqE2zGEpbYrkrxAVZqnRD5VN P8SRJsRFkBNGkEi5oXc79InFFwYE1QqWfz2j6MoT6h57Ba7imrbsGEhoaCUjhiUHkSRt g0MjQ+kglIQ8STSQdtZzNCWmYWK+JW1Wdue68orMHuHt2vrgCKWR6Y+ltdogEqPYyI5I duuMPxlwnpgTo77WCsWhkNmOyI0RxVloPT1nhzXYObFUuiP70HXUi4EsO0S5Sn7KcsDO Medg== X-Gm-Message-State: AOAM533iybGnG1gvFey4AOe0kOSmD/YcG5qtu3hZcG/LSoLQQ5vXAqrJ UDXb9e/LyrzaE3ltxKvjgbBOHdh7jm4hrQ== X-Google-Smtp-Source: ABdhPJy5RQkWywaRqfa0z64Zh9FS8XQyNqa+2kkzAzAadQ4ALqgkMC+5ABn4xV4HXIs+3d8d0qlibQ== X-Received: by 2002:ac8:598a:0:b0:2f3:cbf4:7b4e with SMTP id e10-20020ac8598a000000b002f3cbf47b4emr18654814qte.449.1652203881569; Tue, 10 May 2022 10:31:21 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:21 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 2/8] gpio: 104-dio-48e: Utilize iomap interface Date: Tue, 10 May 2022 13:30:54 -0400 Message-Id: <8bc6e7d2fef9f0c320580dd8266eb27da2670feb.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-104-dio-48e.c | 63 +++++++++++++++++---------------- 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/gpio/gpio-104-dio-48e.c b/drivers/gpio/gpio-104-dio-48e.c index 6bf41040c41f..f118ad9bcd33 100644 --- a/drivers/gpio/gpio-104-dio-48e.c +++ b/drivers/gpio/gpio-104-dio-48e.c @@ -49,7 +49,7 @@ struct dio48e_gpio { unsigned char out_state[6]; unsigned char control[2]; raw_spinlock_t lock; - unsigned int base; + void __iomem *base; unsigned char irq_mask; }; @@ -70,7 +70,7 @@ static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offs struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); const unsigned int io_port = offset / 8; const unsigned int control_port = io_port / 3; - const unsigned int control_addr = dio48egpio->base + 3 + control_port * 4; + void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4; unsigned long flags; unsigned int control; @@ -95,9 +95,9 @@ static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offs } control = BIT(7) | dio48egpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, control_addr); control &= ~BIT(7); - outb(control, control_addr); + iowrite8(control, control_addr); raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); @@ -111,7 +111,7 @@ static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int off const unsigned int io_port = offset / 8; const unsigned int control_port = io_port / 3; const unsigned int mask = BIT(offset % 8); - const unsigned int control_addr = dio48egpio->base + 3 + control_port * 4; + void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4; const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port; unsigned long flags; unsigned int control; @@ -142,12 +142,12 @@ static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int off dio48egpio->out_state[io_port] &= ~mask; control = BIT(7) | dio48egpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, control_addr); - outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port); + iowrite8(dio48egpio->out_state[io_port], dio48egpio->base + out_port); control &= ~BIT(7); - outb(control, control_addr); + iowrite8(control, control_addr); raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); @@ -171,7 +171,7 @@ static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset) return -EINVAL; } - port_state = inb(dio48egpio->base + in_port); + port_state = ioread8(dio48egpio->base + in_port); raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); @@ -186,7 +186,7 @@ static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip); unsigned long offset; unsigned long gpio_mask; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; /* clear bits array to a clean slate */ @@ -194,7 +194,7 @@ static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { port_addr = dio48egpio->base + ports[offset / 8]; - port_state = inb(port_addr) & gpio_mask; + port_state = ioread8(port_addr) & gpio_mask; bitmap_set_value8(bits, port_state, offset); } @@ -217,7 +217,7 @@ static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int val else dio48egpio->out_state[port] &= ~mask; - outb(dio48egpio->out_state[port], dio48egpio->base + out_port); + iowrite8(dio48egpio->out_state[port], dio48egpio->base + out_port); raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); } @@ -229,7 +229,7 @@ static void dio48e_gpio_set_multiple(struct gpio_chip *chip, unsigned long offset; unsigned long gpio_mask; size_t index; - unsigned int port_addr; + void __iomem *port_addr; unsigned long bitmask; unsigned long flags; @@ -244,7 +244,7 @@ static void dio48e_gpio_set_multiple(struct gpio_chip *chip, /* update output state data and set device gpio register */ dio48egpio->out_state[index] &= ~gpio_mask; dio48egpio->out_state[index] |= bitmask; - outb(dio48egpio->out_state[index], port_addr); + iowrite8(dio48egpio->out_state[index], port_addr); raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); } @@ -274,7 +274,7 @@ static void dio48e_irq_mask(struct irq_data *data) if (!dio48egpio->irq_mask) /* disable interrupts */ - inb(dio48egpio->base + 0xB); + ioread8(dio48egpio->base + 0xB); raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); } @@ -294,8 +294,8 @@ static void dio48e_irq_unmask(struct irq_data *data) if (!dio48egpio->irq_mask) { /* enable interrupts */ - outb(0x00, dio48egpio->base + 0xF); - outb(0x00, dio48egpio->base + 0xB); + iowrite8(0x00, dio48egpio->base + 0xF); + iowrite8(0x00, dio48egpio->base + 0xB); } if (offset == 19) @@ -341,7 +341,7 @@ static irqreturn_t dio48e_irq_handler(int irq, void *dev_id) raw_spin_lock(&dio48egpio->lock); - outb(0x00, dio48egpio->base + 0xF); + iowrite8(0x00, dio48egpio->base + 0xF); raw_spin_unlock(&dio48egpio->lock); @@ -373,7 +373,7 @@ static int dio48e_irq_init_hw(struct gpio_chip *gc) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc); /* Disable IRQ by default */ - inb(dio48egpio->base + 0xB); + ioread8(dio48egpio->base + 0xB); return 0; } @@ -395,6 +395,10 @@ static int dio48e_probe(struct device *dev, unsigned int id) return -EBUSY; } + dio48egpio->base = devm_ioport_map(dev, base[id], DIO48E_EXTENT); + if (!dio48egpio->base) + return -ENOMEM; + dio48egpio->chip.label = name; dio48egpio->chip.parent = dev; dio48egpio->chip.owner = THIS_MODULE; @@ -408,7 +412,6 @@ static int dio48e_probe(struct device *dev, unsigned int id) dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple; dio48egpio->chip.set = dio48e_gpio_set; dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple; - dio48egpio->base = base[id]; girq = &dio48egpio->chip.irq; girq->chip = &dio48e_irqchip; @@ -423,16 +426,16 @@ static int dio48e_probe(struct device *dev, unsigned int id) raw_spin_lock_init(&dio48egpio->lock); /* initialize all GPIO as output */ - outb(0x80, base[id] + 3); - outb(0x00, base[id]); - outb(0x00, base[id] + 1); - outb(0x00, base[id] + 2); - outb(0x00, base[id] + 3); - outb(0x80, base[id] + 7); - outb(0x00, base[id] + 4); - outb(0x00, base[id] + 5); - outb(0x00, base[id] + 6); - outb(0x00, base[id] + 7); + iowrite8(0x80, dio48egpio->base + 3); + iowrite8(0x00, dio48egpio->base); + iowrite8(0x00, dio48egpio->base + 1); + iowrite8(0x00, dio48egpio->base + 2); + iowrite8(0x00, dio48egpio->base + 3); + iowrite8(0x80, dio48egpio->base + 7); + iowrite8(0x00, dio48egpio->base + 4); + iowrite8(0x00, dio48egpio->base + 5); + iowrite8(0x00, dio48egpio->base + 6); + iowrite8(0x00, dio48egpio->base + 7); err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio); if (err) { From patchwork Tue May 10 17:30:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97433C4332F for ; Tue, 10 May 2022 17:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348276AbiEJRff (ORCPT ); Tue, 10 May 2022 13:35:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348265AbiEJRfb (ORCPT ); Tue, 10 May 2022 13:35:31 -0400 Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 762BB36B66 for ; Tue, 10 May 2022 10:31:23 -0700 (PDT) Received: by mail-qt1-x82a.google.com with SMTP id o18so14055196qtk.7 for ; Tue, 10 May 2022 10:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Dp773USXqVyyiKXPdjKnqOpvmUov/JtSiRinsH2S0Gc=; b=R1u5ol4k8XrpPnnPuo8fgHEHhOQIWJTbJCzfSzG45TXL4G1RQLas3JH2euBe5CZkyB ZHy0AphUsiVk4j6mgMP0ddccQCbrY4NXtt6R/pY1tOhIkZ54HDNIhUlSeM7LH/lNjea/ SVY8Cyp4fN8EAvET5tk2Mpzsq9J/mPnI6cg8VFwN/WMpqWIRvJWWdtE6CFcvPPM5cBkE C+6oEfjnD0P1Dg4Dfe6BNWLjAJFvrgfPUi3gSAFiuYzY3Ab3gyk3omFdNo321KdizCsK 7LBgyiQ7/df4nA1AmNuGHBF8ks2PH5DNANi5p6Cd/3n9UkXlfWkpsnZIADBOMScA8oqX Vbuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Dp773USXqVyyiKXPdjKnqOpvmUov/JtSiRinsH2S0Gc=; b=dd71UeOXR5E6RPwNsULXiRqvENdMnP/jzHv6XEFmiRwIhXS0+4k8Pl3jhezlxGhM3K KRqEIYi3uUX/QoGb/c+mLSOxGj6R6BIv+Vos1v8qi7+Wo3phcyx6nK7sOOliQ8XXd6Dq ZX5kAWGbobbBk539buOLkFqNAOQG0gXdxZJJla17f8Tw5oL+YMMHKgLsZl2zlZ1Q6v7r llFIRAPcaW7hF6nFuSyYMSN5Z8997tX57B21JKVJuDx7eM9440qi5jcUZK+d3s2uObLY uKZKdSBThFYWukuiF4k1xSnYsBCabDTWb6XWiU9p/SaxXaEYjenPXl6Ipcv0uVii//6m n2QA== X-Gm-Message-State: AOAM530jzJ+VK9Jfge5n9tV2SWJNHNfyWrdc4Au+81HLbnlBZnqWypyW wwPk7yn2RE86ikEQ+8dLlMp1hUh/74E/bQ== X-Google-Smtp-Source: ABdhPJyaOMPUXrLX4jwVkNgym0/oA/GePiD78bI0k2HI9pkktZLs0mGazb5+MEuzhiCAFYnxt4HMyA== X-Received: by 2002:ac8:5f88:0:b0:2f3:b80c:a7a4 with SMTP id j8-20020ac85f88000000b002f3b80ca7a4mr20932274qta.38.1652203882313; Tue, 10 May 2022 10:31:22 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:22 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 3/8] gpio: 104-idi-48: Utilize iomap interface Date: Tue, 10 May 2022 13:30:55 -0400 Message-Id: <09e2418d2dcf93c45a70c3a0a1fe7fdd8104a689.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-104-idi-48.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-104-idi-48.c b/drivers/gpio/gpio-104-idi-48.c index 34be7dd9f5b9..9521ece3ebef 100644 --- a/drivers/gpio/gpio-104-idi-48.c +++ b/drivers/gpio/gpio-104-idi-48.c @@ -47,7 +47,7 @@ struct idi_48_gpio { raw_spinlock_t lock; spinlock_t ack_lock; unsigned char irq_mask[6]; - unsigned base; + void __iomem *base; unsigned char cos_enb; }; @@ -66,15 +66,15 @@ static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset) struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip); unsigned i; static const unsigned int register_offset[6] = { 0, 1, 2, 4, 5, 6 }; - unsigned base_offset; + void __iomem *port_addr; unsigned mask; for (i = 0; i < 48; i += 8) if (offset < i + 8) { - base_offset = register_offset[i / 8]; + port_addr = idi48gpio->base + register_offset[i / 8]; mask = BIT(offset - i); - return !!(inb(idi48gpio->base + base_offset) & mask); + return !!(ioread8(port_addr) & mask); } /* The following line should never execute since offset < 48 */ @@ -88,7 +88,7 @@ static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, unsigned long offset; unsigned long gpio_mask; static const size_t ports[] = { 0, 1, 2, 4, 5, 6 }; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; /* clear bits array to a clean slate */ @@ -96,7 +96,7 @@ static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { port_addr = idi48gpio->base + ports[offset / 8]; - port_state = inb(port_addr) & gpio_mask; + port_state = ioread8(port_addr) & gpio_mask; bitmap_set_value8(bits, port_state, offset); } @@ -130,7 +130,7 @@ static void idi_48_irq_mask(struct irq_data *data) raw_spin_lock_irqsave(&idi48gpio->lock, flags); - outb(idi48gpio->cos_enb, idi48gpio->base + 7); + iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7); raw_spin_unlock_irqrestore(&idi48gpio->lock, flags); } @@ -163,7 +163,7 @@ static void idi_48_irq_unmask(struct irq_data *data) raw_spin_lock_irqsave(&idi48gpio->lock, flags); - outb(idi48gpio->cos_enb, idi48gpio->base + 7); + iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7); raw_spin_unlock_irqrestore(&idi48gpio->lock, flags); } @@ -204,7 +204,7 @@ static irqreturn_t idi_48_irq_handler(int irq, void *dev_id) raw_spin_lock(&idi48gpio->lock); - cos_status = inb(idi48gpio->base + 7); + cos_status = ioread8(idi48gpio->base + 7); raw_spin_unlock(&idi48gpio->lock); @@ -250,8 +250,8 @@ static int idi_48_irq_init_hw(struct gpio_chip *gc) struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc); /* Disable IRQ by default */ - outb(0, idi48gpio->base + 7); - inb(idi48gpio->base + 7); + iowrite8(0, idi48gpio->base + 7); + ioread8(idi48gpio->base + 7); return 0; } @@ -273,6 +273,10 @@ static int idi_48_probe(struct device *dev, unsigned int id) return -EBUSY; } + idi48gpio->base = devm_ioport_map(dev, base[id], IDI_48_EXTENT); + if (!idi48gpio->base) + return -ENOMEM; + idi48gpio->chip.label = name; idi48gpio->chip.parent = dev; idi48gpio->chip.owner = THIS_MODULE; @@ -283,7 +287,6 @@ static int idi_48_probe(struct device *dev, unsigned int id) idi48gpio->chip.direction_input = idi_48_gpio_direction_input; idi48gpio->chip.get = idi_48_gpio_get; idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple; - idi48gpio->base = base[id]; girq = &idi48gpio->chip.irq; girq->chip = &idi_48_irqchip; From patchwork Tue May 10 17:30:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 847C6C43217 for ; Tue, 10 May 2022 17:31:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245227AbiEJRfi (ORCPT ); Tue, 10 May 2022 13:35:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348266AbiEJRfc (ORCPT ); Tue, 10 May 2022 13:35:32 -0400 Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 353294704E for ; Tue, 10 May 2022 10:31:24 -0700 (PDT) Received: by mail-qv1-xf2d.google.com with SMTP id e17so13096357qvj.11 for ; Tue, 10 May 2022 10:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dAiResiSDR0UVkYFGpWdpsHXqinI6QYsvByx1jrEmYs=; b=SmmF/FWHV+dCZpxlqQIcq5MpAYpbVHs5XeWkXs50nvqsMsfMPAe20HNuw3lb9DmnCz nhR6Oh9i33Nnl+dkQGXcQy1UsSS+1JCKWlv71waan9SGO3QIc6qUv1hYJ4faRLFUOzgO Vrd9i7LcUnn2HaSymBKkBrRTjtwFyAZxwiByr11d554bO+pxIwEnsEXucjXiL9t+JV+m oD2vsa5ZTVWEJqOow2LE9V7Oq9vl46IDGqW/Mw1BOa0+pLIo/VXC/XbedDb0PJlW0Ev+ am3BzMDXimMibkr9AqJSkGnpBtX14wbczsUEnUwe+l5Y8AkYK46iauj3sC+bLWBYZrQX M4Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dAiResiSDR0UVkYFGpWdpsHXqinI6QYsvByx1jrEmYs=; b=ePP8y3zO8ZNvavCkQ967GhISDEhCBQs9kWufoz8alFOuCw7pIc40Ld2pU2TB9HE5MU VCIlb9YAnyHwhu8GUoFYoljWL1fxiC7VyL6dSnLEIE/jWDf7v9+InuFi+AkOXqJ8ZuUO CYlDWtdwqqWnEsdena5V2C2rfmaROkLjPUUTGiX7gbTnV/bsnLar2UKrxLi09xv1O/5h lZ6nfDJv1FcDSnHlf7jtBA6juh39QURfDIGXHP8zxYNoHrwo/lrfw6gHd6r0MlqojHR0 IX9bmd1VW4St8RN38f0kO/K2MoaYiCQscMErj5g+qaAVHmP9+XtZ4eMah7l77ilA2/pG 3imw== X-Gm-Message-State: AOAM531ph1DCPkr/vlz7jElPuxqbK3T3PuJZOiJwn5pOb/UKgnNapp1c fmVcIjMxDO5u4OqmMsqaL3uN85Xxz79nKA== X-Google-Smtp-Source: ABdhPJza0jR2kpJcC/r1piienpe1i5hTVSk12hHR973c1jA2x/FkiKwoSb4zCs2oaY70NW9rwOk6Ig== X-Received: by 2002:a05:6214:21e1:b0:440:fa7a:493e with SMTP id p1-20020a05621421e100b00440fa7a493emr18645248qvj.55.1652203883031; Tue, 10 May 2022 10:31:23 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:22 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 4/8] gpio: 104-idio-16: Utilize iomap interface Date: Tue, 10 May 2022 13:30:56 -0400 Message-Id: <1aed489e67526819d9f5c5a11f4bb3a172acd1f1.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-104-idio-16.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-104-idio-16.c b/drivers/gpio/gpio-104-idio-16.c index c68ed1a135fa..45f7ad8573e1 100644 --- a/drivers/gpio/gpio-104-idio-16.c +++ b/drivers/gpio/gpio-104-idio-16.c @@ -44,7 +44,7 @@ struct idio_16_gpio { struct gpio_chip chip; raw_spinlock_t lock; unsigned long irq_mask; - unsigned int base; + void __iomem *base; unsigned int out_state; }; @@ -79,9 +79,9 @@ static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset) return -EINVAL; if (offset < 24) - return !!(inb(idio16gpio->base + 1) & mask); + return !!(ioread8(idio16gpio->base + 1) & mask); - return !!(inb(idio16gpio->base + 5) & (mask>>8)); + return !!(ioread8(idio16gpio->base + 5) & (mask>>8)); } static int idio_16_gpio_get_multiple(struct gpio_chip *chip, @@ -91,9 +91,9 @@ static int idio_16_gpio_get_multiple(struct gpio_chip *chip, *bits = 0; if (*mask & GENMASK(23, 16)) - *bits |= (unsigned long)inb(idio16gpio->base + 1) << 16; + *bits |= (unsigned long)ioread8(idio16gpio->base + 1) << 16; if (*mask & GENMASK(31, 24)) - *bits |= (unsigned long)inb(idio16gpio->base + 5) << 24; + *bits |= (unsigned long)ioread8(idio16gpio->base + 5) << 24; return 0; } @@ -116,9 +116,9 @@ static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset, idio16gpio->out_state &= ~mask; if (offset > 7) - outb(idio16gpio->out_state >> 8, idio16gpio->base + 4); + iowrite8(idio16gpio->out_state >> 8, idio16gpio->base + 4); else - outb(idio16gpio->out_state, idio16gpio->base); + iowrite8(idio16gpio->out_state, idio16gpio->base); raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -135,9 +135,9 @@ static void idio_16_gpio_set_multiple(struct gpio_chip *chip, idio16gpio->out_state |= *mask & *bits; if (*mask & 0xFF) - outb(idio16gpio->out_state, idio16gpio->base); + iowrite8(idio16gpio->out_state, idio16gpio->base); if ((*mask >> 8) & 0xFF) - outb(idio16gpio->out_state >> 8, idio16gpio->base + 4); + iowrite8(idio16gpio->out_state >> 8, idio16gpio->base + 4); raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -158,7 +158,7 @@ static void idio_16_irq_mask(struct irq_data *data) if (!idio16gpio->irq_mask) { raw_spin_lock_irqsave(&idio16gpio->lock, flags); - outb(0, idio16gpio->base + 2); + iowrite8(0, idio16gpio->base + 2); raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -177,7 +177,7 @@ static void idio_16_irq_unmask(struct irq_data *data) if (!prev_irq_mask) { raw_spin_lock_irqsave(&idio16gpio->lock, flags); - inb(idio16gpio->base + 2); + ioread8(idio16gpio->base + 2); raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -212,7 +212,7 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id) raw_spin_lock(&idio16gpio->lock); - outb(0, idio16gpio->base + 1); + iowrite8(0, idio16gpio->base + 1); raw_spin_unlock(&idio16gpio->lock); @@ -232,8 +232,8 @@ static int idio_16_irq_init_hw(struct gpio_chip *gc) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc); /* Disable IRQ by default */ - outb(0, idio16gpio->base + 2); - outb(0, idio16gpio->base + 1); + iowrite8(0, idio16gpio->base + 2); + iowrite8(0, idio16gpio->base + 1); return 0; } @@ -255,6 +255,10 @@ static int idio_16_probe(struct device *dev, unsigned int id) return -EBUSY; } + idio16gpio->base = devm_ioport_map(dev, base[id], IDIO_16_EXTENT); + if (!idio16gpio->base) + return -ENOMEM; + idio16gpio->chip.label = name; idio16gpio->chip.parent = dev; idio16gpio->chip.owner = THIS_MODULE; @@ -268,7 +272,6 @@ static int idio_16_probe(struct device *dev, unsigned int id) idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple; idio16gpio->chip.set = idio_16_gpio_set; idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple; - idio16gpio->base = base[id]; idio16gpio->out_state = 0xFFFF; girq = &idio16gpio->chip.irq; From patchwork Tue May 10 17:30:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29DC6C433FE for ; Tue, 10 May 2022 17:31:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348266AbiEJRfj (ORCPT ); Tue, 10 May 2022 13:35:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348269AbiEJRfc (ORCPT ); Tue, 10 May 2022 13:35:32 -0400 Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B33DE483BF for ; Tue, 10 May 2022 10:31:24 -0700 (PDT) Received: by mail-qk1-x736.google.com with SMTP id k8so8570714qki.8 for ; Tue, 10 May 2022 10:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H2AK5sECXXWOxpJaFbUfWcwhgtP35mSHuJJkQivb894=; b=VcKW5OAEtI9CIIGbpJVturNwnTEXXxGHV15anSA7hIHQNL8i+uXg1rRWq5C3e94fZ0 P+9fP2H/Jy+DHF5Nk/I9YsLyWm9PRGMXopfp6qAucu6aoDwMtNTGJFyNBRowGI3dJvAP JHKNdUYERax1iYceZ1cTZzfn5qR4Bzs6VPuY4ZLtvfPNncpu1R5DJsklss8fdztFoPg0 7Cribio15rvAGrbr8TXCBubM4A24nK1EnQx8XxHN5tlzrPGan24EVzUp4BoxQfav2xE0 R2W4xUzZWygvNbcZEeTOlkFxDkjetJEGog2gcoJyCRda2+0e4fe4l9sFnWBquTaHzmot 54VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H2AK5sECXXWOxpJaFbUfWcwhgtP35mSHuJJkQivb894=; b=OQNQN9V80Vp5pDno7V5BOj0JRhVkUik3rPW4vSxW2rCvMlSgDT2cy7jexAgS2kyA/S 1foIoArMY5dHpWkCDQwPbTHerTEEIlltAQjqM2hPOKEen/rwJh4xwEPQumfLKGnH4Lb4 LiNvc/NoMNwllLtxQNjJ2HjDJATc6b0g2JDCfS3cIXNacELQd++wUzPghEPQ58JQ0FNu 0oRVozMsUnnJ5/er0xmMBpjXjDAbNaGgFg/fdh0acKR586ftG0Sa/I3CQ8SmKY5ZgwIv 0eaypp0LVg/mtJolnX4gGrhM4JW1akQnvS8S5h2awHSVIvT4gwCxEYKMEouxFXu3PxE2 arrw== X-Gm-Message-State: AOAM530iOEEj9wrzgvggl0LGBaz+zOk5PlzFJ3imELFuVj51prkGlyg3 zBH10tjXak4QFwtqlHa/61EuglSCBRyajg== X-Google-Smtp-Source: ABdhPJx9VrK2hOiDY6jNzkQ/GWTB+b92TOrNM9oe99NIxVJ138UceIhQn9xggxOFs+XzKDFvrIfirg== X-Received: by 2002:a37:bbc4:0:b0:69b:db2c:c962 with SMTP id l187-20020a37bbc4000000b0069bdb2cc962mr16165564qkf.565.1652203883755; Tue, 10 May 2022 10:31:23 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:23 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 5/8] gpio: gpio-mm: Utilize iomap interface Date: Tue, 10 May 2022 13:30:57 -0400 Message-Id: <1b274435871047e85fc8bbbf15840424632c47d0.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-gpio-mm.c | 43 +++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/gpio-gpio-mm.c b/drivers/gpio/gpio-gpio-mm.c index b89b8c5ff1f5..097a06463d01 100644 --- a/drivers/gpio/gpio-gpio-mm.c +++ b/drivers/gpio/gpio-gpio-mm.c @@ -42,7 +42,7 @@ struct gpiomm_gpio { unsigned char out_state[6]; unsigned char control[2]; spinlock_t lock; - unsigned int base; + void __iomem *base; }; static int gpiomm_gpio_get_direction(struct gpio_chip *chip, @@ -64,7 +64,6 @@ static int gpiomm_gpio_direction_input(struct gpio_chip *chip, struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip); const unsigned int io_port = offset / 8; const unsigned int control_port = io_port / 3; - const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4; unsigned long flags; unsigned int control; @@ -89,7 +88,7 @@ static int gpiomm_gpio_direction_input(struct gpio_chip *chip, } control = BIT(7) | gpiommgpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, gpiommgpio->base + 3 + control_port*4); spin_unlock_irqrestore(&gpiommgpio->lock, flags); @@ -103,7 +102,6 @@ static int gpiomm_gpio_direction_output(struct gpio_chip *chip, const unsigned int io_port = offset / 8; const unsigned int control_port = io_port / 3; const unsigned int mask = BIT(offset % 8); - const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4; const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port; unsigned long flags; unsigned int control; @@ -134,9 +132,9 @@ static int gpiomm_gpio_direction_output(struct gpio_chip *chip, gpiommgpio->out_state[io_port] &= ~mask; control = BIT(7) | gpiommgpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, gpiommgpio->base + 3 + control_port*4); - outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port); + iowrite8(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port); spin_unlock_irqrestore(&gpiommgpio->lock, flags); @@ -160,7 +158,7 @@ static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset) return -EINVAL; } - port_state = inb(gpiommgpio->base + in_port); + port_state = ioread8(gpiommgpio->base + in_port); spin_unlock_irqrestore(&gpiommgpio->lock, flags); @@ -175,7 +173,7 @@ static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip); unsigned long offset; unsigned long gpio_mask; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; /* clear bits array to a clean slate */ @@ -183,7 +181,7 @@ static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { port_addr = gpiommgpio->base + ports[offset / 8]; - port_state = inb(port_addr) & gpio_mask; + port_state = ioread8(port_addr) & gpio_mask; bitmap_set_value8(bits, port_state, offset); } @@ -207,7 +205,7 @@ static void gpiomm_gpio_set(struct gpio_chip *chip, unsigned int offset, else gpiommgpio->out_state[port] &= ~mask; - outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port); + iowrite8(gpiommgpio->out_state[port], gpiommgpio->base + out_port); spin_unlock_irqrestore(&gpiommgpio->lock, flags); } @@ -219,7 +217,7 @@ static void gpiomm_gpio_set_multiple(struct gpio_chip *chip, unsigned long offset; unsigned long gpio_mask; size_t index; - unsigned int port_addr; + void __iomem *port_addr; unsigned long bitmask; unsigned long flags; @@ -234,7 +232,7 @@ static void gpiomm_gpio_set_multiple(struct gpio_chip *chip, /* update output state data and set device gpio register */ gpiommgpio->out_state[index] &= ~gpio_mask; gpiommgpio->out_state[index] |= bitmask; - outb(gpiommgpio->out_state[index], port_addr); + iowrite8(gpiommgpio->out_state[index], port_addr); spin_unlock_irqrestore(&gpiommgpio->lock, flags); } @@ -268,6 +266,10 @@ static int gpiomm_probe(struct device *dev, unsigned int id) return -EBUSY; } + gpiommgpio->base = devm_ioport_map(dev, base[id], GPIOMM_EXTENT); + if (!gpiommgpio->base) + return -ENOMEM; + gpiommgpio->chip.label = name; gpiommgpio->chip.parent = dev; gpiommgpio->chip.owner = THIS_MODULE; @@ -281,7 +283,6 @@ static int gpiomm_probe(struct device *dev, unsigned int id) gpiommgpio->chip.get_multiple = gpiomm_gpio_get_multiple; gpiommgpio->chip.set = gpiomm_gpio_set; gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple; - gpiommgpio->base = base[id]; spin_lock_init(&gpiommgpio->lock); @@ -292,14 +293,14 @@ static int gpiomm_probe(struct device *dev, unsigned int id) } /* initialize all GPIO as output */ - outb(0x80, base[id] + 3); - outb(0x00, base[id]); - outb(0x00, base[id] + 1); - outb(0x00, base[id] + 2); - outb(0x80, base[id] + 7); - outb(0x00, base[id] + 4); - outb(0x00, base[id] + 5); - outb(0x00, base[id] + 6); + iowrite8(0x80, gpiommgpio->base + 3); + iowrite8(0x00, gpiommgpio->base); + iowrite8(0x00, gpiommgpio->base + 1); + iowrite8(0x00, gpiommgpio->base + 2); + iowrite8(0x80, gpiommgpio->base + 7); + iowrite8(0x00, gpiommgpio->base + 4); + iowrite8(0x00, gpiommgpio->base + 5); + iowrite8(0x00, gpiommgpio->base + 6); return 0; } From patchwork Tue May 10 17:30:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845342 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D782C433EF for ; Tue, 10 May 2022 17:31:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348259AbiEJRfl (ORCPT ); Tue, 10 May 2022 13:35:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348274AbiEJRfc (ORCPT ); Tue, 10 May 2022 13:35:32 -0400 Received: from mail-qt1-x82f.google.com (mail-qt1-x82f.google.com [IPv6:2607:f8b0:4864:20::82f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 731BE488A0 for ; Tue, 10 May 2022 10:31:24 -0700 (PDT) Received: by mail-qt1-x82f.google.com with SMTP id hf18so14095993qtb.0 for ; Tue, 10 May 2022 10:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=69H/OSOuPn7SmYjJsCkxqhmQsUZwmRmjFUMtoE7YesE=; b=UT+BIGsLrpFrpGwMeYdjS97ZGaREc9gwyhtxzyet08ZimzRKyOOa0e+1CNB67SAGbU w1IVgmYhZ5Ignn3dFihVaNdxfa898WyL87Y1HBgKBnDXNuek4lPWXk/oBEXskF1veNub gRBA62IXTJM2T7SdXZVgoV9rLAm6eOTAYFsJNUE5DDISL2BN60BjO8ZIQhR8zcoWl+fB bGfxS8V9P7LulhcGYOkoC5tt1il0S3W0jrVjIT0Ushl1xUcIOvlYxI9kyH4wxet2pOaC gX6U4wwCP/x3rJkW4j6X83iPpkObOVm7HRhksWRbH2subi2D2XnoNiZm53IrpVT6ICWN AGGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=69H/OSOuPn7SmYjJsCkxqhmQsUZwmRmjFUMtoE7YesE=; b=AaQiug4f1PUFVLTmq3wbQsDAGO9K75crK3Ua5Mu1zayoleXliS9LfRhYNIjR/sL31U 4a7YkaYf5u7gq7yAzHbE5r68/j1tChYLJSkeTDLZ4ae1XXqTy9y/SOzt1OUSxFmBTREj FdP1q6LGcjPv5P69lLoi+iy0zIDIf8QufeKUt4eegyPhdQY4G+VJ30oz2+X1ynlXR66d MhBRiJ7gHriMi4kIerwhaZmY7BLguSuP+Qa/E7esMwxs1e1zsr8jwReMJNT3mvYlLfbs M2QkPWQ9jpZKuDPuiV8Tw1EHe17DkYfmgjFLgsgAm2a2p0ohFJi5bGJQEkbR/7WWsZdL ow2g== X-Gm-Message-State: AOAM5339AlVgVGubYDxcaZgiiDyJUGuEyO5uNdvjoetMCTrDKNOGBYcw 3pxCkFiEAIPx0sQEJ3sv/oxmA5JDuUEk5g== X-Google-Smtp-Source: ABdhPJww3LD3FhZdBaUtwi6pBZUOxCPehLydw6w/Tx9Ck8N1/994c9xJszrkobMjbAMq8ml43XWqmQ== X-Received: by 2002:a05:622a:54d:b0:2f3:ce29:234a with SMTP id m13-20020a05622a054d00b002f3ce29234amr15998280qtx.559.1652203884456; Tue, 10 May 2022 10:31:24 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:24 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 6/8] gpio: ws16c48: Utilize iomap interface Date: Tue, 10 May 2022 13:30:58 -0400 Message-Id: <817800777df540e6d92b4b8aec832e68488a4eaf.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-ws16c48.c | 65 +++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/drivers/gpio/gpio-ws16c48.c b/drivers/gpio/gpio-ws16c48.c index bb02a82e22f4..5078631d8014 100644 --- a/drivers/gpio/gpio-ws16c48.c +++ b/drivers/gpio/gpio-ws16c48.c @@ -47,7 +47,7 @@ struct ws16c48_gpio { raw_spinlock_t lock; unsigned long irq_mask; unsigned long flow_mask; - unsigned base; + void __iomem *base; }; static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) @@ -73,7 +73,7 @@ static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ws16c48gpio->io_state[port] |= mask; ws16c48gpio->out_state[port] &= ~mask; - outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); + iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); @@ -95,7 +95,7 @@ static int ws16c48_gpio_direction_output(struct gpio_chip *chip, ws16c48gpio->out_state[port] |= mask; else ws16c48gpio->out_state[port] &= ~mask; - outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); + iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); @@ -118,7 +118,7 @@ static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset) return -EINVAL; } - port_state = inb(ws16c48gpio->base + port); + port_state = ioread8(ws16c48gpio->base + port); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); @@ -131,7 +131,7 @@ static int ws16c48_gpio_get_multiple(struct gpio_chip *chip, struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip); unsigned long offset; unsigned long gpio_mask; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; /* clear bits array to a clean slate */ @@ -139,7 +139,7 @@ static int ws16c48_gpio_get_multiple(struct gpio_chip *chip, for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { port_addr = ws16c48gpio->base + offset / 8; - port_state = inb(port_addr) & gpio_mask; + port_state = ioread8(port_addr) & gpio_mask; bitmap_set_value8(bits, port_state, offset); } @@ -166,7 +166,7 @@ static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ws16c48gpio->out_state[port] |= mask; else ws16c48gpio->out_state[port] &= ~mask; - outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); + iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -178,7 +178,7 @@ static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, unsigned long offset; unsigned long gpio_mask; size_t index; - unsigned int port_addr; + void __iomem *port_addr; unsigned long bitmask; unsigned long flags; @@ -195,7 +195,7 @@ static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, /* update output state data and set device gpio register */ ws16c48gpio->out_state[index] &= ~gpio_mask; ws16c48gpio->out_state[index] |= bitmask; - outb(ws16c48gpio->out_state[index], port_addr); + iowrite8(ws16c48gpio->out_state[index], port_addr); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -219,10 +219,10 @@ static void ws16c48_irq_ack(struct irq_data *data) port_state = ws16c48gpio->irq_mask >> (8*port); - outb(0x80, ws16c48gpio->base + 7); - outb(port_state & ~mask, ws16c48gpio->base + 8 + port); - outb(port_state | mask, ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(port_state & ~mask, ws16c48gpio->base + 8 + port); + iowrite8(port_state | mask, ws16c48gpio->base + 8 + port); + iowrite8(0xC0, ws16c48gpio->base + 7); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -244,9 +244,9 @@ static void ws16c48_irq_mask(struct irq_data *data) ws16c48gpio->irq_mask &= ~mask; - outb(0x80, ws16c48gpio->base + 7); - outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); + iowrite8(0xC0, ws16c48gpio->base + 7); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -268,9 +268,9 @@ static void ws16c48_irq_unmask(struct irq_data *data) ws16c48gpio->irq_mask |= mask; - outb(0x80, ws16c48gpio->base + 7); - outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); + iowrite8(0xC0, ws16c48gpio->base + 7); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -304,9 +304,9 @@ static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) return -EINVAL; } - outb(0x40, ws16c48gpio->base + 7); - outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x40, ws16c48gpio->base + 7); + iowrite8(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port); + iowrite8(0xC0, ws16c48gpio->base + 7); raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); @@ -330,20 +330,20 @@ static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id) unsigned long int_id; unsigned long gpio; - int_pending = inb(ws16c48gpio->base + 6) & 0x7; + int_pending = ioread8(ws16c48gpio->base + 6) & 0x7; if (!int_pending) return IRQ_NONE; /* loop until all pending interrupts are handled */ do { for_each_set_bit(port, &int_pending, 3) { - int_id = inb(ws16c48gpio->base + 8 + port); + int_id = ioread8(ws16c48gpio->base + 8 + port); for_each_set_bit(gpio, &int_id, 8) generic_handle_domain_irq(chip->irq.domain, gpio + 8*port); } - int_pending = inb(ws16c48gpio->base + 6) & 0x7; + int_pending = ioread8(ws16c48gpio->base + 6) & 0x7; } while (int_pending); return IRQ_HANDLED; @@ -370,11 +370,11 @@ static int ws16c48_irq_init_hw(struct gpio_chip *gc) struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc); /* Disable IRQ by default */ - outb(0x80, ws16c48gpio->base + 7); - outb(0, ws16c48gpio->base + 8); - outb(0, ws16c48gpio->base + 9); - outb(0, ws16c48gpio->base + 10); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(0, ws16c48gpio->base + 8); + iowrite8(0, ws16c48gpio->base + 9); + iowrite8(0, ws16c48gpio->base + 10); + iowrite8(0xC0, ws16c48gpio->base + 7); return 0; } @@ -396,6 +396,10 @@ static int ws16c48_probe(struct device *dev, unsigned int id) return -EBUSY; } + ws16c48gpio->base = devm_ioport_map(dev, base[id], WS16C48_EXTENT); + if (!ws16c48gpio->base) + return -ENOMEM; + ws16c48gpio->chip.label = name; ws16c48gpio->chip.parent = dev; ws16c48gpio->chip.owner = THIS_MODULE; @@ -409,7 +413,6 @@ static int ws16c48_probe(struct device *dev, unsigned int id) ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple; ws16c48gpio->chip.set = ws16c48_gpio_set; ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple; - ws16c48gpio->base = base[id]; girq = &ws16c48gpio->chip.irq; girq->chip = &ws16c48_irqchip; From patchwork Tue May 10 17:30:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E1A4C43217 for ; Tue, 10 May 2022 17:31:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348257AbiEJRfl (ORCPT ); Tue, 10 May 2022 13:35:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348277AbiEJRfc (ORCPT ); Tue, 10 May 2022 13:35:32 -0400 Received: from mail-qv1-xf34.google.com (mail-qv1-xf34.google.com [IPv6:2607:f8b0:4864:20::f34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B3A74B856 for ; Tue, 10 May 2022 10:31:26 -0700 (PDT) Received: by mail-qv1-xf34.google.com with SMTP id p3so11599271qvi.7 for ; Tue, 10 May 2022 10:31:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=seOjmihEBRKsZp4b34pJA/ndUMIaVSf7C6FlpVBGPxk=; b=wmwYtqg29pKeFXBRyIVmMMB5jXw+g9NzFNeJb3vvTmD7qXtMYZRgrQrL8PieMDygNo h+dqTmyo22/puKrfK8c21hUSNlBFmGBhZYngefgcyRMWYm+Gucxwz4IYLFZ/CnvXKN+A 5ebu2EVI9eBbBge4y0/Q1JE1Z7GLGJRKjEY6MBuzTRELfaotpjuYYx5y/yjXtJYyfR+B RVA6ARVZQtRAn7WpXSOHv7w23TWVU498vBwfJBj4S9nRIkcSwTwarukhZV8Zg5RSlqjT dw/Rq015C1K4/5bSG7oYv2QGMtSe2S0iMBJjDNSfcIvFFBwOay4mpQKyxe5xIH59HvjJ bZ6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=seOjmihEBRKsZp4b34pJA/ndUMIaVSf7C6FlpVBGPxk=; b=Z0W4BKkqSpByn+CBBkJZlqXxtT4zI4+tRI7lD4dR4iYjOb/Bux8fKpg88ZfPLlgfBX 1oQsv5iqYjJMB1uABCvp7knZ/O+ieLhfMTUzXckzJnHrfTSSgg6vVNxyMBV2ZWX3QLlv 9+GAq/n4+QE/wMhYZnQ/zIyvs+sTBbQsA+YK17TUIFFNnxhVk9LgdbgSHSYiFJXGPpO8 fqmNY6OqE9kHr8p1qeku/Ozj+/orhKl11D+5D+MF4kkcG3HX5aGhvA72aVSaaI7dDusY HeyYwUTQ0FvEbjI6pKcoDQwzsJ2HpaqDIQEVr3HMds0MO4hXYnSBXBSAtz7pQpfb1GPc 47rw== X-Gm-Message-State: AOAM530/PaDU8Lzq05mf6O6E/MTT35xe14RNSSD45sPqwkGZdZFaZzzx AdKWQOMsQvUF3EDwY6x22G66pCC8HZLSuA== X-Google-Smtp-Source: ABdhPJzZQJHFV8UJ1NPGzpYgeWXgn4ciBhy6e9TckMU1/L3vVDqbAWahmnq8VC8unCEvQMTOrR0teQ== X-Received: by 2002:a05:6214:c6f:b0:45a:a2f2:6d23 with SMTP id t15-20020a0562140c6f00b0045aa2f26d23mr19357429qvj.55.1652203885151; Tue, 10 May 2022 10:31:25 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:24 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Jonathan Cameron , Lars-Peter Clausen Subject: [PATCH 7/8] iio: adc: stx104: Utilize iomap interface Date: Tue, 10 May 2022 13:30:59 -0400 Message-Id: <64673797df382c52fc32fce24348b25a0b05e73a.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray --- drivers/iio/adc/stx104.c | 56 +++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 55bd2dc514e9..7552351bfed9 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -51,7 +51,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - unsigned int base; + void __iomem *base; }; /** @@ -64,7 +64,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - unsigned int base; + void __iomem *base; unsigned int out_state; }; @@ -79,7 +79,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); gain = adc_config & 0x3; *val = 1 << gain; @@ -91,24 +91,24 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } /* select ADC channel */ - outb(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); /* trigger ADC sample capture and wait for completion */ - outb(0, priv->base); - while (inb(priv->base + 8) & BIT(7)); + iowrite8(0, priv->base); + while (ioread8(priv->base + 8) & BIT(7)); - *val = inw(priv->base); + *val = ioread16(priv->base); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); adbu = !(adc_config & BIT(2)); *val = -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); adbu = !(adc_config & BIT(2)); gain = adc_config & 0x3; @@ -130,16 +130,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - outb(0, priv->base + 11); + iowrite8(0, priv->base + 11); break; case 2: - outb(1, priv->base + 11); + iowrite8(1, priv->base + 11); break; case 4: - outb(2, priv->base + 11); + iowrite8(2, priv->base + 11); break; case 8: - outb(3, priv->base + 11); + iowrite8(3, priv->base + 11); break; default: return -EINVAL; @@ -153,7 +153,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - outw(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, priv->base + 4 + 2 * chan->channel); return 0; } @@ -222,7 +222,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset) if (offset >= 4) return -EINVAL; - return !!(inb(stx104gpio->base) & BIT(offset)); + return !!(ioread8(stx104gpio->base) & BIT(offset)); } static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, @@ -230,7 +230,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, { struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip); - *bits = inb(stx104gpio->base); + *bits = ioread8(stx104gpio->base); return 0; } @@ -252,7 +252,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset, else stx104gpio->out_state &= ~mask; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -279,7 +279,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *chip, stx104gpio->out_state &= ~*mask; stx104gpio->out_state |= *mask & *bits; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -306,11 +306,16 @@ static int stx104_probe(struct device *dev, unsigned int id) return -EBUSY; } + priv = iio_priv(indio_dev); + priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->base) + return -ENOMEM; + indio_dev->info = &stx104_info; indio_dev->modes = INDIO_DIRECT_MODE; /* determine if differential inputs */ - if (inb(base[id] + 8) & BIT(5)) { + if (ioread8(priv->base + 8) & BIT(5)) { indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->channels = stx104_channels_diff; } else { @@ -320,18 +325,15 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->name = dev_name(dev); - priv = iio_priv(indio_dev); - priv->base = base[id]; - /* configure device for software trigger operation */ - outb(0, base[id] + 9); + iowrite8(0, priv->base + 9); /* initialize gain setting to x1 */ - outb(0, base[id] + 11); + iowrite8(0, priv->base + 11); /* initialize DAC output to 0V */ - outw(0, base[id] + 4); - outw(0, base[id] + 6); + iowrite16(0, priv->base + 4); + iowrite16(0, priv->base + 6); stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.parent = dev; @@ -346,7 +348,7 @@ static int stx104_probe(struct device *dev, unsigned int id) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; - stx104gpio->base = base[id] + 3; + stx104gpio->base = priv->base + 3; stx104gpio->out_state = 0x0; spin_lock_init(&stx104gpio->lock); From patchwork Tue May 10 17:31:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 12845340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3346C4332F for ; Tue, 10 May 2022 17:31:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348256AbiEJRfk (ORCPT ); Tue, 10 May 2022 13:35:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348286AbiEJRfe (ORCPT ); Tue, 10 May 2022 13:35:34 -0400 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C59D74BB99 for ; Tue, 10 May 2022 10:31:26 -0700 (PDT) Received: by mail-qk1-x735.google.com with SMTP id a76so13702254qkg.12 for ; Tue, 10 May 2022 10:31:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9mQuOu+XRqgTZ4Bko2jc/5sm39T7MgSYxzJZaxMktN4=; b=ouHq2900hAOqDb+MXC1Fi7kl65Nx7yzrT9leVeMpabMrEqIQJWRkXdzGPa9MrhzZgp MTLF3CPiLjipxh/vVbeL5xkVPQCT1qZRGYAFiarTN5o5K7c8eAaXOsyGUQeKel5mBG7e c82JVNYGzSLTDvLW7PUMqOpg75RvXzORYlLztyEqY1yOmqhVts0Bu49tRizRmCYj2dEb cvXGCtBTqLVqVsfJQWuMpbdk+mIAMXnaO8xGo5WXvHqXToSAYgnWB0i2Ry8fTuMSgJDD WjqURJvLHoasbzFwlwXHeVbCW6ziiR+UCdVNmPnHjtBdhCWZ2eHx/vGVFPaw59YQwX/G XJgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9mQuOu+XRqgTZ4Bko2jc/5sm39T7MgSYxzJZaxMktN4=; b=yw5RbDFrNAtIJZRXza79VKvHzoD6N9fEmE6y+xX+LsqS8/M44rIZkqxHOLAeFm6liz AMyBX1p8D7cchF0ZqtfcEXbPmb8b0fTsSNBndmcRuif4Puj37Eyc/xUVmqGe5VupyM0k 3esEibaKVLvLOr+lcty20TZJ3Dcqo0yp+iLHWwVCrmp0lOuD3Z9ZPZgjgDHZsRJXDUcS FK0ePQ1uVl5VwRi0UwkkNj1cGu0mHambslghiD05rVN7dHH0ALl+J259nhzY/zd4GMRT Rd0G40vcjq6saV5XS3cnRzZP03BjIq1fshXaYUrd4pKcWR3aZtjvAX5O6TAX5YMiFAzH ClwQ== X-Gm-Message-State: AOAM530vYt7OiKL3raM1dWgUyVj3pwCc/Cr4CPnB5HPheX8nHfmr3NoL C6dUuvLeB78X350XX1l8B7YZ+MUUyNk2ag== X-Google-Smtp-Source: ABdhPJzMHkLzUtYji99bKeJH7gAfpbWZHkXB9Hva/GQb4rz2ewUZZpaYjPU3mC+JFj3OZ+aSg7rn+A== X-Received: by 2002:a37:55c2:0:b0:479:8293:d7d0 with SMTP id j185-20020a3755c2000000b004798293d7d0mr16425698qkb.182.1652203885821; Tue, 10 May 2022 10:31:25 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:25 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Jonathan Cameron , Lars-Peter Clausen Subject: [PATCH 8/8] iio: dac: cio-dac: Utilize iomap interface Date: Tue, 10 May 2022 13:31:00 -0400 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray --- drivers/iio/dac/cio-dac.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/iio/dac/cio-dac.c b/drivers/iio/dac/cio-dac.c index 95813569f394..8080984dcb03 100644 --- a/drivers/iio/dac/cio-dac.c +++ b/drivers/iio/dac/cio-dac.c @@ -41,7 +41,7 @@ MODULE_PARM_DESC(base, "Measurement Computing CIO-DAC base addresses"); */ struct cio_dac_iio { int chan_out_states[CIO_DAC_NUM_CHAN]; - unsigned int base; + void __iomem *base; }; static int cio_dac_read_raw(struct iio_dev *indio_dev, @@ -71,7 +71,7 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - outw(val, priv->base + chan_addr_offset); + iowrite16(val, priv->base + chan_addr_offset); return 0; } @@ -105,18 +105,20 @@ static int cio_dac_probe(struct device *dev, unsigned int id) return -EBUSY; } + priv = iio_priv(indio_dev); + priv->base = devm_ioport_map(dev, base[id], CIO_DAC_EXTENT); + if (!priv->base) + return -ENOMEM; + indio_dev->info = &cio_dac_info; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = cio_dac_channels; indio_dev->num_channels = CIO_DAC_NUM_CHAN; indio_dev->name = dev_name(dev); - priv = iio_priv(indio_dev); - priv->base = base[id]; - /* initialize DAC outputs to 0V */ for (i = 0; i < 32; i += 2) - outw(0, base[id] + i); + iowrite16(0, priv->base + i); return devm_iio_device_register(dev, indio_dev); }