From patchwork Tue May 10 21:33:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F4ECC433F5 for ; Tue, 10 May 2022 21:33:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D85BF10E1AE; Tue, 10 May 2022 21:33:37 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4040010E174; Tue, 10 May 2022 21:33:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652218413; x=1683754413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bIlEdmCPlaX2gZe1NITcJ2yrFM0j4MtDdH8jCnz9COE=; b=GQzJ8uFVQyXfs8hKtKx24Iwp6+K3cu2faGbNkpeypeHmmal70wD+IPwx u1cf8V6SpmBorVJXB0NRW5V536I40fGm3C3YjQbbjQg95uh3p2+RR45Oz sChqVNeDDGkitDm3n2BCE0AUsqygV3ZO5q/LiMQ6B8ZQEL6CAVe7O8gtL sU145Gqs8JdHXWTyq002F9uvn1B4nK8k+ZJu9CBMwl8CWRr6WtGOYC4K3 I2BNPM5ME43dUfv9qK2HtOWMdlYagZ+4hfBHhKlgCdSHwf0RcrMWNa04E uh6CXFMNXwj7nFOLW8Z9sbZR04VqKVh5gqGzygjOnorJjuKs0siFaAyQ3 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="268350062" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="268350062" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 14:33:32 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="593769236" Received: from brauta-mobl1.ger.corp.intel.com (HELO intel.com) ([10.252.50.37]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 14:33:29 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Subject: [PATCH v2 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines Date: Tue, 10 May 2022 23:33:02 +0200 Message-Id: <20220510213304.101055-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220510213304.101055-1-andi.shyti@linux.intel.com> References: <20220510213304.101055-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , Andi Shyti , Matthew Auld , Andi Shyti , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chris Wilson As an extension of the current skip TLB invalidations if the device is powered down, we recognised that prior to any engine activity, all the TLBs are explicitly invalidated. Thus anytime we know the engine is asleep, we can skip invalidating the TLBs on that engine. Signed-off-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h index bc898df7a48cc..2654133b39f22 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h @@ -55,6 +55,10 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt) for (tmp = 1, intel_gt_pm_get(gt); tmp; \ intel_gt_pm_put(gt), tmp = 0) +#define with_intel_gt_pm_if_awake(gt, wf) \ + for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \ + intel_gt_pm_put(gt), tmp = 0) + static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt) { return intel_wakeref_wait_for_idle(>->wakeref); From patchwork Tue May 10 21:33:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EC90C433FE for ; Tue, 10 May 2022 21:33:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F126B10E1B1; Tue, 10 May 2022 21:33:40 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7134710E1B1; Tue, 10 May 2022 21:33:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652218419; x=1683754419; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8Lg/qFI8YCDh3drp3SQBXA/kUsVpG1F4olW0foZVpH0=; b=nMuj23UjjbINZ12b5AcbeIvEDxGeop3pApxxJPTkBEKSFvwhdJZB32N8 Qtzo1GqJb3nEIP+jd9RXIDfaS5ATfVGJlresgSkCqlrwsADzgTrdTPLn1 XTqJlpV8xBjnonNaeLk7I0s85+hySdAQisYhcapRsYkZUUcO6EBjs6i7/ cU2y1gUg1M5QlSlYCTRmSlfpJbrUdoPDGZiBl0Ze1PVPZ5tN9LUvNiTLT jbSVkoPXr9vJsxK9vk1sC08knGPShSVIjeEIyrgoLxD53pgtQ3Mf4N/H5 NT9b68heqYZ14Lt7660wJPUKklMZPZoMvrAwexTRm7AZkrAsmeaJjjqE/ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="250042705" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="250042705" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 14:33:38 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="565851352" Received: from brauta-mobl1.ger.corp.intel.com (HELO intel.com) ([10.252.50.37]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 14:33:35 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Subject: [PATCH v2 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj Date: Tue, 10 May 2022 23:33:03 +0200 Message-Id: <20220510213304.101055-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220510213304.101055-1-andi.shyti@linux.intel.com> References: <20220510213304.101055-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , Andi Shyti , Matthew Auld , Andi Shyti , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" During object cleanup we invalidate the TLBs but we do it only for gt0. Invalidate the caches for all the tiles. Reported-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++--- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 2 +- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 97c820eee115a..37d23e328bd0c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -13,6 +13,7 @@ #include "i915_gem_mman.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_pm.h" void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, struct sg_table *pages, @@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) { struct drm_i915_private *i915 = to_i915(obj->base.dev); - intel_wakeref_t wakeref; + struct intel_gt *gt; + int i; - with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref) - intel_gt_invalidate_tlbs(to_gt(i915)); + for_each_gt(gt, i915, i) { + int tmp; + + with_intel_gt_pm_if_awake(gt, tmp) + intel_gt_invalidate_tlbs(gt); + } } return pages; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h index 2654133b39f22..3b1fbce7ea369 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h @@ -55,7 +55,7 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt) for (tmp = 1, intel_gt_pm_get(gt); tmp; \ intel_gt_pm_put(gt), tmp = 0) -#define with_intel_gt_pm_if_awake(gt, wf) \ +#define with_intel_gt_pm_if_awake(gt, tmp) \ for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \ intel_gt_pm_put(gt), tmp = 0) From patchwork Tue May 10 21:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12845558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 056BBC433EF for ; Tue, 10 May 2022 21:34:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D9A4310E2D2; Tue, 10 May 2022 21:33:58 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9D1510E277; Tue, 10 May 2022 21:33:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652218436; x=1683754436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gQjUa14is2CyA6aL4DZCAMxYlPhFqzuQk6NgkxtmASI=; b=eAoVSt1Wn38iOYON2dVr9isbRuIrX44zZtk2phn9V3YhIFoCJeIL2Sm4 d0dt9KPnjQqY1QVekQGG2jaXduuGd7r29XZj4luTyDHif8wAeH99s9pka Ano3k2yUobOR0pAVL8ejxS8YdS2aVMoXjk1gELEtSXLHUyZmVSM43DH0h A3s+9RcYNxe1MxglLIwWmR2qqdgOViv3hHy3YiwSTxAKnyw1z7P4WdglW I00LVOxjaRU2OVvhqZKoxzJDXl8MvGsC6lHSeiR05xs6F+K8f/RC0mvQv D6FUDhqYJ73U7iu9udLBBNpbhLpAosHb0mVsrPwL/nBZhHNi6QU1nq2QM w==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="251557374" X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="251557374" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 14:33:44 -0700 X-IronPort-AV: E=Sophos;i="5.91,215,1647327600"; d="scan'208";a="565851393" Received: from brauta-mobl1.ger.corp.intel.com (HELO intel.com) ([10.252.50.37]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 14:33:41 -0700 From: Andi Shyti To: Intel GFX , DRI Devel Subject: [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake Date: Tue, 10 May 2022 23:33:04 +0200 Message-Id: <20220510213304.101055-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220510213304.101055-1-andi.shyti@linux.intel.com> References: <20220510213304.101055-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tvrtko Ursulin , Andi Shyti , Matthew Auld , Andi Shyti , Chris Wilson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We want to check if the engine is awake first before invalidating its cache. Suggested-by: Chris Wilson Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 034182f85501b..de26fbe6b71dd 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1219,6 +1219,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) const unsigned int timeout_ms = 4; struct reg_and_bit rb; + if (!intel_engine_pm_is_awake(engine)) + continue; + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); if (!i915_mmio_reg_offset(rb.reg)) continue;